Home Microcontrollers (MCUs) & processors Arm-based processors
Home
Microcontrollers (MCUs) & processors
Arm-based processors
NEW

AM68

ACTIVE

General Purpose SoC with dual core 64-bit Arm Cortex-A72, graphics, 1-port PCIe Gen3, USB3.0

Order now
Data sheet
User guides
Errata

AM68

ACTIVE
Data sheet Order now

Product details

Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors 2 Arm Cortex-R5F CPU 64-bit Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 3 Hardware accelerators 1 video encode/decode accelerator Features General purpose, USB 3.0 Operating system Linux Security Cryptography, Debug security, Device Identity, Secure boot, Secure storage & programming Rating Automotive Power supply solution LP8733 Operating temperature range (°C) -40 to 105
Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors 2 Arm Cortex-R5F CPU 64-bit Graphics acceleration 1 3D Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 3 Hardware accelerators 1 video encode/decode accelerator Features General purpose, USB 3.0 Operating system Linux Security Cryptography, Debug security, Device Identity, Secure boot, Secure storage & programming Rating Automotive Power supply solution LP8733 Operating temperature range (°C) -40 to 105
FCBGA (ALZ) 770 529 mm² 23 x 23

Processor cores:

  • Up to dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex-A72 core
  • Deep Learning Accelerator:
    • Up to 8 Trillion Operations Per Second (TOPS)
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem supports:
    • Up to 4 displays
    • Up to two DSI 4L TX (up to 2.5K)
    • One eDP 4L
    • One DPI 24-bit RGB parallel interface
    • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
    • Safety features such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64, up to 800 MHz
    • 50 GFLOPS, 4 GTexels/s
    • >500 MTexels/s, >8 GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL ES 3.1, Vulkan 1.2
  • Two CSI2.0 4L Camera Serial interface (CSI-Rx) Plus CSI2.- 4L Tx (CSI-Tx) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
    • 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to two 32-bit data bus with inline ECC up to 17 GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • Up to two 512KB on-chip SRAM in MAIN domain, protected by ECC

Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L RX plus Two CSI2.04L TX
  • Two Ethernet RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface (eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

Technology / Package:

  • 16-nm FinFET technology
  • 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

Processor cores:

  • Up to dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex-A72 core
  • Deep Learning Accelerator:
    • Up to 8 Trillion Operations Per Second (TOPS)
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Dual-core Arm Cortex-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI
    • 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM
  • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management
    • 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
    • 480 MPixel/s ISP
    • Support for up to 16-bit input RAW format
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
    • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem supports:
    • Up to 4 displays
    • Up to two DSI 4L TX (up to 2.5K)
    • One eDP 4L
    • One DPI 24-bit RGB parallel interface
    • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
    • Safety features such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • IMG BXS-4-64, up to 800 MHz
    • 50 GFLOPS, 4 GTexels/s
    • >500 MTexels/s, >8 GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL ES 3.1, Vulkan 1.2
  • Two CSI2.0 4L Camera Serial interface (CSI-Rx) Plus CSI2.- 4L Tx (CSI-Tx) with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • Support for 1,2,3, or 4 data lane mode up to 1.5Gbps
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
    • 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s)

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to two 32-bit data bus with inline ECC up to 17 GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • Up to two 512KB on-chip SRAM in MAIN domain, protected by ECC

Device security:

  • Secure boot with secure run-time support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L RX plus Two CSI2.04L TX
  • Two Ethernet RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface (eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

Technology / Package:

  • 16-nm FinFET technology
  • 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

The AM68 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM68x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM68 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to two Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 Trillion Operations Per Second (TOPS) within the lowest power envelope in the industry even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep learning function in the AM68 class of processors.

The AM68 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM68x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM68 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to two Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Key Performance Cores Overview: The C7000™ DSP next generation core (“C7x”) combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 Trillion Operations Per Second (TOPS) within the lowest power envelope in the industry even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep learning function in the AM68 class of processors.

filter Find other Arm-based processors
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 19
Type Title Date
* Data sheet AM68x Processors, Silicon Revision 1.0 datasheet (Rev. A) PDF | HTML 18 Aug 2023
* Errata J721S2, TDA4VE, TDA4AL, TDA4VL, AM68A Processor Silicon Errata (Rev. B) PDF | HTML 20 May 2023
* User guide J721S2, TDA4AL, TDA4VL, TDA4VE, AM68A Technical Reference Manual (Rev. C) PDF | HTML 26 Jun 2023
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application brief 智慧多顯示器系統的五個主要設計考量 PDF | HTML 09 Apr 2024
Application brief 스마트 다중 디스플레이 시스템을 위한 5가지 설계 고려 사항 PDF | HTML 09 Apr 2024
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 04 Apr 2024
Application brief Top Five Design Considerations for Smart Multi-display Systems PDF | HTML 22 Mar 2024
White paper General Purpose processors for high compute, graphics, and connectivity applications PDF | HTML 20 Mar 2024
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15 Nov 2023
White paper Securing Arm-Based Application Processors (Rev. E) 09 Nov 2023
User guide AM68 Power Estimation Tool User’s Guide (Rev. A) PDF | HTML 16 May 2023
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. E) PDF | HTML 15 May 2023
Application note AM68x Processor Power Solutions Using LP87334E PMIC for Industrial Applications PDF | HTML 14 Mar 2023
Application note Jacinto7 DDRSS Register Configuration Tool (Rev. B) PDF | HTML 30 Jan 2023
User guide SK-AM68 Process Starter Kit User's Guide PDF | HTML 05 Jan 2023
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 18 Aug 2020
Application note OSPI Tuning Procedure PDF | HTML 08 Jul 2020
Application note Jacinto 7 High-Speed Interface Layout Guidelines 04 Oct 2019

Design & development

Please view the Design & development section on a desktop.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos