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Design Rule Verification Report

Date : 11/25/2013
Time : 1:32:35 PM
Elapsed Time : 00:00:01
Filename : C:\Userdata\PA\TI Designs\0 - Working\ADS1247_RTD\Altium\ADS1247_3-Wire RTD_HWcomp\ADS1247_3-Wire RTD_HWcomp.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Clearance Constraint (Gap=7mil) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Width Constraint (Min=6mil) (Max=200mil) (Preferred=12mil) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Total 0