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CD4001UB

ACTIVE

4-ch, 2-input, 3-V to 18-V NOR gates

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Data sheet

CD4001UB

ACTIVE
Data sheet Order now

Product details

Technology family CD4000 Number of channels 4 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Output type Push-Pull Input type Standard CMOS Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125
Technology family CD4000 Number of channels 4 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Output type Push-Pull Input type Standard CMOS Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Propagation delay time = 30 ns (typ.) at CL = 50 pF, VDD = 10 V
  • Standardized symmetrical output characteristics
  • 100% tested for maximum quiescent current at 20 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings

Data sheet acquired from Harris Semiconductor
  • Propagation delay time = 30 ns (typ.) at CL = 50 pF, VDD = 10 V
  • Standardized symmetrical output characteristics
  • 100% tested for maximum quiescent current at 20 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings

Data sheet acquired from Harris Semiconductor

CD4001UB quad 2-input NOR gate provides the system designer with direct implementation of the NOR function and supplements the existing family of CMOS gates.

The CD4001UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4001UB quad 2-input NOR gate provides the system designer with direct implementation of the NOR function and supplements the existing family of CMOS gates.

The CD4001UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
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Technical documentation

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Type Title Date
* Data sheet CD4001UB TYPES datasheet (Rev. C) 21 Aug 2003
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 03 Dec 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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Information included:
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