Analog Design Journal

Achieving precise nanosecond-level laser pulse control for lidar and ToF systems

By Leaphar Castro, Member Group Technical Staff, and Anant Sinha, application engineer, high-speed amplifiers

In autonomous robots and industrial automation, split-second detection errors could mean missed obstacles, failed inspections and compromised safety. Rise and fall time, propagation delay and pulse-to-pulse stability each create timing errors that compound across thousands of pulses per second. This article walks through practical design steps, including output current setting, bias voltage sizing and damping network optimization to suppress parasitic ringing. Lab results confirm rise and fall times <1 ns, propagation delay variation <50 ps and pulse-to-pulse amplitude variation <2%, enabling millimeter-level spatial resolution under real-world conditions.

How integrated isolated bias modules improve power density and reliability

By Mark Allen Esquillo, marketing manager, and Carter Pollan, applications engineer, high-voltage power

Designing power electronics for electric vehicles, data centers and renewable energy systems means squeezing higher performance into shrinking form factors — where board space, thermal headroom and electrical noise leave little margin for error. Discrete flyback converters force engineers to simultaneously balance transformer sizing, EMI filtering and thermal management, extending development timelines and consuming valuable board area. IsoShield™ technology tackles these trade-offs by embedding the transformer, switching FETs and isolation barrier into a single compact package — cutting solution area up to 70%, improving thermal dissipation up to 30% and reducing vibration-induced mechanical torque by >90% while meeting CISPR 25 Class 5 requirements with minimal external filtering.

Realizing 5G network potential through mMIMO and precise beamforming technology

By Bhavesh Rathod, applications engineer, wireless infrastructure

Squeezing multi-gigabit throughput and submillisecond latency out of a dense 5G mMIMO antenna array confronts engineers with a fundamental challenge. Achieving that performance requires every transmit and receive path to maintain deterministic phase relationships through every power cycle, link reinitialization and bring-up event — and even small errors accumulate quickly across dozens of antennas, corrupting precoding vectors, degrading beam accuracy and undermining overall network performance. Three practical synchronization approaches — single-shot sysref mode, GPIO-based sysref latching and NCO frequency selection — address these trade-offs, with detailed hardware sequencing for achieving phase-coherent beamforming in 64- to 128-antenna radio designs across sub-6GHz and millimeter-wave frequency bands.

A novel CCM-TCM multimode control method for totem-pole bridgeless PFC

By Bosheng Sun, systems engineer

80 Plus Ruby, the newest and most demanding data center PSU efficiency certification, and high power density requirements put engineers at odds with two competing PFC control methods — CCM delivers high power density but incurs high switching losses, while TCM achieves zero voltage switching (ZVS) but demands multiphase interleaving that drives up size and cost. A multimode approach bypasses this trade-off by running CCM near the AC voltage peak where current demand is highest, then automatically shifting to TCM with ZVS near the zero-crossing region where current drops. Tested on a 3.6kW GaN-based design, the result delivers power density exceeding 180 W/in³, light-load efficiency improvements up to 2% over traditional CCM and distortion-free mode transitions — including the new 5% load requirement that 80 Plus Ruby introduces for the first time.

How to cut PLC output power dissipation in half using an adaptive supply

By Ahmed Noeman, systems engineer, precision amplifiers

As PLC modules pack more channels into tighter footprints, power dissipation in 4 20mA current output stages quietly becomes a thermal management crisis — fixed supply voltages waste hundreds of milliwatts per channel regardless of load conditions. Tracking the output voltage and trimming headroom to the minimum required solves this directly, cutting channel power dissipation by >50% without sacrificing signal quality. This article walks engineers through DC/DC converter selection, feedback network design and difference amplifier implementation for adaptive supply control, backed by measured results confirming power losses below 180mW, DC/DC efficiency between 75% and 90%, and 17.5 to 18.2 bits of RMS resolution across the full 4-20mA output range.

Selecting precision op amps as ADC drivers

By Soufiane Bendaoud, senior business development manager, precision amplifiers

Design engineers routinely overlook the op amp when diagnosing ADC performance shortfalls, yet a poor driver choice silently erodes signal-to-noise ratio (SNR), dynamic range and effective number of bits (ENOB) before the root cause becomes obvious. These parameters interact with the ADC in ways that stack errors before a single conversion completes, making op amp selection far more consequential than most designers expect. Simulation results and practical circuit examples across successive approximation register (SAR) and delta-sigma ADC topologies provide a repeatable framework for optimizing precision ADC driver and signal chain performance.