LowLevelFunc430Xv2.c
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33 /*==========================================================================*\
34 | |
35 | LowLevelFunc430X.c |
36 | |
37 | Low Level Functions regarding user's Hardware |
38 |----------------------------------------------------------------------------|
39 | Project: MSP430 Replicator |
40 | Developed using: IAR Embedded Workbench 6.20 |
41 | and: Code Composer Studio 6.0 |
42 |----------------------------------------------------------------------------|
43 | Version history: |
44 | 1.0 04/02 FRGR Initial version. |
45 | 1.1 04/02 FRGR Included SPI mode to speed up shifting function by 2.|
46 | 1.2 06/02 ALB2 Formatting changes, added comments. |
47 | 1.3 08/02 ALB2 Initial code release with Lit# SLAA149. |
48 | 1.4 09/05 SUN1 Software delays redesigned to use TimerA harware; |
49 | see MsDelay() routine. Added TA setup |
50 | 1.5 12/05 STO Adapted for 2xx devices with SpyBiWire using 4JTAG |
51 | 1.6 08/08 WLUT Adapted InitTarget() for SpyBiWire capable devices |
52 | 1.7 08/08 WLUT Replaced Shift() and Shift_430X() with a common shift|
53 | function AllShifts(). |
54 | Added Spy-Bi-Wire capability, can be switched with |
55 | preprocessor definition SPYBIWIRE_MODE between |
56 | 4-wire or 2-wire functionality. |
57 | 1.8 05/09 GC (Elprotronic) Added support for the new hardware - REP430F |
58 | 1.9 08/09 FB Erase SPI mode for more usability |
59 |----------------------------------------------------------------------------|
60 | Designed 2002 by Texas Instruments Germany |
61 \*==========================================================================*/
64 /****************************************************************************/
65 /* INCLUDES */
66 /****************************************************************************/
67 
68 #include "LowLevelFunc430Xv2.h"
69 
70 /****************************************************************************/
71 /* GLOBAL VARIABLES */
72 /****************************************************************************/
73 
75 byte tdo_bit;
78 
79 /****************************************************************************/
80 /* FUNCTIONS */
81 /****************************************************************************/
82 
83 // combinations of sbw-cycles (TMS, TDI, TDO)
84 //---------------------------------
85 void TMSL_TDIL(void)
86 {
88 }
89 //---------------------------------
90 void TMSH_TDIL(void)
91 {
93 }
94 //------------------------------------
95 void TMSL_TDIH(void)
96 {
98 }
99 //-------------------------------------
100 void TMSH_TDIH(void)
101 {
103 }
104 //------------------------------------
105 void TMSL_TDIH_TDOrd(void)
106 {
108 }
109 //------------------------------------
110 void TMSL_TDIL_TDOrd(void)
111 {
113 }
114 //------------------------------------
115 void TMSH_TDIH_TDOrd(void)
116 {
118 }
119 //------------------------------------
120 void TMSH_TDIL_TDOrd(void)
121 {
123 }
124 
125 #ifdef SPYBIWIRE_MODE
126 //----------------------------------------------------------------------------
129 void ClrTCLK_sbw(void)
130 {
131  if (TCLK_saved & SBWDATO)
132  {
133  TMSLDH
134  }
135  else
136  {
137  TMSL
138  }
139 
140  JTAGOUT &= ~SBWDATO;
141 
142  TDIL TDOsbw //ExitTCLK
143  TCLK_saved = (byte)(~SBWDATO);
144 }
145 
146 //----------------------------------------------------------------------------
149 void SetTCLK_sbw(void)
150 {
151  if (TCLK_saved & SBWDATO)
152  {
153  TMSLDH
154  }
155  else
156  {
157  TMSL
158  }
159 
160  JTAGOUT |= SBWDATO;
161 
162  TDIH TDOsbw //ExitTCLK
164 }
165 
166 //----------------------------------------------------------------------------
173 unsigned long AllShifts(word Format, unsigned long Data)
174 {
175  unsigned long TDOword = 0x00000000;
176  unsigned long MSB = 0x00000000;
177  word i;
178 
179  switch(Format)
180  {
181  case F_BYTE: MSB = 0x00000080;
182  break;
183  case F_WORD: MSB = 0x00008000;
184  break;
185  case F_ADDR: MSB = 0x00080000;
186  break;
187  case F_LONG: MSB = 0x80000000;
188  break;
189  default: // this is an unsupported format, function will just return 0
190  return TDOword;
191  }
192  // shift in bits
193  for (i = Format; i > 0; i--)
194  {
195  if (i == 1) // last bit requires TMS=1; TDO one bit before TDI
196  {
197  ((Data & MSB) == 0) ? TMSH_TDIL_TDOrd() : TMSH_TDIH_TDOrd();
198  }
199  else
200  {
201  ((Data & MSB) == 0) ? TMSL_TDIL_TDOrd() : TMSL_TDIH_TDOrd();
202  }
203  Data <<= 1;
204  if (tdo_bit & SBWDATI)
205  TDOword++;
206  if (i > 1)
207  TDOword <<= 1; // TDO could be any port pin
208  }
209  TMSH_TDIH(); // update IR
210  if (TCLK_saved & SBWDATO)
211  {
212  TMSL_TDIH();
213  }
214  else
215  {
216  TMSL_TDIL();
217  }
218 
219  // de-scramble bits on a 20bit shift
220  if(Format == F_ADDR)
221  {
222  TDOword = ((TDOword << 16) + (TDOword >> 4)) & 0x000FFFFF;
223  }
224 
225  return(TDOword);
226 }
227 
228 #else
229 //----------------------------------------------------------------------------
236 unsigned long AllShifts(word Format, unsigned long Data)
237 {
238  word tclk = StoreTCLK(); // Store TCLK state;
239  unsigned long TDOword = 0x00000000;
240  unsigned long MSB = 0x00000000;
241  word i;
242 
243  switch(Format)
244  {
245  case F_BYTE: MSB = 0x00000080;
246  break;
247  case F_WORD: MSB = 0x00008000;
248  break;
249  case F_ADDR: MSB = 0x00080000;
250  break;
251  case F_LONG: MSB = 0x80000000;
252  break;
253  default: // this is an unsupported format, function will just return 0
254  return TDOword;
255  }
256  for (i = Format; i > 0; i--)
257  {
258  ((Data & MSB) == 0) ? ClrTDI() : SetTDI();
259  Data <<= 1;
260  if (i == 1) // Last bit requires TMS=1
261  {
262  SetTMS();
263  }
264  ClrTCK();
265  SetTCK();
266  TDOword <<= 1; // TDO could be any port pin
267  if (ScanTDO() != 0)
268  {
269  TDOword++;
270  }
271  }
272  // common exit
273  RestoreTCLK(tclk); // restore TCLK state
274 
275  // JTAG FSM = Exit-DR
276  ClrTCK();
277  SetTCK();
278  // JTAG FSM = Update-DR
279  ClrTMS();
280  ClrTCK();
281  SetTCK();
282  // JTAG FSM = Run-Test/Idle
283  return(TDOword);
284 }
285 #endif
286 
287 //----------------------------------------------------------------------------
289 void InitController(void)
290 {
291  // Stop watchdog timer to prevent time out reset
292  WDTCTL = WDTPW + WDTHOLD;
293 
294  //set higher Vcoree, to be able to handle the MCLK freq = 18 MHz
295  SetVCoreUp( 2 );
296 
297  //****** set XT1 clock - crystal 12 MHz **********
298 
299  P7SEL = 3; //Port select XT1
300  UCSCTL5 = 0; //DIVPA, DIVA, DIVS, DIVM -> all direct (DIV=1)
301  UCSCTL6 = XT2OFF+XT1DRIVE_1+XTS;
302  //XT2 OFF, XT1-ON
303  //Drive strength - 8-16MHz LFXT1 HF mode
304  //Loop until XT1,XT2 & DCO stabilizes
305  do{
306  UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); //Clear XT2,XT1,DCO fault flags
307  SFRIFG1 &= ~OFIFG; //Clear fault flags
308  }while( SFRIFG1 & OFIFG );
309  //Select ACLK = LFXT1 = 12MHz
310  //SMCLK = LFXT1 = 12MHz
311  //MCLK = LFXT1 = 12MHz
312  UCSCTL4 = SELA_0+SELS_0+SELM_0;
313 
314 #ifdef MCLK_18MHZ
315 
316  UCSCTL1 = 6*DCORSEL0_L; //DCO-freq range up to min 39MHz (must be higher then 18MHz*2 = 36 MHz)
317  UCSCTL2 = FLLD0 + 23*FLLN0; //DCO-DIV/2, PLL MULTI*(23+1), freq = 24*0.75 = 18 MHz
318  UCSCTL3 = FLLREFDIV_5; //Reference - XT1-CLK, XT1/16 = 0.75MHz
319  //Loop until XT1,XT2 & DCO stabilizes
320  do{
321  UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); //Clear XT2,XT1,DCO fault flags
322  SFRIFG1 &= ~OFIFG; //Clear fault flags
323  }while( SFRIFG1 & OFIFG );
324 
325  UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;
326 #endif
327 
328  // Setup timer_A for hardware delay
329  TA0CTL = 0; // STOP Timer
330  TA0CTL = ID_3+TASSEL_1; // Timer_A source: ACLK/8 = 1.5 MHz
331  TA0CCR0 = ONEMS; // Load CCR0 with delay... (1ms delay)
332 
333  //****** clock setup is done **********
334 
335 #if(0) //can be enabled for test /debug
336  // SMCLK (18 or 12 MHz) freq test on the S1 switch (open) - test time ~ 10ms
337  P1SEL = 0x40; //SMCLK - to P1.6 (S1 - button)
338  P1DIR = 0x40; //for clk test only - must be disable later
339  MsDelay( 5 );
340  usDelay(5000);
341  P1SEL = 0;
342  // END OF SMCLK freq test on the S1 switch
343 #endif
344 
345  TRSLDIR = 0;
346  // set port to output from MSPF5437 to I/O translators
347  TRSL_CDIR = TEST_DIR + RST_DIR + TCK_DIR + TMS_DIR + TDOI_DIR + TDI_DIR;
348  // set all tirections from I/O translators to MSP430F5437 -- All I/O JTAG lines to input
349  TRSLDIR = TEST_DIR + RST_DIR + TCK_DIR + TMS_DIR + TDOI_DIR + TDI_DIR;
350 
351  // set LED ports direction
353  //TURN-ON all LEDs at the startup
355 
356  // set SW ports pull-ups
357  SW_PULLUP |= SW_MODE0+SW_MODE1+SW_1; //set pull-up/pull-down
358  SW_OUT |= SW_MODE0+SW_MODE1+SW_1; //select pull-up
359 
360  SetTargetVcc (0);
361  SetVpp( 0 );
362 }
363 
364 //----------------------------------------------------------------------------
367 void SetVCoreUp (word level)
368 {
369  // Open PMM registers for write access
370  PMMCTL0_H = 0xA5;
371  // Set SVS/SVM high side new level
372  SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
373  // Set SVM low side to new level
374  SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
375  // Wait till SVM is settled
376  while ((PMMIFG & SVSMLDLYIFG) == 0);
377  // Clear already set flags
378  PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
379  // Set VCore to new level
380  PMMCTL0_L = PMMCOREV0 * level;
381  // Wait till new level reached
382  if ((PMMIFG & SVMLIFG))
383  while ((PMMIFG & SVMLVLRIFG) == 0);
384  // Set SVS/SVM low side to new level
385  SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
386  // Lock PMM registers for write access
387  PMMCTL0_H = 0x00;
388 }
389 
390 //----------------------------------------------------------------------------
395 void SetTargetVcc (word level) //level - requested Vcc * 10
396 {
397  if( level == 0 )
398  TVCC_EN_OUT |= TVCC_DIS_BIT;
399  else
400  TVCC_EN_OUT &= ~TVCC_DIS_BIT;
401  TVCC_EN_DIR |= TVCC_DIS_BIT;
402 
403  if( level < 21 ) level = 21;
404  if( level > 36 ) level = 36;
405  level = TVCC_MASK & ((level - 21)<<TVCC_SHIFT);
406  TVCC_DIR |= TVCC_MASK;
407  TVCC_OUT |= TVCC_MASK; //set min.Vcc ( 0xF0 )
408  TVCC_OUT &= ~level; //set desired Vcc - clear desired bits
409  MsDelay( 50 );
410 }
411 
412 //----------------------------------------------------------------------------
415 word Get_target_Vcc(void)
416 {
417  return( Get_Vx( ADC12INCH_14 ));
418 }
419 
420 //----------------------------------------------------------------------------
423 word Get_Ext_Vcc(void)
424 {
425  return( Get_Vx( ADC12INCH_15 ));
426 }
427 
428 //----------------------------------------------------------------------------
431 word Get_Vx( word index )
432 {
433  word y,x;
434 
435  // ADC12 initialization
436  UCSCTL8 |= MODOSCREQEN; // Enable osc for ADC12 - in the Unifield Clock System
437  ADC12CTL0 |= ADC12SHT0_8 + ADC12REFON + ADC12ON; // Internal reference = 1.5V
438  ADC12CTL1 = ADC12SHP;
439  ADC12MCTL0 = ADC12SREF_1 + index; // Input A14 or A15
440 
441  // Delay for needed ref start-up.
442  usDelay(50);
443 
444  ADC12CTL0 |= ADC12ENC; // Enable conversions
445  ADC12CTL0 |= ADC12SC; // Start conversion - sw trigger
446  ADC12IFG &= ~BIT0;
447  do{
448  }while( (ADC12IFG & BIT0) == 0 );
449  ADC12CTL0 &= ~ADC12ENC; // Disable ADC12
450 
451  // Vcc hardware divider - Vcc/ADCin = 3/1;
452  // Ref Vcc = 1.5
453  // x = x * 3 * 1.5 = x * 4.5 = x * 9 /2
454  // x = x*3;
455 
456  x = (ADC12MEM0 * 9)>>1;
457 
458  // result Vcc = x * 1000/4096 in mV
459  // y = x * 1000/(4000+96) ~= x * 0.25 * 4000/(4000+96) = x * 0.25 * 1/(1+96/4000) != x * 0.25 * (1 - 96/4000)
460  // y = x * 0.25 * (1 - 96/4000) ~= x/4 - x * 24/4000 = x/4 - x/167 ~= x/4 - 3*x/512 = x/4 - x/256 - x/512
461 
462  y = x>>2; // y = x/4
463  x = x>>8; // x = x/256
464  y -= x + (x>>1); // y = x/4 - x/256 - x/512;
465  return(y);
466 }
467 
468 //----------------------------------------------------------------------------
471 void TDI_dir(word dir)
472 {
473  JTAGDIR |= TDI; // Always set to output in the F5437
474  if( dir == 0 ) // Direction: IN - from target to REP430F
475  TRSLDIR |= TDI_DIR;
476  else
477  TRSLDIR &= ~TDI_DIR;
478 }
479 
480 //----------------------------------------------------------------------------
483 void TDOI_dir(word dir)
484 {
485  JTAGDIR &= ~TDO; // Always set to input in the F5437
486  if( dir == 0 ) // Direction IN - from target to REP430F
487  TRSLDIR |= TDOI_DIR;
488  else
489  TRSLDIR &= ~TDOI_DIR;
490 }
491 
492 //----------------------------------------------------------------------------
495 void TEST_dir(word dir)
496 {
497  if( dir == 0 ) // Direction IN - from target to REP430F
498  {
499  JTAGDIR &= ~TEST; // Switch MSP port to input first to avoid two outputs on the line
500  TRSLDIR |= TEST_DIR;
501  }
502  else
503  {
504  TRSLDIR &= ~TEST_DIR; // Switch translator to output first to avoid two outputs on the line
505  JTAGDIR |= TEST; // Switch MSP port to output
506  }
507 }
508 
509 //----------------------------------------------------------------------------
512 void TMS_dir(word dir)
513 {
514  if( dir == 0 ) // Direction IN - from target to REP430F
515  {
516  JTAGDIR &= ~TMS; // Switch MSP port to input first to avoid two outputs on the line
517  TRSLDIR |= TMS_DIR;
518  }
519  else
520  {
521  TRSLDIR &= ~TMS_DIR; // Switch translator to output first to avoid two outputs on the line
522  JTAGDIR |= TMS; // Switch MSP port to output
523  }
524 }
525 
526 //----------------------------------------------------------------------------
529 void RST_dir(word dir)
530 {
531  if( dir == 0 ) // Direction IN - from target to REP430F
532  {
533  JTAGDIR &= ~RST; // Switch MSP port to input first to avoid two outputs on the line
534  TRSLDIR |= RST_DIR;
535  }
536  else
537  {
538  TRSLDIR &= ~RST_DIR; // Switch translator to output first - to avoid two outputs on the line
539  JTAGDIR |= RST; // Switch MSP port to output
540  }
541 }
542 
543 //----------------------------------------------------------------------------
546 void TCK_dir(word dir)
547 {
548  JTAGDIR |= TCK; // Always set to output in the F5437
549  if( dir == 0 ) // Direction IN - from target to REP430F
550  TRSLDIR |= TCK_DIR;
551  else
552  TRSLDIR &= ~TCK_DIR;
553 }
554 //----------------------------------------------------------------------------
557 void SetVpp(word source)
558 {
559  if( source & (VPPONTEST | VPPONTDI )) Enable_Vpp();
560  if(( source & (VPPONTEST | VPPONTDI )) == 0 ) Disable_Vpp();
561 
562  if( source & VPPONTEST ) TEST_dir( 0 );
563  if( source & VPPONTDI ) TDI_dir( 0 );
564 
565  VPPOUT &= ~( VPPONTDI | VPPONTEST );
566  source &= VPPONTDI | VPPONTEST;
567  VPPOUT |= source;
568  VPPDIR |= VPPONTDI | VPPONTEST;
569  MsDelay( 2 );
570  if(( source & VPPONTEST ) == 0 ) TEST_dir( 1 );
571  if(( source & VPPONTDI ) == 0 ) TDI_dir( 1 );
572 }
573 
574 //----------------------------------------------------------------------------
576 void Enable_Vpp(void)
577 {
578  SW_DIR |= SW_VPPEN;
579  SW_OUT &= ~SW_VPPEN;
580  MsDelay( 20 );
581 }
582 
583 //----------------------------------------------------------------------------
585 void Disable_Vpp(void)
586 {
587  SW_OUT |= SW_VPPEN;
588  SW_DIR &= ~SW_VPPEN;
589 }
590 
591 //----------------------------------------------------------------------------
594 {
595  TDI_dir( 1 );
596  TEST_dir( 1 );
597  TMS_dir( 1 );
598  RST_dir( 1 );
599  TCK_dir( 1 );
600 }
601 
602 //----------------------------------------------------------------------------
605 {
606  TDOI_dir( 1 );
607  TCK_dir( 1 );
608 }
609 
610 //----------------------------------------------------------------------------
612 void IO_3state(void)
613 {
614  TDI_dir( 0 );
615  TDOI_dir( 0 );
616  TEST_dir( 0 );
617  TMS_dir( 0 );
618  RST_dir( 0 );
619  TCK_dir( 0 );
620 }
621 
622 //----------------------------------------------------------------------------
624 void TDOisInput(void)
625 {
626  TDI_dir( 0 ); // Release TDI pin on target
627  TDOI_dir( 1 ); // Switch TDI --> TDO
628 }
629 
630 //----------------------------------------------------------------------------
632 void DrvSignals(void)
633 {
634  SetVpp( 0 );
635  IO_3state();
636  JTAGSEL = 0x00; // Pins all I/Os
637 #if ( INTERFACE == SPYBIWIRE_IF )
638  JTAGOUT |= TDI;
639  JTAGOUT &= ~TCK;
641 #else
642  JTAGOUT |= TDI | TMS | TCK | TCLK | RST;
643  JTAGOUT &= ~ TEST;
645 #endif
646 }
647 
648 //----------------------------------------------------------------------------
650 void RlsSignals(void)
651 {
652  SetVpp( 0 );
653  Disable_Vpp();
654  IO_3state();
655 }
656 
657 //----------------------------------------------------------------------------
662 void InitTarget(void)
663 {
664  DrvSignals();
665  SetTargetVcc( VCC_LEVEL ); //level - requested Vcc * 10
666 }
667 
668 //----------------------------------------------------------------------------
670 void ReleaseTarget(void)
671 {
672  RlsSignals();
673  SetTargetVcc( 0 );
674 }
675 
676 //----------------------------------------------------------------------------
679 void MsDelay(word milliseconds)
680 {
681  word i;
682  for(i = milliseconds; i > 0; i--)
683  {
684  TA0CCTL0 &= ~CCIFG; // Clear the interrupt flag
685  TA0CTL |= TACLR+MC_1; // Clear & start timer
686  while ((TA0CCTL0 & CCIFG)==0); // Wait until the Timer elapses
687  TA0CTL &= ~MC_1; // Stop Timer
688  }
689 }
690 
691 //----------------------------------------------------------------------------
694 void usDelay(word microseconds)
695 {
696  do
697  {
698  _NOP();
699  _NOP();
700  _NOP();
701  _NOP();
702  _NOP();
703  _NOP();
704  _NOP();
705  _NOP();
706 #ifdef MCLK_18MHZ
707  _NOP();
708  _NOP();
709  _NOP();
710  _NOP();
711  _NOP();
712  _NOP();
713 #endif
714  }
715  while (--microseconds > 0);
716 }
717 
718 //----------------------------------------------------------------------------
725 void TCLKstrobes(word Amount)
726 {
727  volatile word i;
728 
729  // This implementation has 45 (MCLK=18MHz)
730  // or 30 (MCLK 12MHz) body cycles! -> 400kHz
731  // DO NOT MODIFY IT !
732 
733  for (i = Amount; i > 0; i--)
734  {
735  JTAGOUT |= TCLK; // Set TCLK
736  _NOP();
737  _NOP();
738  _NOP();
739  _NOP();
740  _NOP();
741  _NOP();
742  _NOP();
743  _NOP();
744  _NOP();
745  _NOP();
746 #ifdef MCLK_18MHZ
747  _NOP();
748  _NOP();
749  _NOP();
750  _NOP();
751  _NOP();
752  _NOP();
753  _NOP();
754  _NOP();
755 #endif
756  JTAGOUT &= ~TCLK; // Reset TCLK
757  _NOP();
758 #ifdef MCLK_18MHZ
759  _NOP();
760  _NOP();
761  _NOP();
762  _NOP();
763  _NOP();
764  _NOP();
765  _NOP();
766 #endif
767  }
768 }
769 
770 //----------------------------------------------------------------------------
777 void ShowStatus(word status, word index)
778 {
779  All_LEDs_off();
780  switch (status)
781  {
782  case STATUS_ERROR:
783  LED_red_on(); // Switch red LED on
784  ReleaseTarget(); // Voltages off, JTAG HI-Z
785  while(index); // Stop program, index must be > 0
786  case STATUS_ACTIVE:; // Switch yellow LEDs on
787  LED_yellow_on();
788  break;
789  case STATUS_OK: // Switch green LED on
790  LED_green_on();
791  break;
792  case STATUS_IDLE:; // Keep LEDs switched off
793  }
794 } // return if active, idle, ok
795 
796 //----------------------------------------------------------------------------
799 #ifdef DEBUG
800 void TriggerPulse(word mode)
801 {
802  switch (mode)
803  {
804  case 1: LEDOUT |= TRIGGER; // mode = 1: set trigger
805  break;
806  case 2: LEDOUT |= TRIGGER; // mode = 2: set/reset trigger
807  case 0: LEDOUT &= ~TRIGGER; // mode = 0: reset trigger
808  }
809 }
810 #endif
811 
812 /****************************************************************************/
813 /* END OF SOURCE FILE */
814 /****************************************************************************/
void Enable_Vpp(void)
Enable fuse blow voltage Vpp.
void ClrTCLK_sbw(void)
Clear TCLK in Spy-Bi-Wire mode.
void usDelay(word microseconds)
Delay function (resolution is ~1 us)
#define TCLK
P5.7 TDI (former XOUT) receives TCLK.
#define STATUS_ACTIVE
Replicator is active.
void SetVpp(word source)
function to set the fuse blow voltage Vpp
#define TDOsbw
SBW macro: TDO cycle without reading TDO.
byte TCLK_saved
Holds the last value of TCLK before entering a JTAG sequence.
#define SW_1
SW-1 TEST.
word Get_Vx(word index)
Measure different voltages via ADC12.
void TCK_dir(word dir)
Set the direction for the TCK pin.
void ShowStatus(word status, word index)
This function controls the status LEDs depending on the status argument. It stops program in error ca...
void TDI_dir(word dir)
Set the direction for the TDI pin.
void configure_IO_JTAG(void)
Set JTAG pins to output direction - from REP430F to target.
#define TMSLDH
SBW macro: clear TMS signal and immediately set it high again in the SBWTCK low phase to enter the TD...
#define VCC_LEVEL
Set the target's Vcc level supplied by REP430F.
Definition: Config430Xv2.h:73
#define LED_RED
RED LED.
#define LED_GREEN
GREEN LED.
#define SW_MODE0
Mode-0 switch.
void Disable_Vpp(void)
Disable fuse blow voltage Vpp.
#define LED_YELLOW
YELLOW LED.
unsigned long AllShifts(word Format, unsigned long Data)
Shift a value into TDI (MSB first) and simultaneously shift out a value from TDO (MSB first)...
#define VPPDIR
Fuse blow voltage (Vpp) direction register.
#define LED_yellow_on()
Switch on yellow LED.
#define LED_red_on()
Switch on red LED.
void IO_3state(void)
Set all JTAG pins to input direction - from target to REP430F.
#define TDO_RD
SBW macro: TDO cycle with TDO read.
#define STATUS_IDLE
Replicator is idling.
#define TVCC_MASK
Minimum VCC value.
#define TVCC_DIR
VCC direction register.
#define VPPONTEST
P8.2 Fuse blow voltage switched to TEST.
#define TEST_DIR
TEST Translator direction 0 - output from REP430F, 1 - input to REP430F.
void SetVCoreUp(word level)
Function to set a specific voltage level via the PMM.
#define TDO
P5.6 JTAG TDO output pin.
#define SBWDATI
JTAG data in pin in SBW mode - separate pin in MSP430F5437 - common IO translator.
void InitController(void)
Initialization of the Controller Board.
#define All_LEDs_off()
Switch off all LEDs.
#define SBWDATO
JTAG data_out pin in SBW mode -separate pin in MSP430F5437 - common IO translator.
#define TMS_DIR
TMS Translator direction 0 - output from REP430F, 1 - input to REP430F.
#define SW_MODE1
Mode-1 switch.
#define LED_green_on()
Switch on green LED.
void TCLKstrobes(word Amount)
This function generates Amount strobes with the Flash Timing Generator.
#define TDIH
SBW macro: Set TDI = 1.
#define RestoreTCLK(x)
JTAG macro: restore TCLK signal on TDI pin (based on input: x)
void TEST_dir(word dir)
Set the direction for the TEST pin.
void TDOI_dir(word dir)
Set the direction for the TDO pin.
#define JTAGSEL
JTAG select register.
#define TMSH
SBW macro: set TMS signal.
#define TDOI_DIR
TDO/TDI Translator direction 0 - output from REP430F, 1 - input to REP430F.
#define ClrTDI()
JTAG macro: clear TDI signal.
#define TMS
P5.5 JTAG TMS input pin.
#define VPPOUT
Fuse blow voltage (Vpp) output register.
#define TEST
P5.2 JTAG Test input pin.
#define SetTCK()
JTAG macro: set TCK signal.
#define TDI
P5.7 JTAG TDI input pin.
void TMS_dir(word dir)
Set the direction for the TMS pin.
#define TDIL
SBW macro: clear TDI signal.
#define SetTMS()
JTAG macro: set TMS signal.
#define LED_DIR
LED direction register.
#define TVCC_SHIFT
Value to shift up voltage level.
#define StoreTCLK()
JTAG macro: return current TCLK signal (on TDI pin)
#define STATUS_OK
return 1 = no error
#define TMSL
SBW macro: clear TMS signal.
void ReleaseTarget(void)
Release Target Board (switch voltages off, JTAG pins are HI-Z)
#define RST_DIR
RESET Translator direction 0 - output from REP430F, 1 - input to REP430F.
void TDOisInput(void)
This function switches TDO to Input (used for fuse blowing)
#define SW_VPPEN
Switch-Vpp Enable - test and set/clr.
#define LED_OUT
LED output register.
byte tdo_bit
Holds the value of TDO-bit.
void MsDelay(word milliseconds)
Delay function (resolution is 1 ms)
void configure_IO_SBW(void)
Set SBW pins to output direction - from REP430F to target.
#define TCK_DIR
TCK Translator direction 0 - output from REP430F, 1 - input to REP430F.
#define TVCC_OUT
VCC output register.
#define JTAGDIR
JTAG direction register.
#define STATUS_ERROR
return 0 = error
void SetTargetVcc(word level)
Set target Vcc (supplied from REP430F)
#define TCK
P5.4 JTAG TCK input pin.
#define ClrTCK()
JTAG macro: clear TCK signal.
void RST_dir(word dir)
Set the direction for the RST pin.
#define JTAGOUT
JTAG output register.
void InitTarget(void)
Initialization of the Target Board (switch voltages on, preset JTAG pins)
word Get_target_Vcc(void)
Determine target VCC.
#define ScanTDO()
JTAG macro: return TDO value (result 0 or TDO (0x40))
#define SetTDI()
JTAG macro: set TDI signal.
word Get_Ext_Vcc(void)
Determine external VCC.
void RlsSignals(void)
Release I/O pins.
Low Level function prototypes, macros, and pin-to-signal assignments regarding to user's hardware...
#define RST
P5.3 Hardware RESET input pin.
#define VPPONTDI
P8.1 Fuse blow voltage switched to TDI.
void SetTCLK_sbw(void)
Set TCLK in Spy-Bi-Wire mode.
#define TDI_DIR
TDI Translator direction 0 - output from REP430F, 1 - input to REP430F.
#define ONEMS
CCR0 delay for 1ms with a 1.5 MHz TA clock.
void DrvSignals(void)
Set up I/O pins for JTAG communication.
#define ClrTMS()
JTAG macro: clear TMS signal.

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