LowLevelFunc430.c
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33 /*==========================================================================*\
34 | |
35 | LowLevelFunc430.c |
36 | |
37 | Low Level Functions regarding user's hardware |
38 |----------------------------------------------------------------------------|
39 | Project: MSP430 Replicator |
40 | Developed using: IAR Embedded Workbench 6.20 |
41 | and: Code Composer Studio 6.0 |
42 |----------------------------------------------------------------------------|
43 | Version history: |
44 | 1.0 04/02 FRGR Initial version. |
45 | 1.1 04/02 FRGR Included SPI mode to speed up shifting function by 2.|
46 | 1.2 06/02 ALB2 Formatting changes, added comments. |
47 | 1.3 08/02 ALB2 Initial code release with Lit# SLAA149. |
48 | 1.4 09/05 SUN1 Software delays redesigned to use TimerA harware; |
49 | see MsDelay() routine. Added TA setup |
50 | 1.5 12/05 STO Adapted for 2xx devices with SpyBiWire using 4JTAG |
51 | 1.6 08/08 WLUT Cleaned up InitTarget() for JTAG init sequence. |
52 | 1.7 05/09 GC (Elprotronic) Added support for the new hardware - REP430F |
53 | 1.8 07/09 FB Added support for Spy-Bi-Wire and function |
54 | configure_IO_SBW( void ) |
55 | 1.9 05/12 RL Updated commentaries |
56 |----------------------------------------------------------------------------|
57 | Designed 2002 by Texas Instruments Germany |
58 \*==========================================================================*/
61 /****************************************************************************/
62 /* INCLUDES */
63 /****************************************************************************/
64 
65 #include "LowLevelFunc430.h"
66 #include "JTAGfunc430.h"
67 
68 /****************************************************************************/
69 /* GLOBAL VARIABLES */
70 /****************************************************************************/
71 
73 byte tdo_bit;
76 
77 /****************************************************************************/
78 /* FUNCTIONS */
79 /****************************************************************************/
80 
81 #ifdef SPYBIWIRE_MODE
82 // Combinations of sbw-cycles (TMS, TDI, TDO)
83 //----------------------------------------------------------------------------
85 void TMSL_TDIL(void)
86 {
88 }
89 //----------------------------------------------------------------------------
91 void TMSH_TDIL(void)
92 {
94 }
95 //----------------------------------------------------------------------------
97 void TMSL_TDIH(void)
98 {
100 }
101 //----------------------------------------------------------------------------
103 void TMSH_TDIH(void)
104 {
106 }
107 //----------------------------------------------------------------------------
109 void TMSL_TDIH_TDOrd(void)
110 {
112 }
113 //----------------------------------------------------------------------------
115 void TMSL_TDIL_TDOrd(void)
116 {
118 }
119 //----------------------------------------------------------------------------
121 void TMSH_TDIH_TDOrd(void)
122 {
124 }
125 //----------------------------------------------------------------------------
127 void TMSH_TDIL_TDOrd(void)
128 {
130 }
131 
132 //----------------------------------------------------------------------------
135 void ClrTCLK_sbw(void)
136 {
137  if (TCLK_saved & SBWDATO)
138  {
139  TMSLDH
140  }
141  else
142  {
143  TMSL
144  }
145 
146  JTAGOUT &= ~SBWDATO;
147 
148  TDIL TDOsbw //ExitTCLK
149  TCLK_saved = (byte)(~SBWDATO);
150 }
151 
152 //----------------------------------------------------------------------------
155 void SetTCLK_sbw(void)
156 {
157  if (TCLK_saved & SBWDATO)
158  {
159  TMSLDH
160  }
161  else
162  {
163  TMSL
164  }
165 
166  JTAGOUT |= SBWDATO;
167 
168  TDIH TDOsbw //ExitTCLK
170 }
171 
172 //----------------------------------------------------------------------------
175 {
176  word MSB;
177  word Data, i;
178 
179  Data = IR_EX_BLOW;
180 
181  // JTAG FSM state = Run-Test/Idle
182  if (TCLK_saved & SBWDATO)
183  {
184  TMSH_TDIH();
185  }
186  else
187  {
188  TMSH_TDIL();
189  }
190  TMSH_TDIH(); // JTAG FSM state = Select DR-Scan
191  TMSL_TDIH(); // JTAG FSM state = Select IR-Scan
192  TMSL_TDIH(); // JTAG FSM state = Capture-IR
193 
194  MSB = 0x80;
195  for (i = 8; i > 1; i--)
196  {
197  ((Data & MSB) == 0) ? TMSL_TDIL_TDOrd() : TMSL_TDIH_TDOrd();
198  Data <<= 1;
199  }
200  // last bit requires TMS=1; TDO one bit before TDI
201  ((Data & MSB) == 0) ? TMSH_TDIL_TDOrd() : TMSH_TDIH_TDOrd();
202  // SBWTDIO must be low on exit!
203  TMSH_TDIL();
204  TMSL_TDIL();
205  // instruction shift done!
206 
207  TMSL // go to TDI-slot via TMS-slot
208  // now in TDI-slot ready to blow the fuse
209 }
210 
211 //----------------------------------------------------------------------------
218 word Shift(word Format, word Data)
219 {
220  word TDOword = 0x0000;
221  word MSB = 0x0000;
222  word i;
223 
224  (Format == F_WORD) ? (MSB = 0x8000) : (MSB = 0x80);
225  for (i = Format; i > 0; i--)
226  {
227  if (i == 1) // last bit requires TMS=1; TDO one bit before TDI
228  {
229  ((Data & MSB) == 0) ? TMSH_TDIL_TDOrd() : TMSH_TDIH_TDOrd();
230  }
231  else
232  {
233  ((Data & MSB) == 0) ? TMSL_TDIL_TDOrd() : TMSL_TDIH_TDOrd();
234  }
235  Data <<= 1;
236  if (tdo_bit & SBWDATI)
237  TDOword++;
238  if (i > 1)
239  TDOword <<= 1; // TDO could be any port pin
240  }
241  TMSH_TDIH(); // update IR
242  if (TCLK_saved & SBWDATO)
243  {
244  TMSL_TDIH();
245  }
246  else
247  {
248  TMSL_TDIL();
249  }
250  return(TDOword);
251 }
252 #else
253 //----------------------------------------------------------------------------
260 word Shift(word Format, word Data)
261 {
262  word tclk = StoreTCLK(); // Store TCLK state;
263  word TDOword = 0x0000; // Initialize shifted-in word
264  word MSB = 0x0000;
265 
266  // Shift via port pins, no coding necessary
267  volatile word i;
268  (Format == F_WORD) ? (MSB = 0x8000) : (MSB = 0x80);
269  for (i = Format; i > 0; i--)
270  {
271  ((Data & MSB) == 0) ? ClrTDI() : SetTDI();
272  Data <<= 1;
273  if (i == 1) // Last bit requires TMS=1
274  {
275  SetTMS();
276  }
277  ClrTCK();
278  SetTCK();
279  TDOword <<= 1; // TDO could be any port pin
280  if (ScanTDO() != 0)
281  {
282  TDOword++;
283  }
284  }
285  // common exit
286  RestoreTCLK(tclk); // restore TCLK state
287 
288  // JTAG FSM = Exit-DR
289  ClrTCK();
290  SetTCK();
291  // JTAG FSM = Update-DR
292  ClrTMS();
293  ClrTCK();
294  SetTCK();
295  // JTAG FSM = Run-Test/Idle
296  return(TDOword);
297 }
298 #endif
299 
300 //----------------------------------------------------------------------------
302 void InitController(void)
303 {
304  // Stop watchdog timer to prevent time out reset
305  WDTCTL = WDTPW + WDTHOLD;
306 
307  // Set higher Vcoree, to be able to handle the MCLK freq = 18 MHz
308  SetVCoreUp( 2 );
309 
310  //****** set XT1 clock - crystal 12 MHz **********
311 
312  P7SEL = 3; // Port select XT1
313  UCSCTL5 = 0; // DIVPA, DIVA, DIVS, DIVM -> all direct (DIV=1)
314  UCSCTL6 = XT2OFF+XT1DRIVE_1+XTS;
315  // XT2 OFF, XT1-ON
316  // Drive strength - 8-16MHz LFXT1 HF mode
317  // Loop until XT1,XT2 & DCO stabilizes
318  do{
319  // Clear XT2,XT1,DCO fault flags
320  UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
321  // Clear fault flags
322  SFRIFG1 &= ~OFIFG;
323  }while( SFRIFG1 & OFIFG );
324  // Select ACLK = LFXT1 = 12MHz
325  // SMCLK = LFXT1 = 12MHz
326  // MCLK = LFXT1 = 12MHz
327  UCSCTL4 = SELA_0+SELS_0+SELM_0;
328 
329 #ifdef MCLK_18MHZ
330  // DCO-freq range up to min 39MHz (must be higher then 18MHz*2 = 36 MHz)
331  UCSCTL1 = 6*DCORSEL0_L;
332  // DCO-DIV/2, PLL MULTI*(23+1), freq = 24*0.75 = 18 MHz
333  UCSCTL2 = FLLD0 + 23*FLLN0;
334  // Reference - XT1-CLK, XT1/16 = 0.75MHz
335  UCSCTL3 = FLLREFDIV_5;
336  // Loop until XT1,XT2 & DCO stabilizes
337  do{
338  // Clear XT2,XT1,DCO fault flags
339  UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
340  // Clear fault flags
341  SFRIFG1 &= ~OFIFG;
342  }while( SFRIFG1 & OFIFG );
343 
344  UCSCTL4 = SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV;
345 #endif
346 
347  // Setup timer_A for hardware delay
348  TA0CTL = 0; // STOP Timer
349  TA0CTL = ID_3+TASSEL_1; // Timer_A source: ACLK/8 = 1.5 MHz
350  TA0CCR0 = ONEMS; // Load CCR0 with delay... (1ms delay)
351 
352  //****** clock setup is done **********
353 
354 #if(0) // can be enabled for test /debug
355  // SMCLK (18 or 12 MHz) freq test on the S1 switch (open) - test time ~ 10ms
356  P1SEL = 0x40; // SMCLK - to P1.6 (S1 - button)
357  P1DIR = 0x40; // for clk test only - must be disabled later
358  MsDelay( 5 );
359 
360  P1SEL = 0;
361  // END OF SMCLK freq test on the S1 switch
362 #endif
363 
364  TRSLDIR = 0;
365  // set port to output from MSPF5437 to I/O translators
366  TRSL_CDIR = TEST_DIR + RST_DIR + TCK_DIR + TMS_DIR + TDOI_DIR + TDI_DIR;
367  // set all directions from I/O translators to MSP430F5437
368  // (all I/O JTAG lines to input)
369  TRSLDIR = TEST_DIR + RST_DIR + TCK_DIR + TMS_DIR + TDOI_DIR + TDI_DIR;
370 
371  // set LED ports direction
373  // TURN-ON all LEDs at the startup
375 
376  // set SW ports pull-ups
377  SW_PULLUP |= SW_MODE0+SW_MODE1+SW_1; // set pull-up/pull-down
378  SW_OUT |= SW_MODE0+SW_MODE1+SW_1; // select pull-up
379 
380  SetTargetVcc (0);
381  SetVpp( 0 );
382 }
383 
384 //----------------------------------------------------------------------------
387 void SetVCoreUp (word level)
388 {
389  // Open PMM registers for write access
390  PMMCTL0_H = 0xA5;
391  // Set SVS/SVM high side new level
392  SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
393  // Set SVM low side to new level
394  SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
395  // Wait till SVM is settled
396  while ((PMMIFG & SVSMLDLYIFG) == 0);
397  // Clear already set flags
398  PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
399  // Set VCore to new level
400  PMMCTL0_L = PMMCOREV0 * level;
401  // Wait till new level reached
402  if ((PMMIFG & SVMLIFG))
403  {
404  while ((PMMIFG & SVMLVLRIFG) == 0);
405  }
406  // Set SVS/SVM low side to new level
407  SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
408  // Lock PMM registers for write access
409  PMMCTL0_H = 0x00;
410 }
411 
412 //----------------------------------------------------------------------------
417 void SetTargetVcc (word level) // level - requested Vcc * 10
418 {
419  if( level == 0 )
420  TVCC_EN_OUT |= TVCC_DIS_BIT;
421  else
422  TVCC_EN_OUT &= ~TVCC_DIS_BIT;
423  TVCC_EN_DIR |= TVCC_DIS_BIT;
424 
425  if( level < 21 ) level = 21;
426  if( level > 36 ) level = 36;
427  level = TVCC_MASK & ((level - 21)<<TVCC_SHIFT);
428  TVCC_DIR |= TVCC_MASK;
429  TVCC_OUT |= TVCC_MASK; // set min.Vcc ( 0xF0 )
430  TVCC_OUT &= ~level; // set desired Vcc - clear desired bits
431  MsDelay( 50 );
432 }
433 
434 //----------------------------------------------------------------------------
437 word Get_target_Vcc(void)
438 {
439  return( Get_Vx( ADC12INCH_14 ));
440 }
441 
442 //----------------------------------------------------------------------------
445 word Get_Ext_Vcc(void)
446 {
447  return( Get_Vx( ADC12INCH_15 ));
448 }
449 
450 //----------------------------------------------------------------------------
453 word Get_Vx(word index)
454 {
455  word y,x;
456 
457  // ADC12 initialization
458  UCSCTL8 |= MODOSCREQEN; // Enable osc for ADC12
459  // (in the Unifield Clock System)
460  ADC12CTL0 |= ADC12SHT0_8 + ADC12REFON + ADC12ON; // Internal reference =1.5V
461  ADC12CTL1 = ADC12SHP;
462  ADC12MCTL0 = ADC12SREF_1 + index; // Input A14 or A15
463 
464  // Delay for needed ref start-up.
465  MsDelay( 5 );
466 
467  ADC12CTL0 |= ADC12ENC; // Enable conversions
468  ADC12CTL0 |= ADC12SC; // Start conversion - sw trigger
469  ADC12IFG &= ~BIT0;
470  do{
471  }while( (ADC12IFG & BIT0) == 0 );
472  ADC12CTL0 &= ~ADC12ENC; // Disable ADC12
473 
474  // Vcc hardware divider - Vcc/ADCin = 3/1;
475  // Ref Vcc = 1.5
476  // x = x * 3 * 1.5 = x * 4.5 = x * 9 /2
477 
478  x = (ADC12MEM0 * 9)>>1;
479 
480  // result Vcc = x * 1000/4096 in mV
481  // y = x * 1000/(4000+96) ~= x * 0.25 * 4000/(4000+96)
482  // = x * 0.25 * 1/(1+96/4000) != x * 0.25 * (1 - 96/4000)
483  // y = x * 0.25 * (1 - 96/4000) ~= x/4 - x * 24/4000
484  // = x/4 - x/167 ~= x/4 - 3*x/512 = x/4 - x/256 - x/512
485 
486  y = x>>2; // y = x/4
487  x = x>>8; // x = x/256
488  y -= x + (x>>1); // y = x/4 - x/256 - x/512;
489  return(y);
490 }
491 //----------------------------------------------------------------------------
494 void TDI_dir(word dir)
495 {
496  JTAGDIR |= TDI; // Always set to output in the F5437
497  if( dir == 0 ) // Direction IN - from target to REP430F
498  TRSLDIR |= TDI_DIR;
499  else
500  TRSLDIR &= ~TDI_DIR;
501 }
502 //----------------------------------------------------------------------------
505 void TDOI_dir(word dir)
506 {
507  JTAGDIR &= ~TDO; // Always set to input in the F5437
508  if( dir == 0 ) // Direction IN - from target to REP430
509  TRSLDIR |= TDOI_DIR;
510  else
511  TRSLDIR &= ~TDOI_DIR;
512 }
513 //----------------------------------------------------------------------------
516 void TEST_dir(word dir)
517 {
518  if( dir == 0 ) // Direction IN - from target to REP430
519  {
520  JTAGDIR &= ~TEST; // Switch MSP port to input first - to avoid two outputs on the line
521  TRSLDIR |= TEST_DIR;
522  }
523  else
524  {
525  TRSLDIR &= ~TEST_DIR; // Switch translator to output first - to avoid two outputs on the line
526  JTAGDIR |= TEST; // Switch MSP port to output
527  }
528 }
529 //----------------------------------------------------------------------------
532 void TMS_dir(word dir)
533 {
534  if( dir == 0 ) // Direction IN - from target to REP430
535  {
536  JTAGDIR &= ~TMS; // Switch MSP port to input first - to avoid two outputs on the line
537  TRSLDIR |= TMS_DIR;
538  }
539  else
540  {
541  TRSLDIR &= ~TMS_DIR; // Switch translator to output first - to avoid two outputs on the line
542  JTAGDIR |= TMS; // Switch MSP port to output
543  }
544 }
545 //----------------------------------------------------------------------------
548 void RST_dir(word dir)
549 {
550  if( dir == 0 ) // Direction IN - from target to REP430
551  {
552  JTAGDIR &= ~RST; // Switch MSP port to input first - to avoid two outputs on the line
553  TRSLDIR |= RST_DIR;
554  }
555  else
556  {
557  TRSLDIR &= ~RST_DIR; // Switch translator to output first - to avoid two outputs on the line
558  JTAGDIR |= RST; // Switch MSP port to output
559  }
560 }
561 //----------------------------------------------------------------------------
564 void TCK_dir(word dir)
565 {
566  JTAGDIR |= TCK; // Always set to output in the F5437
567  if( dir == 0 ) // Direction IN - from target to REP430
568  TRSLDIR |= TCK_DIR;
569  else
570  TRSLDIR &= ~TCK_DIR;
571 }
572 //----------------------------------------------------------------------------
575 void SetVpp(word source)
576 {
577  if( source & (VPPONTEST | VPPONTDI )) Enable_Vpp();
578  if(( source & (VPPONTEST | VPPONTDI )) == 0 ) Disable_Vpp();
579 
580  if( source & VPPONTEST ) TEST_dir( 0 );
581  if( source & VPPONTDI ) TDI_dir( 0 );
582 
583  VPPOUT &= ~( VPPONTDI | VPPONTEST );
584  source &= VPPONTDI | VPPONTEST;
585  VPPOUT |= source;
586  VPPDIR |= VPPONTDI | VPPONTEST;
587  MsDelay( 2 );
588  if(( source & VPPONTEST ) == 0 ) TEST_dir( 1 );
589  if(( source & VPPONTDI ) == 0 ) TDI_dir( 1 );
590 }
591 
592 //----------------------------------------------------------------------------
594 void Enable_Vpp(void)
595 {
596  SW_DIR |= SW_VPPEN;
597  SW_OUT &= ~SW_VPPEN;
598  MsDelay( 20 );
599 }
600 
601 //----------------------------------------------------------------------------
603 void Disable_Vpp(void)
604 {
605  SW_OUT |= SW_VPPEN;
606  SW_DIR &= ~SW_VPPEN;
607 }
608 //----------------------------------------------------------------------------
611 {
612  TDI_dir( 1 );
613  TDOI_dir( 0 );
614  TEST_dir( 1 );
615  TMS_dir( 1 );
616  RST_dir( 1 );
617  TCK_dir( 1 );
618 }
619 
620 //----------------------------------------------------------------------------
623 {
624  TDOI_dir( 1 );
625  TCK_dir( 1 );
626 }
627 
628 //----------------------------------------------------------------------------
630 void IO_3state(void)
631 {
632  TDI_dir( 0 );
633  TDOI_dir( 0 );
634  TEST_dir( 0 );
635  TMS_dir( 0 );
636  RST_dir( 0 );
637  TCK_dir( 0 );
638 }
639 
640 //----------------------------------------------------------------------------
642 void TDOisInput(void)
643 {
644  TDI_dir( 0 ); // Release TDI pin on target
645  TDOI_dir( 1 ); // Switch TDI --> TDO
646 }
647 
648 //----------------------------------------------------------------------------
650 void DrvSignals(void)
651 {
652  SetVpp( 0 );
653  IO_3state();
654  JTAGSEL = 0x00; // Pins all I/Os
655 #if ( INTERFACE == SPYBIWIRE_IF )
656  JTAGOUT |= TDI;
657  JTAGOUT &= ~TCK;
659 #else
660  JTAGOUT |= TDI | TMS | TCK | TCLK | RST;
661  JTAGOUT &= ~ TEST;
663 #endif
664 }
665 
666 //----------------------------------------------------------------------------
668 void RlsSignals(void)
669 {
670  SetVpp( 0 );
671  Disable_Vpp();
672  IO_3state();
673 }
674 
675 //----------------------------------------------------------------------------
680 void InitTarget(void)
681 {
682  DrvSignals();
683  SetTargetVcc( VCC_LEVEL ); //level - requested Vcc * 10
684 }
685 
686 //----------------------------------------------------------------------------
688 void ReleaseTarget(void)
689 {
690  RlsSignals();
691  SetTargetVcc( 0 );
692 }
693 
694 //----------------------------------------------------------------------------
697 void MsDelay(word milliseconds)
698 {
699  word i;
700  for(i = milliseconds; i > 0; i--)
701  {
702  TA0CCTL0 &= ~CCIFG; // Clear the interrupt flag
703  TA0CTL |= TACLR+MC_1; // Clear & start timer
704  while ((TA0CCTL0 & CCIFG)==0); // Wait until the Timer elapses
705  TA0CTL &= ~MC_1; // Stop Timer
706  }
707 }
708 
709 //----------------------------------------------------------------------------
712 void usDelay(word microseconds)
713 {
714  do
715  {
716  _NOP();
717  _NOP();
718  _NOP();
719  _NOP();
720  _NOP();
721  _NOP();
722  _NOP();
723  _NOP();
724 #ifdef MCLK_18MHZ
725  _NOP();
726  _NOP();
727  _NOP();
728  _NOP();
729  _NOP();
730  _NOP();
731 #endif
732  }
733  while (--microseconds > 0);
734 }
735 
736 #ifdef SPYBIWIRE_MODE
737 /*----------------------------------------------------------------------------
738  This function controls the status LEDs depending on the status
739  argument. It stops program in error case.
740  Arguments: word status (4 stati - can be extended to 8 - possible for 3 LEDs - Yellow,Green,Red)
741  word index (additional number for detailed diagnostics or
742  watch variable during debugging phase)
743 */
744 void TCLKstrobes(word Amount) // enters with TCLK_saved and exits with TCLK = 1
745 {
746  word i;
747 
748  if (TCLK_saved & SBWDATO)
749  {
750  TMSLDH
751  } // TDI = 1 with rising sbwclk
752  else
753  {
754  TMSL
755  }
756 
757  // This implementation has 30 body cycles! -> 400kHz
758  // DO NOT MODIFY IT !
759 
760  for (i = Amount; i > 0; i--)
761  {
762  JTAGOUT &= ~SBWDATO;
763  _NOP();
764  _NOP();
765  _NOP();
766  _NOP();
767  _NOP();
768  _NOP();
769  _NOP();
770  _NOP();
771  _NOP();
772  _NOP();
773 #ifdef MCLK_18MHZ
774  _NOP();
775  _NOP();
776  _NOP();
777  _NOP();
778  _NOP();
779  _NOP();
780  _NOP();
781  _NOP();
782 #endif
783  JTAGOUT |= SBWDATO;
784  _NOP();
785 #ifdef MCLK_18MHZ
786  _NOP();
787  _NOP();
788  _NOP();
789  _NOP();
790  _NOP();
791  _NOP();
792  _NOP();
793 #endif
794  }
795  TDIH TDOsbw //ExitTCLK
797 }
798 #else
799 
800 //----------------------------------------------------------------------------
808 void TCLKstrobes(word Amount)
809 {
810  volatile word i;
811 
812  // This implementation has 45 (MCLK=18MHz)
813  // or 30 (MCLK 12MHz) body cycles! -> 400kHz
814  // DO NOT MODIFY IT !
815 
816  for (i = Amount; i > 0; i--)
817  {
818  JTAGOUT |= TCLK; // Set TCLK
819  _NOP();
820  _NOP();
821  _NOP();
822  _NOP();
823  _NOP();
824  _NOP();
825  _NOP();
826  _NOP();
827  _NOP();
828  _NOP();
829 #ifdef MCLK_18MHZ
830  _NOP();
831  _NOP();
832  _NOP();
833  _NOP();
834  _NOP();
835  _NOP();
836  _NOP();
837  _NOP();
838 #endif
839  JTAGOUT &= ~TCLK; // Reset TCLK
840  _NOP();
841 #ifdef MCLK_18MHZ
842  _NOP();
843  _NOP();
844  _NOP();
845  _NOP();
846  _NOP();
847  _NOP();
848  _NOP();
849 #endif
850  }
851 }
852 #endif
853 
854 //----------------------------------------------------------------------------
861 void ShowStatus(word status, word index)
862 {
863  All_LEDs_off();
864  switch (status)
865  {
866  case STATUS_ERROR:
867  LED_red_on(); // Switch red LED on
868  ReleaseTarget(); // Voltages off, JTAG HI-Z
869  while(index); // Stop program, index must be > 0
870  case STATUS_ACTIVE:; // Switch yellow LEDs on
871  LED_yellow_on();
872  break;
873  case STATUS_OK: // Switch green LED on
874  LED_green_on();
875  break;
876  case STATUS_IDLE:; // Keep LEDs switched off
877  }
878 } // return if active, idle, ok
879 
880 //----------------------------------------------------------------------------
883 #ifdef DEBUG
884 void TriggerPulse(word mode)
885 {
886  switch (mode)
887  {
888  case 1: LEDOUT |= TRIGGER; // mode = 1: set trigger
889  break;
890  case 2: LEDOUT |= TRIGGER; // mode = 2: set/reset trigger
891  case 0: LEDOUT &= ~TRIGGER; // mode = 0: reset trigger
892  }
893 }
894 #endif
895 
896 /****************************************************************************/
897 /* END OF SOURCE FILE */
898 /****************************************************************************/
#define TMS_DIR
TMS Translator direction 0 - output from REP430F, 1 - input to REP430F.
void TMSH_TDIH_TDOrd(void)
Combination of SBW macros: TMS high, TDI high, TDO read.
#define TDI_DIR
TDI Translator direction 0 - output from REP430F, 1 - input to REP430F.
#define StoreTCLK()
JTAG macro: return current TCLK signal (on TDI pin)
word Shift(word Format, word Data)
Shift a value into TDI (MSB first) and simultaneously shift out a value from TDO (MSB first)...
#define VPPONTEST
P8.2 Fuse blow voltage switched to TEST.
#define SW_MODE0
Mode-0 switch.
#define TMSL
SBW macro: clear TMS signal.
#define SW_1
SW-1 TEST.
void TDOI_dir(word dir)
Set the direction for the TDO pin.
void SetTCLK_sbw(void)
Set TCLK in Spy-Bi-Wire mode.
void ShowStatus(word status, word index)
This function controls the status LEDs depending on the status argument. It stops program in error ca...
#define TDOsbw
SBW macro: TDO cycle without reading TDO.
void SetTargetVcc(word level)
Set target Vcc (supplied from REP430F)
#define TEST
P5.2 JTAG Test input pin.
JTAG Function Prototypes and Definitions.
#define VPPOUT
Fuse blow voltage (Vpp) output register.
#define VCC_LEVEL
Set the target's Vcc level supplied by REP430F.
Definition: Config430.h:70
word Get_Vx(word index)
Measure different voltages via ADC12.
#define TDO_RD
SBW macro: TDO cycle with TDO read.
void TCK_dir(word dir)
Set the direction for the TCK pin.
#define SetTMS()
JTAG macro: set TMS signal.
void DrvSignals(void)
Set up I/O pins for JTAG communication.
#define VPPDIR
Fuse blow voltage (Vpp) direction register.
void TMSH_TDIH(void)
Combination of SBW macros: TMS high, TDI high, no TDO read.
void IR_Ex_Blow_SBW_Shift(void)
Provide JTAG fuse blow instruction.
#define RST_DIR
RESET Translator direction 0 - output from REP430F, 1 - input to REP430F.
#define SW_MODE1
Mode-1 switch.
void ClrTCLK_sbw(void)
Clear TCLK in Spy-Bi-Wire mode.
void configure_IO_JTAG(void)
Set JTAG pins to output direction - from REP430F to target.
void ReleaseTarget(void)
Release Target Board (switch voltages off, JTAG pins are HI-Z)
#define STATUS_ACTIVE
Replicator is active.
void Disable_Vpp(void)
Disable fuse blow voltage Vpp.
#define LED_RED
RED LED.
#define TMSH
SBW macro: set TMS signal.
#define STATUS_ERROR
return 0 = error
#define JTAGSEL
JTAG select register.
#define TCLK
P5.7 TDI (former XOUT) receives TCLK.
#define STATUS_IDLE
Replicator is idling.
void TMSL_TDIL(void)
Combination of SBW macros: TMS low, TDI low, no TDO read.
#define LED_yellow_on()
Switch on yellow LED.
#define TVCC_OUT
VCC output register.
void MsDelay(word milliseconds)
Delay function (resolution is 1 ms)
#define TVCC_MASK
Minimum VCC value.
#define ClrTMS()
JTAG macro: clear TMS signal.
#define TDIH
SBW macro: Set TDI = 1.
#define ONEMS
CCR0 delay for 1ms with a 1.5 MHz TA clock.
void TMS_dir(word dir)
Set the direction for the TMS pin.
void TDOisInput(void)
This function switches TDO to Input (used for fuse blowing)
#define ClrTCK()
JTAG macro: clear TCK signal.
void InitController(void)
Initialization of the Controller Board.
#define LED_OUT
LED output register.
void SetVpp(word source)
function to set the fuse blow voltage Vpp
#define TVCC_SHIFT
Value to shift up voltage level.
#define TEST_DIR
TEST Translator direction 0 - output from REP430F, 1 - input to REP430F.
#define TDOI_DIR
TDO/TDI Translator direction 0 - output from REP430F, 1 - input to REP430F.
byte tdo_bit
Holds the value of TDO-bit.
void SetVCoreUp(word level)
Function to set a specific voltage level via the PMM.
void configure_IO_SBW(void)
Set SBW pins to output direction - from REP430F to target.
#define TCK
P5.4 JTAG TCK input pin.
void TMSL_TDIH(void)
Combination of SBW macros: TMS low, TDI high, no TDO read.
#define SBWDATO
JTAG data_out pin in SBW mode -separate pin in MSP430F5437 - common IO translator.
#define ScanTDO()
JTAG macro: return TDO value (result 0 or TDO (0x40))
void RST_dir(word dir)
Set the direction for the RST pin.
word Get_Ext_Vcc(void)
Determine external VCC.
#define TCK_DIR
TCK Translator direction 0 - output from REP430F, 1 - input to REP430F.
#define RST
P5.3 Hardware RESET input pin.
#define LED_red_on()
Switch on red LED.
#define LED_green_on()
Switch on green LED.
#define LED_YELLOW
YELLOW LED.
#define JTAGOUT
JTAG output register.
#define All_LEDs_off()
Switch off all LEDs.
#define TDO
P5.6 JTAG TDO output pin.
#define LED_GREEN
GREEN LED.
void InitTarget(void)
Initialization of the Target Board (switch voltages on, preset JTAG pins)
word Get_target_Vcc(void)
Determine target VCC.
void TMSL_TDIL_TDOrd(void)
Combination of SBW macros: TMS low, TDI low, TDO read.
void usDelay(word microseconds)
Delay function (resolution is ~1 us)
#define LED_DIR
LED direction register.
#define STATUS_OK
return 1 = no error
#define JTAGDIR
JTAG direction register.
void TDI_dir(word dir)
Set the direction for the TDI pin.
void TEST_dir(word dir)
Set the direction for the TEST pin.
#define TMSLDH
SBW macro: clear TMS signal and immediately set it high again in the SBWTCK low phase to enter the TD...
void IO_3state(void)
Set all JTAG pins to input direction - from target to REP430F.
#define TVCC_DIR
VCC direction register.
byte TCLK_saved
Holds the last value of TCLK before entering a JTAG sequence.
void TMSH_TDIL_TDOrd(void)
Combination of SBW macros: TMS high, TDI low, TDO read.
void Enable_Vpp(void)
Enable fuse blow voltage Vpp.
#define SBWDATI
JTAG data in pin in SBW mode - separate pin in MSP430F5437 - common IO translator.
#define TDI
P5.7 JTAG TDI input pin.
#define IR_EX_BLOW
Perform JTAG fuse blow.
Definition: JTAGfunc430.h:94
#define TDIL
SBW macro: clear TDI signal.
#define SetTCK()
JTAG macro: set TCK signal.
#define TMS
P5.5 JTAG TMS input pin.
#define VPPONTDI
P8.1 Fuse blow voltage switched to TDI.
#define RestoreTCLK(x)
JTAG macro: restore TCLK signal on TDI pin (based on input: x)
#define ClrTDI()
JTAG macro: clear TDI signal.
void RlsSignals(void)
Release I/O pins.
#define SetTDI()
JTAG macro: set TDI signal.
Low Level function prototypes, macros, and pin-to-signal assignments regarding to user's hardware...
void TMSH_TDIL(void)
Combination of SBW macros: TMS high, TDI low, no TDO read.
void TMSL_TDIH_TDOrd(void)
Combination of SBW macros: TMS low, TDI high, TDO read.
#define SW_VPPEN
Switch-Vpp Enable - test and set/clr.

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