JTAGfunc430Xv2.c
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1 /*
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33 /*==========================================================================*\
34 | |
35 | JTAGfunc430Xv2.c |
36 | |
37 | JTAG Control Sequences for Erasing / Programming / Fuse Programming |
38 |----------------------------------------------------------------------------|
39 | Project: JTAG Functions |
40 | Developed using: IAR Embedded Workbench 6.20 |
41 | and: Code Composer Studio 6.0 |
42 |----------------------------------------------------------------------------|
43 | Version history: |
44 | 1.0 08/08 WLUT Initial version. |
45 | 1.1 10/08 WLUT Fixed VerifyPSA_430Xv2(). The previous version was |
46 | driving StartAddr-2 on the devices' address bus. |
47 | This can cause security violations in the 5xx system.|
48 | The fixed version of the algorithm is now operating |
49 | only within the specified memory range which is to |
50 | be verified. |
51 | Removed 'fuse check' in ResetTap() for SPYBIWIREMODE.|
52 | Fuse check is not required for 5xx. |
53 | Added correct Spy-Bi-Wire entry sequence to StartJtag|
54 | 1.2 07/09 FB Fix JTAG 17 BUG, Add support for new Replecator |
55 | Fix Spy Bi wire entry sequence |
56 | 1.3 08/09 FB Changed VerifyPSA_430Xv2 to clock through PSA during |
57 | TCLK low phase |
58 | 1.3 10/10 FB changed function StartJtag(), that the device could |
59 | be held in reset to shift in the "magic pattern" |
60 | to stop user code excecution |
61 | added new function ConnectJTAG() to enstablish the |
62 | physical JTAG connection |
63 | added new function MagicPattern() to stop user code |
64 | execution and set the target device into LPM4 |
65 | 1.4 GC (Elprotronic) Bug in GetCoreID() --> DeviceIdPointer has been fixed|
66 | 1.5 08/11 FB Added FRAM support functions: |
67 | ProgramLockKey() - Set JTAG Lock Key |
68 | UnlockDevice() - Open a device with JTAG password|
69 | WriteFram_430Xv2 - Write FRAM memory |
70 | EraseFRAM_430Xv2 - Erase FRAM memory |
71 | 1.6 10/11 FB/RL Fixed JTAG mailbox ready check |
72 | Added function descriptions |
73 | Added FRAM write through JTAG mailbox |
74 | 1.7 06/12 RL Updated commentaries |
75 | 1.8 10/12 RL Removed hard-coded RAM addresses - RAM start address |
76 | has to be specified in the config header file |
77 | 1.9 03/13 RL/MD Added unlock functions for Info A & BSL |
78 | 1.10 2/14 RL Added FRAM robustness flow in ExecutePOR_430Xv2 and |
79 | WriteMem_430Xv2 for MSP430FR59xx devices |
80 | 1.11 5/14 RL Removed FRAM functionality (see Replicator430FR) |
81 |----------------------------------------------------------------------------|
82 | Designed 2008 by Texas Instruments Germany |
83 \*==========================================================================*/
86 /****************************************************************************/
87 /* INCLUDES */
88 /****************************************************************************/
89 
90 #include "LowLevelFunc430Xv2.h"
91 #include "JTAGfunc430Xv2.h"
92 #include "FlashErase.c"
93 #include "FlashWrite.c"
94 
95 // Spy-Bi-Wire addons --------------------------------------------------------
96 extern byte tdo_bit;
97 extern byte TCLK_saved; // holds the last value of TCLK before entering a JTAG sequence
98 
99 /****************************************************************************/
100 /* Low level routines for accessing the target device via JTAG: */
101 /****************************************************************************/
102 
103 //----------------------------------------------------------------------------
108 static word DR_Shift16(word data)
109 {
110 #ifdef SPYBIWIRE_MODE
111  // JTAG FSM state = Run-Test/Idle
112  if (TCLK_saved & SBWDATO)
113  {
114  TMSH_TDIH();
115  }
116  else
117  {
118  TMSH_TDIL();
119  }
120  // JTAG FSM state = Select DR-Scan
121  TMSL_TDIH();
122  // JTAG FSM state = Capture-DR
123  TMSL_TDIH();
124 #else
125  // JTAG FSM state = Run-Test/Idle
126  SetTMS();
127  ClrTCK();
128  SetTCK();
129 
130  // JTAG FSM state = Select DR-Scan
131  ClrTMS();
132  ClrTCK();
133  SetTCK();
134  // JTAG FSM state = Capture-DR
135  ClrTCK();
136  SetTCK();
137 #endif
138  // JTAG FSM state = Shift-DR, Shift in TDI (16-bit)
139  return(AllShifts(F_WORD, data));
140  // JTAG FSM state = Run-Test/Idle
141 }
142 
143 //----------------------------------------------------------------------------
148 static unsigned long DR_Shift20(unsigned long address)
149 {
150 #ifdef SPYBIWIRE_MODE
151  // JTAG FSM state = Run-Test/Idle
152  if (TCLK_saved & SBWDATO)
153  {
154  TMSH_TDIH();
155  }
156  else
157  {
158  TMSH_TDIL();
159  }
160  // JTAG FSM state = Select DR-Scan
161  TMSL_TDIH();
162  // JTAG FSM state = Capture-DR
163  TMSL_TDIH();
164 #else
165  // JTAG FSM state = Run-Test/Idle
166  SetTMS();
167  ClrTCK();
168  SetTCK();
169 
170  // JTAG FSM state = Select DR-Scan
171  ClrTMS();
172  ClrTCK();
173  SetTCK();
174  // JTAG FSM state = Capture-DR
175  ClrTCK();
176  SetTCK();
177 #endif
178  // JTAG FSM state = Shift-DR, Shift in TDI (16-bit)
179  return(AllShifts(F_ADDR, address));
180  // JTAG FSM state = Run-Test/Idle
181 }
182 
183 //----------------------------------------------------------------------------
189 static word IR_Shift(byte instruction)
190 {
191 #ifdef SPYBIWIRE_MODE
192  // JTAG FSM state = Run-Test/Idle
193  if (TCLK_saved & SBWDATO)
194  {
195  TMSH_TDIH();
196  }
197  else
198  {
199  TMSH_TDIL();
200  }
201  // JTAG FSM state = Select DR-Scan
202  TMSH_TDIH();
203 
204  // JTAG FSM state = Select IR-Scan
205  TMSL_TDIH();
206  // JTAG FSM state = Capture-IR
207  TMSL_TDIH();
208 #else
209  // JTAG FSM state = Run-Test/Idle
210  SetTMS();
211  ClrTCK();
212  SetTCK();
213  // JTAG FSM state = Select DR-Scan
214  ClrTCK();
215  SetTCK();
216 
217  // JTAG FSM state = Select IR-Scan
218  ClrTMS();
219  ClrTCK();
220  SetTCK();
221  // JTAG FSM state = Capture-IR
222  ClrTCK();
223  SetTCK();
224 #endif
225  // JTAG FSM state = Shift-IR, Shift in TDI (8-bit)
226  return(AllShifts(F_BYTE, instruction));
227  // JTAG FSM state = Run-Test/Idle
228 }
229 
230 //----------------------------------------------------------------------------
232 static void ResetTAP(void)
233 {
234  word i;
235 
236 #ifdef SPYBIWIRE_MODE
237  // Reset JTAG FSM
238  for (i = 6; i > 0; i--)
239  {
240  TMSH_TDIH();
241  }
242  // JTAG FSM is now in Test-Logic-Reset
243  TMSL_TDIH(); // now in Run/Test Idle
244 #else
245  // process TDI first to settle fuse current
246  SetTDI();
247  SetTMS();
248  SetTCK();
249 
250  // Reset JTAG FSM
251  for (i = 6; i > 0; i--)
252  {
253  ClrTCK();
254  SetTCK();
255  }
256  // JTAG FSM is now in Test-Logic-Reset
257  ClrTCK();
258  ClrTMS();
259  SetTCK();
260  ClrTCK();
261  SetTCK();
262  ClrTCK();
263  // JTAG FSM is now in Run-Test/IDLE
264 #endif
265 }
266 
267 //----------------------------------------------------------------------------
272 static word ExecutePOR_430Xv2(void)
273 {
274  word id = 0;
275 
276  id = IR_Shift(IR_CNTRL_SIG_CAPTURE);
277 
278  // provide one clock cycle to empty the pipe
279  ClrTCLK();
280  SetTCLK();
281 
282  // prepare access to the JTAG CNTRL SIG register
283  IR_Shift(IR_CNTRL_SIG_16BIT);
284  // release CPUSUSP signal and apply POR signal
285  DR_Shift16(0x0C01);
286  // release POR signal again
287  DR_Shift16(0x0401);
288 
289  ClrTCLK();
290  SetTCLK();
291  ClrTCLK();
292  SetTCLK();
293  ClrTCLK();
294  SetTCLK();
295 
296  // two more to release CPU internal POR delay signals
297  ClrTCLK();
298  SetTCLK();
299  ClrTCLK();
300  SetTCLK();
301 
302  // now set CPUSUSP signal again
303  IR_Shift(IR_CNTRL_SIG_16BIT);
304  DR_Shift16(0x0501);
305  // and provide one more clock
306  ClrTCLK();
307  SetTCLK();
308  // the CPU is now in 'Full-Emulation-State'
309 
310  // disable Watchdog Timer on target device now by setting the HOLD signal
311  // in the WDT_CNTRL register
312  WriteMem_430Xv2(F_WORD, 0x015C, 0x5A80);
313 
314  // Check if device is in Full-Emulation-State again and return status
315  IR_Shift(IR_CNTRL_SIG_CAPTURE);
316  if(DR_Shift16(0) & 0x0301)
317  {
318  return(STATUS_OK);
319  }
320 
321  return(STATUS_ERROR);
322 }
323 
324 //----------------------------------------------------------------------------
327 static void SetPC_430Xv2(unsigned long Addr)
328 {
329  unsigned short Mova;
330  unsigned short Pc_l;
331 
332  Mova = 0x0080;
333  Mova += (unsigned short)((Addr>>8) & 0x00000F00);
334  Pc_l = (unsigned short)((Addr & 0xFFFF));
335 
336  // Check Full-Emulation-State at the beginning
337  IR_Shift(IR_CNTRL_SIG_CAPTURE);
338  if(DR_Shift16(0) & 0x0301)
339  {
340  // MOVA #imm20, PC
341  ClrTCLK();
342  // take over bus control during clock LOW phase
343  IR_Shift(IR_DATA_16BIT);
344  SetTCLK();
345  DR_Shift16(Mova);
346  ClrTCLK();
347  // above is just for delay
348  IR_Shift(IR_CNTRL_SIG_16BIT);
349  DR_Shift16(0x1400);
350  IR_Shift(IR_DATA_16BIT);
351  ClrTCLK();
352  SetTCLK();
353  DR_Shift16(Pc_l);
354  ClrTCLK();
355  SetTCLK();
356  DR_Shift16(0x4303);
357  ClrTCLK();
358  IR_Shift(IR_ADDR_CAPTURE);
359  DR_Shift20(0x00000);
360  }
361 }
362 
363 //----------------------------------------------------------------------------
366 static unsigned long i_ReadJmbOut(void)
367 {
368  unsigned short sJMBINCTL;
369  unsigned long lJMBOUT = 0;
370  unsigned short sJMBOUT0, sJMBOUT1;
371 
372  sJMBINCTL = 0;
373 
374  IR_Shift(IR_JMB_EXCHANGE);// start exchange
375  lJMBOUT = DR_Shift16(sJMBINCTL);
376 
377  if(lJMBOUT & OUT1RDY)// check if new data available
378  {
379  sJMBINCTL |= JMB32B + OUTREQ;
380  lJMBOUT = DR_Shift16(sJMBINCTL);
381  sJMBOUT0 = (unsigned short)DR_Shift16(0);
382  sJMBOUT1 = (unsigned short)DR_Shift16(0);
383 
384  lJMBOUT = ((unsigned long)sJMBOUT1<<16) + sJMBOUT0;
385  }
386 
387  return lJMBOUT;
388 }
389 
390 //----------------------------------------------------------------------------
395 static short i_WriteJmbIn16(word dataX)
396 {
397  unsigned short sJMBINCTL;
398  unsigned short sJMBIN0;
399  unsigned long Timeout = 0;
400  sJMBIN0 = (unsigned short)(dataX & 0x0000FFFF);
401  sJMBINCTL = INREQ;
402 
403  IR_Shift(IR_JMB_EXCHANGE);
404  do
405  {
406  Timeout++;
407  if(Timeout >= 3000)
408  {
409  return STATUS_ERROR;
410  }
411  }
412  while(!(DR_Shift16(0x0000) & IN0RDY) && Timeout < 3000);
413  if(Timeout < 3000)
414  {
415  DR_Shift16(sJMBINCTL);
416  DR_Shift16(sJMBIN0);
417  }
418  return STATUS_OK;
419 }
420 
426 static short i_WriteJmbIn32(unsigned short dataX,unsigned short dataY)
427 {
428  unsigned short sJMBINCTL;
429  unsigned short sJMBIN0,sJMBIN1;
430  unsigned long Timeout = 0;
431 
432  sJMBIN0 = (unsigned short)(dataX & 0x0000FFFF);
433  sJMBIN1 = (unsigned short)(dataY & 0x0000FFFF);
434  sJMBINCTL = JMB32B | INREQ;
435 
436  IR_Shift(IR_JMB_EXCHANGE);
437  do
438  {
439  Timeout++;
440  if(Timeout >= 3000)
441  {
442  return STATUS_ERROR;
443  }
444  }
445  while(!(DR_Shift16(0x0000) & IN0RDY) && Timeout < 3000);
446 
447  if(Timeout < 3000)
448  {
449  sJMBINCTL = 0x11;
450  DR_Shift16(sJMBINCTL) ;
451  DR_Shift16(sJMBIN0);
452  DR_Shift16(sJMBIN1);
453  }
454  return STATUS_OK;
455 }
456 
457 //----------------------------------------------------------------------------
465 word VerifyPSA_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
466 {
467  word TDOword;
468  unsigned long i;
469  const word POLY = 0x0805; // Polynom value for PSA calculation
470  word PSA_CRC = (word)(StartAddr-2); // Start value for PSA calculation
471 
472  ExecutePOR_430Xv2();
473 
474  SetPC_430Xv2(StartAddr);
475 
476  SetTCLK();
477 
478  IR_Shift(IR_CNTRL_SIG_16BIT);
479  DR_Shift16(0x0501);
480 
481  IR_Shift(IR_DATA_16BIT);
482  DR_Shift16(PSA_CRC);
483 
484  IR_Shift(IR_DATA_PSA);
485 
486  for (i = 0; i < Length; i++)
487  {
488  // Calculate the PSA (Pseudo Signature Analysis) value
489  if ((PSA_CRC & 0x8000) == 0x8000)
490  {
491  PSA_CRC ^= POLY;
492  PSA_CRC <<= 1;
493  PSA_CRC |= 0x0001;
494  }
495  else
496  {
497  PSA_CRC <<= 1;
498  }
499  // if pointer is 0 then use erase check mask, otherwise data
500  &DataArray[0] == 0 ? (PSA_CRC ^= 0xFFFF) : (PSA_CRC ^= DataArray[i]);
501 
502  ClrTCLK();
503 
504 #ifdef SPYBIWIRE_MODE
505 
506  TMSH_TDIH();
507  TMSL_TDIH();
508  TMSL_TDIH();
509  TMSH_TDIH();
510  TMSH_TDIH();
511  TMSL_TDIH();
512 #else
513  // Clock through the PSA
514  ClrTCK();
515 
516  SetTMS();
517  SetTCK(); // Select DR scan
518  ClrTCK();
519  ClrTMS();
520 
521  SetTCK(); // Capture DR
522  ClrTCK();
523 
524  SetTCK(); // Shift DR
525  ClrTCK();
526 
527  SetTMS();
528  SetTCK(); // Exit DR
529  ClrTCK();
530 
531  // Set JTAG FSM back into Run-Test/Idle
532  SetTCK();
533  ClrTMS();
534  ClrTCK();
535  SetTCK();
536 
537 #endif
538  SetTCLK();
539 
540  }
541 
542  IR_Shift(IR_SHIFT_OUT_PSA);
543  TDOword = DR_Shift16(0x0000); // Read out the PSA value
544 
545  ExecutePOR_430Xv2();
546 
547  return((TDOword == PSA_CRC) ? STATUS_OK : STATUS_ERROR);
548 }
549 
550 /****************************************************************************/
551 /* High level routines for accessing the target device via JTAG: */
552 /* */
553 /* For the following section, the user is relieved from coding anything. */
554 /* To provide better understanding and clearness, some functionality is */
555 /* coded generously. (Code and speed optimization enhancements may */
556 /* be desired) */
557 /****************************************************************************/
558 
559 //----------------------------------------------------------------------------
561 static void ConnectJTAG()
562 {
563  // drive JTAG/TEST signals
564  DrvSignals();
565  MsDelay(15); // delay 15ms
566 }
567 //----------------------------------------------------------------------------
569 static void StopJtag (void)
570 {
571  // release JTAG/TEST signals
572  RlsSignals();
573  MsDelay(15); // delay 15ms
574 }
575 
578 static void EntrySequences_RstHigh_SBW()
579 {
580  ClrTST(); //1
581  MsDelay(4); // reset TEST logic
582 
583  SetRST(); //2
584 
585  SetTST(); //3
586  MsDelay(20); // activate TEST logic
587 
588  // phase 1
589  SetRST(); //4
590  usDelay(60);
591 
592  // phase 2 -> TEST pin to 0, no change on RST pin
593  // for Spy-Bi-Wire
594  _DINT();
595  ClrTST();
596 
597  // phase 3
598  usDelay(1);
599  // phase 4 -> TEST pin to 1, no change on RST pin
600  // for Spy-Bi-Wire
601  SetTST();
602  _EINT();
603  //_EINT_FET();
604  usDelay(60);
605 
606  // phase 5
607  MsDelay(5);
608 }
609 
612 static void EntrySequences_RstLow_SBW()
613 {
614  ClrTST(); //1
615  MsDelay(1); // reset TEST logic
616 
617  ClrRST(); //2
618  MsDelay(50);
619 
620  SetTST(); //3
621  MsDelay(100); // activate TEST logic
622 
623  // phase 1
624  SetRST(); //4
625  usDelay(40);
626 
627  // phase 2 -> TEST pin to 0, no change on RST pin
628  // for Spy-Bi-Wire
629  _DINT();
630  ClrTST(); //5
631 
632  usDelay(1);
633 
634  // phase 4 -> TEST pin to 1, no change on RST pin
635  // for Spy-Bi-Wire
636  SetTST(); //7
637  _EINT();
638  usDelay(40);
639  MsDelay(5);
640 }
641 
644 static void EntrySequences_RstHigh_JTAG()
645 {
646  ClrTST(); //1
647  MsDelay(4); // reset TEST logic
648 
649  SetRST(); //2
650 
651  SetTST(); //3
652  MsDelay(20); // activate TEST logic
653 
654  // phase 1
655  ClrRST(); //4
656  usDelay(60);
657 
658  // phase 2 -> TEST pin to 0, no change on RST pin
659  // for 4-wire JTAG clear Test pin
660  ClrTST(); //5
661 
662  // phase 3
663  usDelay(1);
664 
665  // phase 4 -> TEST pin to 1, no change on RST pin
666  // for 4-wire JTAG
667  SetTST();//7
668  usDelay(60);
669 
670  // phase 5
671  SetRST();
672  MsDelay(5);
673 }
674 
677 static void EntrySequences_RstLow_JTAG()
678 {
679  _DINT();
680  ClrTST(); //1
681  MsDelay(4); //reset TEST logic
682 
683  ClrRST(); //2
684  MsDelay(50);
685 
686  SetTST(); //3
687  MsDelay(50); //activate TEST logic
688 
689  ClrRST(); //4
690  usDelay(40);
691 
692  // for 4-wire JTAG clear Test pin Test(0)
693  ClrTST(); //5
694  usDelay(2);
695 
696  // for 4-wire JTAG -drive Reset(0)
697  ClrRST();
698  usDelay(2);
699 
700  // 4-wire JTAG - Test (1)
701  SetTST();
702  MsDelay(5);
703  _EINT();
704  SetRST();
705 }
706 
707 //----------------------------------------------------------------------------
708 extern void configure_IO_JTAG( void );
709 //----------------------------------------------------------------------------
714 static word magicPattern(void)
715 {
716  word deviceJtagID = 0;
717 
718  // Enable the JTAG interface to the device.
719  ConnectJTAG();
720  // Apply again 4wire/SBW entry Sequence.
721  // set ResetPin = 0
722  if(INTERFACE == SPYBIWIRE_IF)
723  {
724  EntrySequences_RstLow_SBW();
725  }
726  else
727  {
728  EntrySequences_RstLow_JTAG();
729  }
730  // reset TAP state machine -> Run-Test/Idle
731  ResetTAP();
732  // feed JTAG mailbox with magic pattern
733  if(i_WriteJmbIn16(STOP_DEVICE) == STATUS_OK)
734  {
735  // Apply again 4wire/SBW entry Sequence.
736  if(INTERFACE == SPYBIWIRE_IF)
737  {
738  EntrySequences_RstHigh_SBW();
739  }
740  else
741  {
742  EntrySequences_RstHigh_JTAG();
743  }
744  ResetTAP(); // reset TAP state machine -> Run-Test/Idle
745 
746  deviceJtagID = (word)IR_Shift(IR_CNTRL_SIG_CAPTURE);
747 
748  if(deviceJtagID == JTAG_ID91)
749  {
750  // if Device is in LPM.x5 -> reset IO lock of JTAG pins and Configure it for debug
751  IR_Shift(IR_TEST_3V_REG);
752  DR_Shift16(0x4020);
753  }
754  return deviceJtagID;
755  }
756 
757  // if Device is in LPM.x5 -> reset IO lock of JTAG pins and Configure it for debug
758 #ifdef LPM5_ACTIVATED
759  {
760 #ifdef SPYBIWIREJTAG_IF // run 2 wire mode of 4 wire selection because 4wire pins are locked by JTAG lock
761 
762  ConnectJTAG();
763  StartJtagJSbw(RSTLOW_SBW);
764  jResetJtagTap();
766  jRelease();
767  MsDelay(60);
768 
769  // reset JTAG lock
771  StartJtagJSbw(RSTHIGH_SBW);
772  jResetJtagTap();
773  jsbwJtagUnlock();
774  MsDelay(60);
775 
777  EntrySequences_RstHigh_JTAG();
778  ResetTAP(); // reset TAP state machine -> Run-Test/Idle
779  MsDelay(60);
780  deviceJtagID = (word)IR_Shift(IR_CNTRL_SIG_CAPTURE);
781  if(deviceJtagID == JTAG_ID91)
782  {
783  return deviceJtagID;
784  }
785 #endif
786  }
787 #endif
788  return 1; // return 1 as an invalid JTAG ID
789 }
790 
791 //----------------------------------------------------------------------------
795 static word GetCoreID (void)
796 {
797  word i;
798  word JtagId = 0; //initialize JtagId with an invalid value
799  for (i = 0; i < MAX_ENTRY_TRY; i++)
800  {
801  // release JTAG/TEST signals to safely reset the test logic
802  StopJtag();
803  // establish the physical connection to the JTAG interface
804  ConnectJTAG();
805  // Apply again 4wire/SBW entry Sequence.
806  // set ResetPin =1
807 
808  if(INTERFACE == SPYBIWIRE_IF)
809  {
810  EntrySequences_RstHigh_SBW();
811  }
812  else
813  {
814  EntrySequences_RstHigh_JTAG();
815  }
816  // reset TAP state machine -> Run-Test/Idle
817  ResetTAP();
818  // shift out JTAG ID
819  JtagId = (word)IR_Shift(IR_CNTRL_SIG_CAPTURE);
820 
821  // break if a valid JTAG ID is being returned
822  if((JtagId == JTAG_ID91) || (JtagId == JTAG_ID99)) //****************************
823  {
824  break;
825  }
826  }
827  if(i >= MAX_ENTRY_TRY)
828  {
829 
830  // if connected device is MSP4305438 JTAG Mailbox is not usable
831 #ifdef ACTIVATE_MAGIC_PATTERN
832  for(i = 0; i < MAX_ENTRY_TRY; i++)
833  {
834  // if no JTAG ID is returns -> apply magic pattern to stop user code execution
835  JtagId = magicPattern();
836 
837  if((JtagId == 1) || (i >= MAX_ENTRY_TRY))
838  {
839  // if magic pattern failed and 4 tries passed -> return status error
840  return(STATUS_ERROR);
841  }
842  else
843  {
844  break;
845  }
846  }
847  // For MSP430F5438 family mailbox is not functional in reset state.
848  // Because of this issue the magicPattern is not usable on MSP430F5438 family devices
849 #else
850  return(STATUS_ERROR);
851 #endif
852  }
853  if((JtagId == JTAG_ID91) || (JtagId == JTAG_ID99)) //****************************
854  {
855  return(STATUS_OK);
856  }
857  else
858  {
859  return(STATUS_ERROR);
860  }
861 }
862 
863 //----------------------------------------------------------------------------
868 {
869  IR_Shift(IR_COREIP_ID);
870  CoreId = DR_Shift16(0);
871  if(CoreId == 0)
872  {
873  return(STATUS_ERROR);
874  }
875  IR_Shift(IR_DEVICE_ID);
876  DeviceIdPointer = DR_Shift20(0);
877  // The ID pointer is an un-scrambled 20bit value
878  return(STATUS_OK);
879 }
880 
881 //----------------------------------------------------------------------------
885 static word SyncJtag_AssertPor (void)
886 {
887  word i = 0;
888 
889  IR_Shift(IR_CNTRL_SIG_16BIT);
890  DR_Shift16(0x1501); // Set device into JTAG mode + read
891 
892  if ((IR_Shift(IR_CNTRL_SIG_CAPTURE) != JTAG_ID91) && (IR_Shift(IR_CNTRL_SIG_CAPTURE) != JTAG_ID99)) //****************
893  {
894  return(STATUS_ERROR);
895  }
896  // wait for sync
897  while(!(DR_Shift16(0) & 0x0200) && i < 50)
898  {
899  i++;
900  };
901  // continues if sync was successful
902  if(i >= 50)
903  {
904  return(STATUS_ERROR);
905  }
906 
907  // execute a Power-On-Reset
908  if(ExecutePOR_430Xv2() != STATUS_OK)
909  {
910  return(STATUS_ERROR);
911  }
912 
913  return(STATUS_OK);
914 }
915 
916 //----------------------------------------------------------------------------
923 {
924  if(GetCoreID () != STATUS_OK)
925  {
926  return(STATUS_ERROR);
927  }
928  if (IsLockKeyProgrammed()) // Stop here if fuse is already blown
929  {
930  return(STATUS_FUSEBLOWN);
931  }
932  if (GetCoreipIdXv2()!= STATUS_OK)
933  {
934  return(STATUS_ERROR);
935  }
936  if(SyncJtag_AssertPor() != STATUS_OK)
937  {
938  return(STATUS_ERROR);
939  }
940  // CPU is now in Full-Emulation-State
941  // read DeviceId from memory
942  ReadMemQuick_430Xv2(DeviceIdPointer + 4, 1, (word*)&DeviceId);
943 
944  return(STATUS_OK);
945 }
946 
947 //----------------------------------------------------------------------------
951 void ReleaseDevice_430Xv2(unsigned long Addr)
952 {
953  switch(Addr)
954  {
955  case V_BOR:
956 
957  // perform a BOR via JTAG - we loose control of the device then...
958  IR_Shift(IR_TEST_REG);
959  DR_Shift16(0x0200);
960  MsDelay(5); // wait some time before doing any other action
961  // JTAG control is lost now - GetDevice() needs to be called again to gain control.
962  break;
963 
964  case V_RESET:
965 
966  IR_Shift(IR_CNTRL_SIG_16BIT);
967  DR_Shift16(0x0C01); // Perform a reset
968  DR_Shift16(0x0401);
969  IR_Shift(IR_CNTRL_SIG_RELEASE);
970  break;
971 
972  default:
973 
974  SetPC_430Xv2(Addr); // Set target CPU's PC
975  // prepare release & release
976  SetTCLK();
977  IR_Shift(IR_CNTRL_SIG_16BIT);
978  DR_Shift16(0x0401);
979  IR_Shift(IR_ADDR_CAPTURE);
980  IR_Shift(IR_CNTRL_SIG_RELEASE);
981  }
982 }
983 
984 //----------------------------------------------------------------------------
989 void WriteMem_430Xv2(word Format, unsigned long Addr, word Data)
990 {
991  // Check Init State at the beginning
992  IR_Shift(IR_CNTRL_SIG_CAPTURE);
993  if(DR_Shift16(0) & 0x0301)
994  {
995  ClrTCLK();
996  IR_Shift(IR_CNTRL_SIG_16BIT);
997  if (Format == F_WORD)
998  {
999  DR_Shift16(0x0500);
1000  }
1001  else
1002  {
1003  DR_Shift16(0x0510);
1004  }
1005  IR_Shift(IR_ADDR_16BIT);
1006  DR_Shift20(Addr);
1007 
1008  SetTCLK();
1009  // New style: Only apply data during clock high phase
1010  IR_Shift(IR_DATA_TO_ADDR);
1011  DR_Shift16(Data); // Shift in 16 bits
1012  ClrTCLK();
1013  IR_Shift(IR_CNTRL_SIG_16BIT);
1014  DR_Shift16(0x0501);
1015  SetTCLK();
1016  // one or more cycle, so CPU is driving correct MAB
1017  ClrTCLK();
1018  SetTCLK();
1019  // Processor is now again in Init State
1020  }
1021 }
1022 
1023 //----------------------------------------------------------------------------
1028 void WriteMemQuick_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
1029 {
1030  unsigned long i;
1031 
1032  for (i = 0; i < Length; i++)
1033  {
1034  WriteMem_430Xv2(F_WORD, StartAddr, DataArray[i]);
1035  StartAddr += 2;
1036  }
1037 }
1038 
1039 //----------------------------------------------------------------------------
1045 void WriteFLASH_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
1046 {
1047  word loadAddr = RAM_START_ADDRESS; // RAM start address specified in config header file
1048  word startAddr = loadAddr + FlashWrite_o[0]; // start address of the program in traget RAM
1049 
1050  FlashWrite_o[2] = (unsigned short)(StartAddr); // set write start address
1051  FlashWrite_o[3] = (unsigned short)(StartAddr>>16);
1052  FlashWrite_o[4] = (unsigned short)(Length); // set number of words to write
1053  FlashWrite_o[5] = (unsigned short)(Length>>16);
1054  FlashWrite_o[6] = SegmentInfoAKey5xx; // FCTL3: lock/unlock INFO Segment A
1055  // default = locked
1056 
1057  WriteMemQuick_430Xv2(loadAddr, FlashWrite_o_length/2, (word*)FlashWrite_o);
1058  ReleaseDevice_430Xv2(startAddr);
1059 
1060  {
1061  unsigned long Jmb = 0;
1062  unsigned long Timeout = 0;
1063 
1064  do
1065  {
1066  Jmb = i_ReadJmbOut();
1067  Timeout++;
1068  }
1069  while(Jmb != 0xABADBABE && Timeout < 3000);
1070 
1071  if(Timeout < 3000)
1072  {
1073  unsigned long i;
1074 
1075  for(i = 0; i < Length; i++)
1076  {
1077  i_WriteJmbIn16(DataArray[i]);
1078  //usDelay(100); // delay 100us - added by GC
1079  }
1080  }
1081  }
1082  {
1083  unsigned long Jmb = 0;
1084  unsigned long Timeout = 0;
1085 
1086  do
1087  {
1088  Jmb = i_ReadJmbOut();
1089  Timeout++;
1090  }
1091  while(Jmb != 0xCAFEBABE && Timeout < 3000);
1092  }
1093 
1094  SyncJtag_AssertPor();
1095 
1096  // clear RAM here - init with JMP $
1097  {
1098  word i;
1099 
1100  for (i = 0; i < FlashWrite_o_length/2; i++)
1101  {
1102  WriteMem_430Xv2(F_WORD, loadAddr, 0x3fff);
1103  loadAddr += 2;
1104  }
1105  }
1106 }
1107 
1108 //----------------------------------------------------------------------------
1118 word WriteFLASHallSections_430Xv2(const unsigned int *data, const unsigned long *address, const unsigned long *length_of_sections, const unsigned long sections)
1119 {
1120  int i, init = 1;
1121 
1122  for(i = 0; i < sections; i++)
1123  {
1124  // Write/Verify(PSA) one FLASH section
1125  WriteFLASH(address[i], length_of_sections[i], (word*)&data[init-1]);
1126  if (!VerifyMem(address[i], length_of_sections[i], (word*)&data[init-1]))
1127  {
1128  return(STATUS_ERROR);
1129  }
1130  init += length_of_sections[i];
1131  }
1132  return(STATUS_OK);
1133 }
1134 
1135 //----------------------------------------------------------------------------
1140 word ReadMem_430Xv2(word Format, unsigned long Addr)
1141 {
1142  word TDOword = 0;
1143 
1144  // Check Init State at the beginning
1145  IR_Shift(IR_CNTRL_SIG_CAPTURE);
1146  if(DR_Shift16(0) & 0x0301)
1147  {
1148  // Read Memory
1149  ClrTCLK();
1150  IR_Shift(IR_CNTRL_SIG_16BIT);
1151  if (Format == F_WORD)
1152  {
1153  DR_Shift16(0x0501); // Set word read
1154  }
1155  else
1156  {
1157  DR_Shift16(0x0511); // Set byte read
1158  }
1159  IR_Shift(IR_ADDR_16BIT);
1160  DR_Shift20(Addr); // Set address
1161  IR_Shift(IR_DATA_TO_ADDR);
1162  SetTCLK();
1163  ClrTCLK();
1164  TDOword = DR_Shift16(0x0000); // Shift out 16 bits
1165 
1166  SetTCLK();
1167  // one or more cycle, so CPU is driving correct MAB
1168  ClrTCLK();
1169  SetTCLK();
1170  // Processor is now again in Init State
1171  }
1172 
1173  return TDOword;
1174 }
1175 
1176 //----------------------------------------------------------------------------
1181 void ReadMemQuick_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
1182 {
1183  unsigned long i, lPc = 0;
1184 
1185  // Set PC to 'safe' address
1186  if (IR_Shift(IR_CNTRL_SIG_CAPTURE) == JTAG_ID99)
1187  {
1188  lPc = 0x00000004;
1189  }
1190 
1191  SetPC_430Xv2(StartAddr);
1192  SetTCLK();
1193  IR_Shift(IR_CNTRL_SIG_16BIT);
1194  DR_Shift16(0x0501);
1195  IR_Shift(IR_ADDR_CAPTURE);
1196 
1197  IR_Shift(IR_DATA_QUICK);
1198 
1199  for (i = 0; i < Length; i++)
1200  {
1201  SetTCLK();
1202  ClrTCLK();
1203  *DataArray++ = DR_Shift16(0); // Read data from memory.
1204  }
1205 
1206  if(lPc)
1207  {
1208  SetPC_430Xv2(lPc);
1209  }
1210  SetTCLK();
1211 
1212 }
1213 
1214 //----------------------------------------------------------------------------
1221 void EraseFLASH_430Xv2(word EraseMode, unsigned long EraseAddr)
1222 {
1223  word loadAddr = RAM_START_ADDRESS; // RAM start address specified in config header file
1224  word startAddr = loadAddr + FlashErase_o[0]; // start address of the program in target RAM
1225 
1226  FlashErase_o[2] = (unsigned short)(EraseAddr); // set dummy write address
1227  FlashErase_o[3] = (unsigned short)(EraseAddr>>16);
1228  FlashErase_o[4] = EraseMode; // set erase mode
1229  FlashErase_o[5] = SegmentInfoAKey5xx; // FCTL3: lock/unlock INFO Segment A
1230  // default = locked
1231 
1232  WriteMemQuick_430Xv2(loadAddr, FlashErase_o_length/2, (word*)FlashErase_o);
1233  ReleaseDevice_430Xv2(startAddr);
1234 
1235  {
1236  unsigned long Jmb = 0;
1237  unsigned long Timeout = 0;
1238 
1239  do
1240  {
1241  Jmb = i_ReadJmbOut();
1242  Timeout++;
1243  }
1244  while(Jmb != 0xCAFEBABE && Timeout < 3000);
1245  }
1246 
1247  SyncJtag_AssertPor();
1248 
1249  // clear RAM here - init with JMP $
1250  {
1251  word i;
1252 
1253  for (i = 0; i < FlashErase_o_length/2; i++)
1254  {
1255  WriteMem_430Xv2(F_WORD, loadAddr, 0x3fff);
1256  loadAddr += 2;
1257  }
1258  }
1259 }
1260 
1261 //----------------------------------------------------------------------------
1269 void EraseFLASH_430Xv2_wo_release(word EraseMode, unsigned long EraseAddr)
1270 {
1271  word loadAddr = RAM_START_ADDRESS; // RAM start address specified in config header file
1272  word startAddr = loadAddr + FlashErase_o[0]; // start address of the program in target RAM
1273 
1274  FlashErase_o[2] = (unsigned short)(EraseAddr); // set dummy write address
1275  FlashErase_o[3] = (unsigned short)(EraseAddr>>16);
1276  FlashErase_o[4] = EraseMode; // set erase mode
1277  FlashErase_o[5] = SegmentInfoAKey5xx; // FCTL3: lock/unlock INFO Segment A
1278  // default = locked
1279 
1280  WriteMemQuick_430Xv2(loadAddr, FlashErase_o_length/2, (word*)FlashErase_o);
1281 
1282  {
1283  word i;
1284  SetPC_430Xv2(startAddr);
1285  for (i=110; i--;)
1286  {
1287  ClrTCLK();
1288  SetTCLK();
1289  }
1290  }
1291 
1292  //max mass/segment erase time for F543x is 32ms
1293  //do not check mailbox, just wait..
1294  MsDelay(35);
1295 
1296  //let Erase function finish
1297  {
1298  word i;
1299  for (i=110; i--;) //110 to let the erase routine finish the restauration
1300  {
1301  ClrTCLK();
1302  SetTCLK();
1303  }
1304  }
1305 
1306  SyncJtag_AssertPor();
1307 
1308  // clear RAM here - init with JMP $
1309  {
1310  word i;
1311 
1312  for (i = 0; i < FlashErase_o_length/2; i++)
1313  {
1314  WriteMem_430Xv2(F_WORD, loadAddr, 0x3fff);
1315  loadAddr += 2;
1316  }
1317  }
1318 }
1319 
1320 //----------------------------------------------------------------------------
1326 word EraseCheck_430Xv2(unsigned long StartAddr, unsigned long Length)
1327 {
1328  return (VerifyPSA_430Xv2(StartAddr, Length, 0));
1329 }
1330 
1331 //----------------------------------------------------------------------------
1338 word VerifyMem_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
1339 {
1340  return (VerifyPSA_430Xv2(StartAddr, Length, DataArray));
1341 }
1342 //------------------------------------------------------------------------
1345 word ProgramLockKey(void)
1346 {
1347  word LockKey[2] = { 0xDEAD, 0xBABE };
1348 
1349  // unprotect BSL memory by writing to the SYSBSLC register
1350  // to reset the BSL protection bit (SYSBSLPE)
1351  WriteMem(F_WORD, 0x0182, 0x0003);
1352 
1353  // write JTAG lock key to flash memory
1354  WriteFLASH(0x17FC, 2, LockKey);
1355 
1356  // now perform a BOR via JTAG - we loose control of the device then...
1357  IR_Shift(IR_TEST_REG);
1358  DR_Shift16(0x0200);
1359  MsDelay(5); // wait some time until Bootcode is executed
1360 
1361  // -> get it under JTAG control again
1362  // and return result of "is fuse blown?"
1363  return(GetDevice() == STATUS_FUSEBLOWN);
1364 }
1365 
1366 //------------------------------------------------------------------------
1370 {
1371  word i;
1372 
1373  for (i = 3; i > 0; i--) // First trial could be wrong
1374  {
1375  IR_Shift(IR_CNTRL_SIG_CAPTURE);
1376  if (DR_Shift16(0xAAAA) == 0x5555)
1377  {
1378  return(STATUS_OK); // Fuse is blown
1379  }
1380  }
1381  return(STATUS_ERROR); // Fuse is not blown
1382 }
1383 
1384 //------------------------------------------------------------------------
1387 {
1388  unsigned short BslCur;
1389 
1390  // Read SYSBSLC register
1391  BslCur = ReadMem_430Xv2(F_WORD, 0x0182);
1392  // Disable BSL area protection
1393  BslCur &= ~SYSBSLPE;
1394  // Write back SYSBSLC register
1395  WriteMem_430Xv2(F_WORD, 0x0182, BslCur);
1396 }
1397 
1398 //------------------------------------------------------------------------
1401 {
1402  SegmentInfoAKey5xx = 0xA508;
1403 }
1404 
1405 /****************************************************************************/
1406 /* END OF SOURCE FILE */
1407 /****************************************************************************/
void usDelay(word microseconds)
Delay function (resolution is ~1 us)
#define ClrTST()
SBW macro: clear TEST pin signal.
#define IR_CNTRL_SIG_RELEASE
Release the CPU from JTAG control.
word ProgramLockKey(void)
This function disables JTAG access to the target device.
#define IR_SHIFT_OUT_PSA
Shift out the PSA pattern generated by IR_DATA_PSA.
#define OUTREQ
JTAG mailbox constant -.
#define V_BOR
Triggers a "brown-out" reset on device release from JTAG control.
#define SetTCLK()
SBW macro: set TCLK signal.
#define IR_DATA_QUICK
Set the MSP430 MDB to a specific 16-bit value (RAM only)
#define OUT1RDY
JTAG mailbox constant -.
byte tdo_bit
Holds the value of TDO-bit.
#define RAM_START_ADDRESS
Set the start address of the device RAM.
Definition: Config430Xv2.h:83
unsigned long AllShifts(word Format, unsigned long Data)
Shift a value into TDI (MSB first) and simultaneously shift out a value from TDO (MSB first)...
void WriteFLASH_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
This function programs/verifies an array of words into the FLASH memory by using the FLASH controller...
JTAG Function Prototypes and Definitions.
#define IR_DATA_TO_ADDR
Set the MSP430 MDB with a specific 16-bit value and write it to the memory address which is currently...
#define JTAG_ID99
JTAG identification value for 430Xv2 architecture FR59XX devices.
word EraseCheck_430Xv2(unsigned long StartAddr, unsigned long Length)
This function performs an Erase Check over the given memory range.
#define SetTST()
SBW macro: set TEST pin signal.
word VerifyPSA_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
This function compares the computed PSA (Pseudo Signature Analysis) value to the PSA value shifted ou...
#define IR_TEST_3V_REG
Instruction for 3 volt test register in 5xx.
#define IR_TEST_REG
Instruction for test register in 5xx.
#define IR_ADDR_16BIT
Set the MSP430 MAB to a specific 16-bit value.
byte TCLK_saved
Holds the last value of TCLK before entering a JTAG sequence.
#define SBWDATO
JTAG data_out pin in SBW mode -separate pin in MSP430F5437 - common IO translator.
unsigned short FlashErase_o[]
Holds the target code for a flash erase operation.
Definition: FlashErase.c:56
#define IR_CNTRL_SIG_CAPTURE
Read out the JTAG control signal register.
word VerifyMem_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
This function performs a Verification over the given memory range.
#define IR_DATA_PSA
Switch JTAG data register to PSA mode.
#define INREQ
JTAG mailbox constant -.
#define JTAG_ID91
JTAG identification value for 430Xv2 architecture devices.
#define STATUS_FUSEBLOWN
GetDevice returns this if the security fuse is blown.
void jResetJtagTap(void)
Reset target JTAG interface and perform fuse-HW check.
Definition: JSBW.c:154
void jsbwJtagUnlock(void)
Function for resetting the JTAG lock via JSBW.
Definition: JSBW.c:283
#define JMB32B
JTAG mailbox constant -.
word GetCoreipIdXv2()
Function to determine & compare core identification info (Xv2)
word GetDevice_430Xv2(void)
Function to take target device under JTAG control. Disables the target watchdog. Sets the global DEVI...
#define IR_DEVICE_ID
Instruction to determine device's DeviceID.
void ReleaseDevice_430Xv2(unsigned long Addr)
Function to release the target device from JTAG control.
#define SetTCK()
JTAG macro: set TCK signal.
void UnlockBsl_430Xv2Flash(void)
This function unlocks the BSL memory protection.
#define IN0RDY
JTAG mailbox constant -.
#define IR_DATA_16BIT
Set the MSP430 MDB to a specific 16-bit value with the next 16-bit data access.
void WriteMemQuick_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
This function writes an array of words into the target memory.
unsigned short FlashWrite_o[]
Holds the target code for an flash write operation.
Definition: FlashWrite.c:56
#define ClrRST()
SBW macro: clear RST signal.
#define SetTMS()
JTAG macro: set TMS signal.
#define INTERFACE
Select the interface to be used to communicate with the device.
Definition: Config430Xv2.h:68
void ReadMemQuick_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
This function reads an array of words from the memory.
#define STATUS_OK
return 1 = no error
Funclet for Flash write operations.
#define ClrTCLK()
SBW macro: clear TCLK signal.
void WriteMem_430Xv2(word Format, unsigned long Addr, word Data)
This function writes one byte/word at a given address ( <0xA00)
void StartJtagJSbw(byte states)
Start JTAG communication in JSBW mode.
Definition: JSBW.c:79
#define V_RESET
Triggers a regular reset on device release from JTAG control.
#define IR_JMB_EXCHANGE
Request a JTAG mailbox exchange.
word WriteFLASHallSections_430Xv2(const unsigned int *data, const unsigned long *address, const unsigned long *length_of_sections, const unsigned long sections)
This function programs/verifies a set of data arrays of words into a FLASH memory by using the "Write...
void MsDelay(word milliseconds)
Delay function (resolution is 1 ms)
void jRelease(void)
Releases the JSBW logic.
Definition: JSBW.c:65
#define STATUS_ERROR
return 0 = error
void EraseFLASH_430Xv2(word EraseMode, unsigned long EraseAddr)
This function performs a mass erase (with and w/o info memory) or a segment erase of a FLASH module s...
#define MAX_ENTRY_TRY
Maximum number of tries for the determination of the core identification info.
Definition: Config430Xv2.h:152
word IsLockKeyProgrammed(void)
This function checks if the JTAG lock key is programmed.
void JsbwMagicPattern(void)
Function for applying the magic pattern via JSBW.
Definition: JSBW.c:271
word ReadMem_430Xv2(word Format, unsigned long Addr)
This function reads one byte/word from a given address in memory.
#define IR_ADDR_CAPTURE
Read out the MAB data on the next 16/20-bit data access.
Funclet for Flash erase operations.
#define ClrTCK()
JTAG macro: clear TCK signal.
#define SetTDI()
JTAG macro: set TDI signal.
#define IR_COREIP_ID
Instruction to determine device's CoreIP.
#define IR_CNTRL_SIG_16BIT
Set the JTAG control signal register.
void RlsSignals(void)
Release I/O pins.
Low Level function prototypes, macros, and pin-to-signal assignments regarding to user's hardware...
void UnlockInfoA_430Xv2(void)
This function unlocks segment A of the InfoMemory (Flash)
void configure_IO_JTAG(void)
Set JTAG pins to output direction - from REP430F to target.
#define SPYBIWIRE_IF
Spy-Bi-Wire interface.
void EraseFLASH_430Xv2_wo_release(word EraseMode, unsigned long EraseAddr)
This function performs a mass erase (with and w/o info memory) or a segment erase of a FLASH module s...
#define SetRST()
SBW macro: set RST signal.
void DrvSignals(void)
Set up I/O pins for JTAG communication.
#define ClrTMS()
JTAG macro: clear TMS signal.

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