JTAGfunc430FR.c
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33 /*==========================================================================*\
34 | |
35 | JTAGfunc430FR.c |
36 | |
37 | JTAG Control Sequences for Erasing / Programming / Fuse Programming |
38 |----------------------------------------------------------------------------|
39 | Project: MSP430 FRAM Replicator |
40 | Developed using: IAR Embedded Workbench 6.20 |
41 | and: Code Composer Studio 6.0 |
42 |----------------------------------------------------------------------------|
43 | Version history: |
44 | 1.0 04/14 RL Initial version. |
45 | 1.1 02/16 RL Added workaround for inconsistency between PC and MAB |
46 |----------------------------------------------------------------------------|
47 | Designed 2014 by Texas Instruments Germany |
48 \*==========================================================================*/
51 /****************************************************************************/
52 /* INCLUDES */
53 /****************************************************************************/
54 
55 #include "LowLevelFunc430Xv2.h"
56 #include "JTAGfunc430FR.h"
57 
58 #ifdef FR4xxFR2xx
59  #include "FramEraseFR4xx.c"
60  #include "FramWriteFR4xx.c"
61  #include "msp430CodeFR4xx.h"
62 #else
63  #include "FramErase.c"
64  #include "FramWrite.c"
65  #include "msp430CodeFR57_6xx.h"
66 #endif
67 
68 
69 
70 // Spy-Bi-Wire addons --------------------------------------------------------
71 extern byte tdo_bit;
72 extern byte TCLK_saved; // holds the last value of TCLK before entering a JTAG sequence
73 
74 /****************************************************************************/
75 /* Low level routines for accessing the target device via JTAG: */
76 /****************************************************************************/
77 
78 //----------------------------------------------------------------------------
83 static word DR_Shift16(word data)
84 {
85 #ifdef SPYBIWIRE_MODE
86  // JTAG FSM state = Run-Test/Idle
87  if (TCLK_saved & SBWDATO)
88  {
89  TMSH_TDIH();
90  }
91  else
92  {
93  TMSH_TDIL();
94  }
95  // JTAG FSM state = Select DR-Scan
96  TMSL_TDIH();
97  // JTAG FSM state = Capture-DR
98  TMSL_TDIH();
99 #else
100  // JTAG FSM state = Run-Test/Idle
101  SetTMS();
102  ClrTCK();
103  SetTCK();
104 
105  // JTAG FSM state = Select DR-Scan
106  ClrTMS();
107  ClrTCK();
108  SetTCK();
109  // JTAG FSM state = Capture-DR
110  ClrTCK();
111  SetTCK();
112 #endif
113  // JTAG FSM state = Shift-DR, Shift in TDI (16-bit)
114  return(AllShifts(F_WORD, data));
115  // JTAG FSM state = Run-Test/Idle
116 }
117 
118 //----------------------------------------------------------------------------
123 static unsigned long DR_Shift20(unsigned long address)
124 {
125 #ifdef SPYBIWIRE_MODE
126  // JTAG FSM state = Run-Test/Idle
127  if (TCLK_saved & SBWDATO)
128  {
129  TMSH_TDIH();
130  }
131  else
132  {
133  TMSH_TDIL();
134  }
135  // JTAG FSM state = Select DR-Scan
136  TMSL_TDIH();
137  // JTAG FSM state = Capture-DR
138  TMSL_TDIH();
139 #else
140  // JTAG FSM state = Run-Test/Idle
141  SetTMS();
142  ClrTCK();
143  SetTCK();
144 
145  // JTAG FSM state = Select DR-Scan
146  ClrTMS();
147  ClrTCK();
148  SetTCK();
149  // JTAG FSM state = Capture-DR
150  ClrTCK();
151  SetTCK();
152 #endif
153  // JTAG FSM state = Shift-DR, Shift in TDI (16-bit)
154  return(AllShifts(F_ADDR, address));
155  // JTAG FSM state = Run-Test/Idle
156 }
157 
158 //----------------------------------------------------------------------------
164 static word IR_Shift(byte instruction)
165 {
166 #ifdef SPYBIWIRE_MODE
167  // JTAG FSM state = Run-Test/Idle
168  if (TCLK_saved & SBWDATO)
169  {
170  TMSH_TDIH();
171  }
172  else
173  {
174  TMSH_TDIL();
175  }
176  // JTAG FSM state = Select DR-Scan
177  TMSH_TDIH();
178 
179  // JTAG FSM state = Select IR-Scan
180  TMSL_TDIH();
181  // JTAG FSM state = Capture-IR
182  TMSL_TDIH();
183 #else
184  // JTAG FSM state = Run-Test/Idle
185  SetTMS();
186  ClrTCK();
187  SetTCK();
188  // JTAG FSM state = Select DR-Scan
189  ClrTCK();
190  SetTCK();
191 
192  // JTAG FSM state = Select IR-Scan
193  ClrTMS();
194  ClrTCK();
195  SetTCK();
196  // JTAG FSM state = Capture-IR
197  ClrTCK();
198  SetTCK();
199 #endif
200  // JTAG FSM state = Shift-IR, Shift in TDI (8-bit)
201  return(AllShifts(F_BYTE, instruction));
202  // JTAG FSM state = Run-Test/Idle
203 }
204 
205 //----------------------------------------------------------------------------
207 static void ResetTAP(void)
208 {
209  word i;
210 
211 #ifdef SPYBIWIRE_MODE
212  // Reset JTAG FSM
213  for (i = 6; i > 0; i--)
214  {
215  TMSH_TDIH();
216  }
217  // JTAG FSM is now in Test-Logic-Reset
218  TMSL_TDIH(); // now in Run/Test Idle
219 #else
220  // process TDI first to settle fuse current
221  SetTDI();
222  SetTMS();
223  SetTCK();
224 
225  // Reset JTAG FSM
226  for (i = 6; i > 0; i--)
227  {
228  ClrTCK();
229  SetTCK();
230  }
231  // JTAG FSM is now in Test-Logic-Reset
232  ClrTCK();
233  ClrTMS();
234  SetTCK();
235  ClrTCK();
236  SetTCK();
237  ClrTCK();
238  // JTAG FSM is now in Run-Test/IDLE
239 #endif
240 }
241 #define SAFE_FRAM_PC 0x0004
242 
243 //----------------------------------------------------------------------------
248 static word ExecutePOR_430Xv2(void)
249 {
250  // provide one clock cycle to empty the pipe
251  ClrTCLK();
252  SetTCLK();
253 
254  // prepare access to the JTAG CNTRL SIG register
255  IR_Shift(IR_CNTRL_SIG_16BIT);
256  // release CPUSUSP signal and apply POR signal
257  DR_Shift16(0x0C01);
258  // release POR signal again
259  DR_Shift16(0x0401);
260 
261 
262  // Set PC to 'safe' memory location
263  IR_Shift(IR_DATA_16BIT);
264  ClrTCLK();
265  SetTCLK();
266  ClrTCLK();
267  SetTCLK();
268  DR_Shift16(SAFE_FRAM_PC);
269  // PC is set to 0x4 - MAB value can be 0x6 or 0x8
270 
271  // drive safe address into PC
272  ClrTCLK();
273  SetTCLK();
274 
275  IR_Shift(IR_DATA_CAPTURE);
276 
277  // two more to release CPU internal POR delay signals
278  ClrTCLK();
279  SetTCLK();
280  ClrTCLK();
281  SetTCLK();
282 
283  // now set CPUSUSP signal again
284  IR_Shift(IR_CNTRL_SIG_16BIT);
285  DR_Shift16(0x0501);
286  // and provide one more clock
287  ClrTCLK();
288  SetTCLK();
289  // the CPU is now in 'Full-Emulation-State'
290 
291  // disable Watchdog Timer on target device now by setting the HOLD signal
292  // in the WDT_CNTRL register
293  unsigned short id = IR_Shift(IR_CNTRL_SIG_CAPTURE);
294  if(id == JTAG_ID98)
295  {
296  WriteMem_430Xv2(F_WORD, 0x01CC, 0x5A80);
297  }
298  else
299  {
300  WriteMem_430Xv2(F_WORD, 0x015C, 0x5A80);
301  }
302 
303  // Initialize Test Memory with default values to ensure consistency
304  // between PC value and MAB (MAB is +2 after sync)
305  if(id == JTAG_ID91 || id == JTAG_ID99)
306  {
307  WriteMem_430Xv2(F_WORD, 0x06, 0x3FFF);
308  WriteMem_430Xv2(F_WORD, 0x08, 0x3FFF);
309  }
310 
311  // Check if device is in Full-Emulation-State again and return status
312  IR_Shift(IR_CNTRL_SIG_CAPTURE);
313  if(DR_Shift16(0) & 0x0301)
314  {
315  return(STATUS_OK);
316  }
317 
318  return(STATUS_ERROR);
319 }
320 
321 //----------------------------------------------------------------------------
324 static void SetPC_430Xv2(unsigned long Addr)
325 {
326  unsigned short Mova;
327  unsigned short Pc_l;
328 
329  Mova = 0x0080;
330  Mova += (unsigned short)((Addr>>8) & 0x00000F00);
331  Pc_l = (unsigned short)((Addr & 0xFFFF));
332 
333  // Check Full-Emulation-State at the beginning
334  IR_Shift(IR_CNTRL_SIG_CAPTURE);
335  if(DR_Shift16(0) & 0x0301)
336  {
337  // MOVA #imm20, PC
338  ClrTCLK();
339  // take over bus control during clock LOW phase
340  IR_Shift(IR_DATA_16BIT);
341  SetTCLK();
342  DR_Shift16(Mova);
343  // insert on 24.03.2010 Florian
344  ClrTCLK();
345  // above is just for delay
346  IR_Shift(IR_CNTRL_SIG_16BIT);
347  DR_Shift16(0x1400);
348  IR_Shift(IR_DATA_16BIT);
349  ClrTCLK();
350  SetTCLK();
351  DR_Shift16(Pc_l);
352  ClrTCLK();
353  SetTCLK();
354  DR_Shift16(0x4303);
355  ClrTCLK();
356  IR_Shift(IR_ADDR_CAPTURE);
357  DR_Shift20(0x00000);
358  }
359 }
360 
361 //----------------------------------------------------------------------------
364 static unsigned long i_ReadJmbOut(void)
365 {
366  unsigned short sJMBINCTL;
367  unsigned long lJMBOUT = 0;
368  unsigned short sJMBOUT0, sJMBOUT1;
369 
370  sJMBINCTL = 0;
371 
372  IR_Shift(IR_JMB_EXCHANGE);// start exchange
373  lJMBOUT = DR_Shift16(sJMBINCTL);
374 
375  if(lJMBOUT & OUT1RDY)// check if new data available
376  {
377  sJMBINCTL |= JMB32B + OUTREQ;
378  lJMBOUT = DR_Shift16(sJMBINCTL);
379  sJMBOUT0 = (unsigned short)DR_Shift16(0);
380  sJMBOUT1 = (unsigned short)DR_Shift16(0);
381  lJMBOUT = ((unsigned long)sJMBOUT1<<16) + sJMBOUT0;
382  }
383  return lJMBOUT;
384 }
385 
386 //----------------------------------------------------------------------------
391 static short i_WriteJmbIn16(word dataX)
392 {
393  unsigned short sJMBINCTL;
394  unsigned short sJMBIN0;
395  unsigned long Timeout = 0;
396  sJMBIN0 = (unsigned short)(dataX & 0x0000FFFF);
397  sJMBINCTL = INREQ;
398 
399  IR_Shift(IR_JMB_EXCHANGE);
400  do
401  {
402  Timeout++;
403  if(Timeout >= 3000)
404  {
405  return STATUS_ERROR;
406  }
407  }
408  while(!(DR_Shift16(0x0000) & IN0RDY) && Timeout < 3000);
409  if(Timeout < 3000)
410  {
411  DR_Shift16(sJMBINCTL);
412  DR_Shift16(sJMBIN0);
413  }
414  return STATUS_OK;
415 }
416 
422 short i_WriteJmbIn32(unsigned short dataX,unsigned short dataY)
423 {
424  unsigned short sJMBINCTL;
425  unsigned short sJMBIN0,sJMBIN1;
426  unsigned long Timeout = 0;
427 
428  sJMBIN0 = (unsigned short)(dataX & 0x0000FFFF);
429  sJMBIN1 = (unsigned short)(dataY & 0x0000FFFF);
430  sJMBINCTL = JMB32B | INREQ;
431 
432  IR_Shift(IR_JMB_EXCHANGE);
433  do
434  {
435  Timeout++;
436  if(Timeout >= 3000)
437  {
438  return STATUS_ERROR;
439  }
440  }
441  while(!(DR_Shift16(0x0000) & IN0RDY) && Timeout < 3000);
442 
443  if(Timeout < 3000)
444  {
445  sJMBINCTL = 0x11;
446  DR_Shift16(sJMBINCTL) ;
447  DR_Shift16(sJMBIN0);
448  DR_Shift16(sJMBIN1);
449  }
450  return STATUS_OK;
451 }
452 
453 //----------------------------------------------------------------------------
461 word VerifyPSA_430Xv2(unsigned long StartAddr, unsigned long Length, unsigned short const *DataArray)
462 {
463  word TDOword;
464  unsigned long i;
465  const word POLY = 0x0805; // Polynom value for PSA calculation
466  word PSA_CRC = (word)(StartAddr-2); // Start value for PSA calculation
467 
468  ExecutePOR_430Xv2();
469 
470  SetPC_430Xv2(StartAddr);
471 
472  SetTCLK();
473 
474  IR_Shift(IR_CNTRL_SIG_16BIT);
475  DR_Shift16(0x0501);
476 
477  IR_Shift(IR_DATA_16BIT);
478  DR_Shift16(PSA_CRC);
479 
480  IR_Shift(IR_DATA_PSA);
481 
482  for (i = 0; i < Length; i++)
483  {
484  // Calculate the PSA (Pseudo Signature Analysis) value
485  if ((PSA_CRC & 0x8000) == 0x8000)
486  {
487  PSA_CRC ^= POLY;
488  PSA_CRC <<= 1;
489  PSA_CRC |= 0x0001;
490  }
491  else
492  {
493  PSA_CRC <<= 1;
494  }
495  // if pointer is 0 then use erase check mask, otherwise data
496  &DataArray[0] == 0 ? (PSA_CRC ^= 0xFFFF) : (PSA_CRC ^= DataArray[i]);
497 
498  ClrTCLK();
499 
500 #ifdef SPYBIWIRE_MODE
501 
502  TMSH_TDIH();
503  TMSL_TDIH();
504  TMSL_TDIH();
505  TMSH_TDIH();
506  TMSH_TDIH();
507  TMSL_TDIH();
508 
509 #else
510  // Clock through the PSA
511 
512  ClrTCK();
513 
514  SetTMS();
515  SetTCK(); // Select DR scan
516  ClrTCK();
517  ClrTMS();
518 
519  SetTCK(); // Capture DR
520  ClrTCK();
521 
522  SetTCK(); // Shift DR
523  ClrTCK();
524 
525  SetTMS();
526  SetTCK(); // Exit DR
527  ClrTCK();
528 
529  // Set JTAG FSM back into Run-Test/Idle
530  SetTCK();
531  ClrTMS();
532  ClrTCK();
533  SetTCK();
534 
535 #endif
536  SetTCLK();
537  }
538 
539  IR_Shift(IR_SHIFT_OUT_PSA);
540  TDOword = DR_Shift16(0x0000); // Read out the PSA value
541 
542  ExecutePOR_430Xv2();
543 
544  return((TDOword == PSA_CRC) ? STATUS_OK : STATUS_ERROR);
545 }
546 
547 /****************************************************************************/
548 /* High level routines for accessing the target device via JTAG: */
549 /* */
550 /* For the following section, the user is relieved from coding anything. */
551 /* To provide better understanding and clearness, some functionality is */
552 /* coded generously. (Code and speed optimization enhancements may */
553 /* be desired) */
554 /****************************************************************************/
555 
556 //----------------------------------------------------------------------------
558 static void ConnectJTAG()
559 {
560  // drive JTAG/TEST signals
561  DrvSignals();
562  MsDelay(15); // delay 15ms
563 }
564 
565 //----------------------------------------------------------------------------
568 static void EntrySequences_RstHigh_SBW()
569 {
570  ClrTST(); //1
571  MsDelay(4); // reset TEST logic
572 
573  SetRST(); //2
574 
575  SetTST(); //3
576  MsDelay(20); // activate TEST logic
577 
578  // phase 1
579  SetRST(); //4
580  usDelay(60);
581 
582  // phase 2 -> TEST pin to 0, no change on RST pin
583  // for Spy-Bi-Wire
584  _DINT();
585  ClrTST();
586 
587  // phase 3
588  usDelay(1);
589  // phase 4 -> TEST pin to 1, no change on RST pin
590  // for Spy-Bi-Wire
591  SetTST();
592  _EINT();
593  //_EINT_FET();
594  usDelay(60);
595 
596  // phase 5
597  MsDelay(5);
598 }
599 
602 static void EntrySequences_RstLow_SBW()
603 {
604  ClrTST(); //1
605  MsDelay(1); // reset TEST logic
606 
607  ClrRST(); //2
608  MsDelay(50);
609 
610  SetTST(); //3
611  MsDelay(100); // activate TEST logic
612 
613  // phase 1
614  SetRST(); //4
615  usDelay(40);
616 
617  // phase 2 -> TEST pin to 0, no change on RST pin
618  // for Spy-Bi-Wire
619  _DINT();
620  ClrTST(); //5
621 
622  usDelay(1);
623 
624  // phase 4 -> TEST pin to 1, no change on RST pin
625  // for Spy-Bi-Wire
626  SetTST(); //7
627  _EINT();
628  usDelay(40);
629  MsDelay(5);
630 }
631 
634 static void EntrySequences_RstHigh_JTAG()
635 {
636  ClrTST(); //1
637  MsDelay(4); // reset TEST logic
638 
639  SetRST(); //2
640 
641  SetTST(); //3
642  MsDelay(20); // activate TEST logic
643 
644  // phase 1
645  ClrRST(); //4
646  usDelay(60);
647 
648  // phase 2 -> TEST pin to 0, no change on RST pin
649  // for 4-wire JTAG clear Test pin
650  ClrTST(); //5
651 
652  // phase 3
653  usDelay(1);
654 
655  // phase 4 -> TEST pin to 1, no change on RST pin
656  // for 4-wire JTAG
657  SetTST();//7
658  usDelay(60);
659 
660  // phase 5
661  SetRST();
662  MsDelay(5);
663 }
664 
667 static void EntrySequences_RstLow_JTAG()
668 {
669  _DINT();
670  ClrTST(); //1
671  MsDelay(4); //reset TEST logic
672 
673  ClrRST(); //2
674  MsDelay(50);
675 
676  SetTST(); //3
677  MsDelay(50); //activate TEST logic
678 
679  ClrRST(); //4
680  usDelay(40);
681 
682  // for 4-wire JTAG clear Test pin Test(0)
683  ClrTST(); //5
684  usDelay(2);
685 
686  // for 4-wire JTAG -dry Reset(0)
687  ClrRST();
688  usDelay(2);
689 
690  // 4-wire JTAG - Test (1)
691  SetTST();
692  MsDelay(5);
693  _EINT();
694 
695  SetRST();
696 }
697 
698 //----------------------------------------------------------------------------
700 static void StopJtag (void)
701 {
702  // release JTAG/TEST signals
703  RlsSignals();
704  MsDelay(15); // delay 15ms
705 }
706 
707 //----------------------------------------------------------------------------
708 extern void configure_IO_JTAG( void );
709 //----------------------------------------------------------------------------
714 static word magicPattern(void)
715 {
716  word deviceJtagID = 0;
717 
718  // Enable the JTAG interface to the device.
719  ConnectJTAG();
720  // Apply again 4wire/SBW entry Sequence.
721  // set ResetPin = 0
722  if(INTERFACE == SPYBIWIRE_IF)
723  {
724  EntrySequences_RstLow_SBW();
725  }
726  else
727  {
728  EntrySequences_RstLow_JTAG();
729  }
730  // reset TAP state machine -> Run-Test/Idle
731  ResetTAP();
732  // feed JTAG mailbox with magic pattern
733  if(i_WriteJmbIn16(STOP_DEVICE) == STATUS_OK)
734  {
735  // Apply again 4wire/SBW entry Sequence.
736  if(INTERFACE == SPYBIWIRE_IF)
737  {
738  EntrySequences_RstHigh_SBW();
739  }
740  else
741  {
742  EntrySequences_RstHigh_JTAG();
743  }
744  ResetTAP(); // reset TAP state machine -> Run-Test/Idle
745 
746  deviceJtagID = (word)IR_Shift(IR_CNTRL_SIG_CAPTURE);
747 
748  if(deviceJtagID == JTAG_ID91)
749  {
750  // if Device is in LPM.x5 -> reset IO lock of JTAG pins and Configure it for debug
751  IR_Shift(IR_TEST_3V_REG);
752  DR_Shift16(0x4020);
753  }
754  else if(deviceJtagID == JTAG_ID99)
755  {
756  IR_Shift(IR_TEST_3V_REG);
757  DR_Shift16(0x40A0);
758  }
759  return deviceJtagID;
760  }
761  // if Device is in LPM.x5 -> reset IO lock of JTAG pins and Configure it for debug
762 #ifdef LPM5_ACTIVATED
763  {
764 #ifdef SPYBIWIREJTAG_IF // run 2 wire mode of 4 wire selection because 4wire pins are locked by JTAG lock
765 
766  ConnectJTAG();
767  StartJtagJSbw(RSTLOW_SBW);
768  jResetJtagTap();
770  jRelease();
771  MsDelay(60);
772 
773  // reset JTAG lock
775  StartJtagJSbw(RSTHIGH_SBW);
776  jResetJtagTap();
777  jsbwJtagUnlock();
778  MsDelay(60);
779 
781  EntrySequences_RstHigh_JTAG();
782  ResetTAP(); // reset TAP state machine -> Run-Test/Idle
783  MsDelay(60);
784  deviceJtagID = (word)IR_Shift(IR_CNTRL_SIG_CAPTURE);
785  if(deviceJtagID == JTAG_ID91 || deviceJtagID == JTAG_ID99)
786  {
787  return deviceJtagID;
788  }
789 #endif
790  }
791 #endif
792  return 1; // return 1 as an invalid JTAG ID
793 }
794 
795 //----------------------------------------------------------------------------
802 word UnlockDevice_430Xv2(unsigned short* password, unsigned long passwordLength)
803 {
804  unsigned short i = 0;
805  /*----------------------------------------------------------------------- */
806  /* phase 1 of device entry using a user password */
807  /*------------------------------------------------------------------------*/
808 
809  // Enable the JTAG interface to the device.
810  ConnectJTAG();
811  // Apply again 4wire/SBW entry Sequence.
812  // set ResetPin =0
813  if(INTERFACE == SPYBIWIRE_IF)
814  {
815  EntrySequences_RstLow_SBW();
816  }
817  else
818  {
819  EntrySequences_RstLow_JTAG();
820  }
821  // reset TAP state machine -> Run-Test/Idle
822  ResetTAP();
823  // shift in JTAG mailbox exchange request
824  if(i_WriteJmbIn32(STOP_DEVICE, 0x1E1E) == STATUS_ERROR)
825  {
826  return STATUS_ERROR;
827  }
828  StopJtag();
829  /*----------------------------------------------------------------------- */
830  /* phase 2 of device entry using a user password */
831  /*------------------------------------------------------------------------*/
832  // Enable the JTAG interface to the device.
833  ConnectJTAG();
834  // Apply again 4wire/SBW entry Sequence.
835  if(INTERFACE == SPYBIWIRE_IF)
836  {
837  EntrySequences_RstHigh_SBW();
838  }
839  else
840  {
841  EntrySequences_RstHigh_JTAG();
842  }
843  // reset TAP state machine -> Run-Test/Idle
844  ResetTAP();
845  // shift in JTAG mailbox exchange request
846  while(i < passwordLength)
847  {
848  if(i_WriteJmbIn16(password[i]) == STATUS_ERROR)
849  {
850  return STATUS_ERROR;
851  }
852  }
853  return(STATUS_OK);
854 }
855 
856 //----------------------------------------------------------------------------
860 static word GetCoreID (void)
861 {
862  word i;
863  word JtagId = 0; //initialize JtagId with an invalid value
864  for (i = 0; i < MAX_ENTRY_TRY; i++)
865  {
866  // release JTAG/TEST signals to safely reset the test logic
867  StopJtag();
868  // establish the physical connection to the JTAG interface
869  ConnectJTAG();
870  // Apply again 4wire/SBW entry Sequence.
871  // set ResetPin =1
872  if(INTERFACE == SPYBIWIRE_IF)
873  {
874  EntrySequences_RstHigh_SBW();
875  }
876  else
877  {
878  EntrySequences_RstHigh_JTAG();
879  }
880  // reset TAP state machine -> Run-Test/Idle
881  ResetTAP();
882  // shift out JTAG ID
883  JtagId = (word)IR_Shift(IR_CNTRL_SIG_CAPTURE);
884 
885  // break if a valid JTAG ID is being returned
886  if((JtagId == JTAG_ID91) || (JtagId == JTAG_ID99) || (JtagId == JTAG_ID98)) //****************************
887  {
888  break;
889  }
890  }
891  if(i >= MAX_ENTRY_TRY)
892  {
893  // if connected device is MSP4305438 JTAG Mailbox is not usable
894 #ifdef ACTIVATE_MAGIC_PATTERN
895  for(i = 0; i < MAX_ENTRY_TRY; i++)
896  {
897  // if no JTAG ID is returns -> apply magic pattern to stop user cd excecution
898  JtagId = magicPattern();
899 
900  if((JtagId == 1) || (i >= MAX_ENTRY_TRY))
901  {
902  // if magic pattern failed and 4 tries passed -> return status error
903  return(STATUS_ERROR);
904  }
905  else
906  {
907  break;
908  }
909  }
910  // For MSP430F5438 family mailbox is not functional in reset state.
911  // Because of this issue the magicPattern is not usable on MSP430F5438 family devices
912 #else
913  return(STATUS_ERROR);
914 #endif
915  }
916  if((JtagId == JTAG_ID91) || (JtagId == JTAG_ID99) || (JtagId == JTAG_ID98)) //****************************
917  {
918  return(STATUS_OK);
919  }
920  else
921  {
922  return(STATUS_ERROR);
923  }
924 }
925 
926 //----------------------------------------------------------------------------
931 {
932  IR_Shift(IR_COREIP_ID);
933  CoreId = DR_Shift16(0);
934  if(CoreId == 0)
935  {
936  return(STATUS_ERROR);
937  }
938  IR_Shift(IR_DEVICE_ID);
939  DeviceIdPointer = DR_Shift20(0);
940  // The ID pointer is an un-scrambled 20bit value
941  return(STATUS_OK);
942 }
943 
944 //----------------------------------------------------------------------------
948 static word SyncJtag_AssertPor (void)
949 {
950  word i = 0;
951 
952  IR_Shift(IR_CNTRL_SIG_16BIT);
953  DR_Shift16(0x1501); // Set device into JTAG mode + read
954 
955  if ((IR_Shift(IR_CNTRL_SIG_CAPTURE) != JTAG_ID91) &&
956  (IR_Shift(IR_CNTRL_SIG_CAPTURE) != JTAG_ID99) &&
957  (IR_Shift(IR_CNTRL_SIG_CAPTURE) != JTAG_ID98))
958  {
959  return(STATUS_ERROR);
960  }
961  // wait for sync
962  while(!(DR_Shift16(0) & 0x0200) && i < 50)
963  {
964  i++;
965  };
966  // continues if sync was successful
967  if(i >= 50)
968  {
969  return(STATUS_ERROR);
970  }
971  // execute a Power-On-Reset
972  if(ExecutePOR_430Xv2() != STATUS_OK)
973  {
974  return(STATUS_ERROR);
975  }
976 
977  return(STATUS_OK);
978 }
979 
980 //----------------------------------------------------------------------------
987 {
988  if(GetCoreID () != STATUS_OK)
989  {
990  return(STATUS_ERROR);
991  }
992  if (IsLockKeyProgrammed()) // Stop here if fuse is already blown
993  {
994  return(STATUS_FUSEBLOWN);
995  }
996  if (GetCoreipIdXv2()!= STATUS_OK)
997  {
998  return(STATUS_ERROR);
999  }
1000  if(SyncJtag_AssertPor() != STATUS_OK)
1001  {
1002  return(STATUS_ERROR);
1003  }
1004  // CPU is now in Full-Emulation-State
1005  // read DeviceId from memory
1006  ReadMemQuick_430Xv2(DeviceIdPointer + 4, 1, (word*)&DeviceId);
1007 
1008  return(STATUS_OK);
1009 }
1010 
1011 //----------------------------------------------------------------------------
1015 void ReleaseDevice_430Xv2(unsigned long Addr)
1016 {
1017  switch(Addr)
1018  {
1019  case V_BOR:
1020 
1021  // perform a BOR via JTAG - we loose control of the device then...
1022  IR_Shift(IR_TEST_REG);
1023  DR_Shift16(0x0200);
1024  MsDelay(5); // wait some time before doing any other action
1025  // JTAG control is lost now - GetDevice() needs to be called again to gain control.
1026  break;
1027 
1028  case V_RESET:
1029 
1030  IR_Shift(IR_CNTRL_SIG_16BIT);
1031  DR_Shift16(0x0C01); // Perform a reset
1032  DR_Shift16(0x0401);
1033  IR_Shift(IR_CNTRL_SIG_RELEASE);
1034  break;
1035 
1036  default:
1037 
1038  SetPC_430Xv2(Addr); // Set target CPU's PC
1039  // prepare release & release
1040  SetTCLK();
1041  IR_Shift(IR_CNTRL_SIG_16BIT);
1042  DR_Shift16(0x0401);
1043  IR_Shift(IR_ADDR_CAPTURE);
1044  IR_Shift(IR_CNTRL_SIG_RELEASE);
1045  }
1046 }
1047 
1048 //----------------------------------------------------------------------------
1053 void WriteMem_430Xv2(word Format, unsigned long Addr, word Data)
1054 {
1055  // Check Init State at the beginning
1056  IR_Shift(IR_CNTRL_SIG_CAPTURE);
1057  if(DR_Shift16(0) & 0x0301)
1058  {
1059  ClrTCLK();
1060  IR_Shift(IR_CNTRL_SIG_16BIT);
1061  if (Format == F_WORD)
1062  {
1063  DR_Shift16(0x0500);
1064  }
1065  else
1066  {
1067  DR_Shift16(0x0510);
1068  }
1069  IR_Shift(IR_ADDR_16BIT);
1070  DR_Shift20(Addr);
1071 
1072  SetTCLK();
1073  // New style: Only apply data during clock high phase
1074  IR_Shift(IR_DATA_TO_ADDR);
1075  DR_Shift16(Data); // Shift in 16 bits
1076  ClrTCLK();
1077  IR_Shift(IR_CNTRL_SIG_16BIT);
1078  DR_Shift16(0x0501);
1079  SetTCLK();
1080  // one or more cycle, so CPU is driving correct MAB
1081  ClrTCLK();
1082  SetTCLK();
1083  // Processor is now again in Init State
1084  }
1085 }
1086 
1087 //----------------------------------------------------------------------------
1092 void WriteMemQuick_430Xv2(unsigned long StartAddr, unsigned long Length, unsigned short const *DataArray)
1093 {
1094  unsigned long i;
1095 
1096  for (i = 0; i < Length; i++)
1097  {
1098  WriteMem_430Xv2(F_WORD, StartAddr, DataArray[i]);
1099  StartAddr += 2;
1100  }
1101 }
1102 
1103 //----------------------------------------------------------------------------
1109 short WriteFram_430Xv2(unsigned long StartAddr, unsigned long Length, unsigned short const *DataArray)
1110 {
1111  unsigned long Jmb = 0;
1112  unsigned long Timeout = 0;
1113  word loadAddr = RAM_START_ADDRESS; // RAM start address specified in config header file
1114  word startAddr = loadAddr + FramWrite_o[0]; // start address of the program in target RAM
1115 
1116  FramWrite_o[2] = (unsigned short)(StartAddr); // set write start address
1117  FramWrite_o[3] = (unsigned short)(StartAddr>>16);
1118  FramWrite_o[4] = (unsigned short)(Length); // set number of words to write
1119  FramWrite_o[5] = (unsigned short)(Length>>16);
1120 
1121  WriteMemQuick_430Xv2(loadAddr, FramWrite_o_length/2, (word*)FramWrite_o);
1122  ReleaseDevice_430Xv2(startAddr);
1123 
1124  Jmb = 0;
1125  Timeout = 0;
1126  do
1127  {
1128  Jmb = i_ReadJmbOut();
1129  Timeout++;
1130  }
1131  while(Jmb != 0xABADBABE && Timeout < 3000);
1132 
1133  if(Timeout < 3000)
1134  {
1135  unsigned long i;
1136 
1137  for(i = 0; i < Length; i++)
1138  {
1139  i_WriteJmbIn16(DataArray[i]);
1140  }
1141  }
1142  Jmb = 0;
1143  Timeout = 0;
1144 
1145  do
1146  {
1147  Jmb = i_ReadJmbOut();
1148  Timeout++;
1149  }
1150  while(Jmb != 0xCAFEBABE && Timeout < 3000);
1151 
1152  if(SyncJtag_AssertPor() != STATUS_OK)
1153  {
1154  return(STATUS_ERROR);
1155  }
1156 
1157  // clear RAM here - init with JMP $
1158  {
1159  word i;
1160 
1161  for (i = 0; i < FramWrite_o_length/2; i++)
1162  {
1163  WriteMem_430Xv2(F_WORD, loadAddr, 0x3fff);
1164  loadAddr += 2;
1165  }
1166  }
1167  return(STATUS_OK);
1168 }
1169 
1175 
1177 {
1178 #ifdef MailBoxWriteFram
1179  int sectionIndex = 0;
1180  unsigned long memTarget;
1181  unsigned short const *dataPointer;
1182 
1183  dataPointer = program->textData;
1184 
1185  for(sectionIndex=0; sectionIndex < program->noSections; sectionIndex++)
1186  {
1187  //Setup start address of section
1188  memTarget = program->startAddress[sectionIndex];
1189  if (WriteFram_430Xv2(memTarget, program->sectionLength[sectionIndex], dataPointer)!= STATUS_OK)
1190  {
1191  return(STATUS_ERROR);
1192  }
1193  dataPointer = dataPointer + program->sectionLength[sectionIndex];
1194  }
1195  // verify data after download
1196  dataPointer = program->textData;
1197  for(sectionIndex=0; sectionIndex < program->noSections; sectionIndex++)
1198  {
1199  //Setup start address of section
1200  memTarget = program->startAddress[sectionIndex];
1201  if (!VerifyMem_430Xv2(memTarget, program->sectionLength[sectionIndex], dataPointer))
1202  {
1203  return(STATUS_ERROR);
1204  }
1205  dataPointer = dataPointer + program->sectionLength[sectionIndex];
1206  }
1207  return STATUS_OK;
1208 #else
1209  int sectionIndex;
1210  unsigned long memTarget;
1211  unsigned short const *dataPointer;
1212 
1213  dataPointer = program->textData;
1214 
1215  //Loop over all sections to load
1216  for(sectionIndex=0; sectionIndex < program->noSections; sectionIndex++)
1217  {
1218  //Setup start address of section
1219  memTarget = program->startAddress[sectionIndex];
1220  WriteMemQuick_430Xv2(memTarget, program->sectionLength[sectionIndex], dataPointer);
1221  dataPointer = dataPointer + program->sectionLength[sectionIndex];
1222  }
1223  // verify data after download
1224  dataPointer = program->textData;
1225  for(sectionIndex=0; sectionIndex < program->noSections; sectionIndex++)
1226  {
1227  //Setup start address of section
1228  memTarget = program->startAddress[sectionIndex];
1229  if (!VerifyMem_430Xv2(memTarget, program->sectionLength[sectionIndex], dataPointer))
1230  {
1231  return(STATUS_ERROR);
1232  }
1233  dataPointer = dataPointer + program->sectionLength[sectionIndex];
1234  }
1235  return STATUS_OK;
1236 #endif
1237 }
1240 
1244 {
1245  //Setup program data for code download
1246  prog.textData = (unsigned short const *)&msp430Code;
1247  prog.startAddress = (unsigned long const *)&msp430Code_address;
1248  prog.sectionLength = (unsigned long const *)&msp430Code_length_of_sections;
1249  prog.noSections = msp430Code_sections;
1250  prog.start = msp430Code_start;
1251  //Download program to target device
1252  return DownloadProgram(&prog);
1253 }
1254 
1255 //----------------------------------------------------------------------------
1260 word ReadMem_430Xv2(word Format, unsigned long Addr)
1261 {
1262  word TDOword = 0;
1263  MsDelay(1);
1264  // Check Init State at the beginning
1265  IR_Shift(IR_CNTRL_SIG_CAPTURE);
1266  if(DR_Shift16(0) & 0x0301)
1267  {
1268  // Read Memory
1269  ClrTCLK();
1270  IR_Shift(IR_CNTRL_SIG_16BIT);
1271  if (Format == F_WORD)
1272  {
1273  DR_Shift16(0x0501); // Set word read
1274  }
1275  else
1276  {
1277  DR_Shift16(0x0511); // Set byte read
1278  }
1279  IR_Shift(IR_ADDR_16BIT);
1280  DR_Shift20(Addr); // Set address
1281  IR_Shift(IR_DATA_TO_ADDR);
1282  SetTCLK();
1283  ClrTCLK();
1284  TDOword = DR_Shift16(0x0000); // Shift out 16 bits
1285 
1286  SetTCLK();
1287  // one or more cycle, so CPU is driving correct MAB
1288  ClrTCLK();
1289  SetTCLK();
1290  // Processor is now again in Init State
1291  }
1292  return TDOword;
1293 }
1294 
1295 //----------------------------------------------------------------------------
1300 void ReadMemQuick_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
1301 {
1302  unsigned long i, lPc = 0;
1303 
1304  // Set PC to 'safe' address
1305  if((IR_Shift(IR_CNTRL_SIG_CAPTURE) == JTAG_ID99) || (IR_Shift(IR_CNTRL_SIG_CAPTURE) == JTAG_ID98))
1306  {
1307  lPc = 0x00000004;
1308  }
1309 
1310  SetPC_430Xv2(StartAddr);
1311  SetTCLK();
1312  IR_Shift(IR_CNTRL_SIG_16BIT);
1313  DR_Shift16(0x0501);
1314  IR_Shift(IR_ADDR_CAPTURE);
1315 
1316  IR_Shift(IR_DATA_QUICK);
1317 
1318  for (i = 0; i < Length; i++)
1319  {
1320  SetTCLK();
1321  ClrTCLK();
1322  *DataArray++ = DR_Shift16(0); // Read data from memory.
1323  }
1324 
1325  if(lPc)
1326  {
1327  SetPC_430Xv2(lPc);
1328  }
1329  SetTCLK();
1330 }
1331 
1332 //----------------------------------------------------------------------------
1340 void EraseFRAM_430Xv2(unsigned long EraseAddr, unsigned long Length)
1341 {
1342  word loadAddr = RAM_START_ADDRESS; // RAM start address specified in config header file
1343  word startAddr = loadAddr + FramErase_o[0]; // start address of the program in target RAM
1344 
1345  FramErase_o[2] = (unsigned short)(EraseAddr); // set dummy write address
1346  FramErase_o[3] = (unsigned short)(EraseAddr>>16);
1347  FramErase_o[4] = (unsigned short)(Length);
1348  FramErase_o[5] = (unsigned short)(Length>>16);
1349 
1350  WriteMemQuick_430Xv2(loadAddr, FramErase_o_length/2, (word*)FramErase_o);
1351  ReleaseDevice_430Xv2(startAddr);
1352  {
1353  unsigned long Jmb = 0;
1354  unsigned long Timeout = 0;
1355 
1356  do
1357  {
1358  Jmb = 0;
1359  Jmb = i_ReadJmbOut();
1360  Timeout++;
1361  }
1362  // original timeout: 3000
1363  while(Jmb != 0xCAFEBABE && Timeout < Length);
1364  }
1365 
1366  SyncJtag_AssertPor();
1367 
1368  // clear RAM here - init with JMP $
1369  {
1370  word i;
1371 
1372  for (i = 0; i < FramErase_o_length/2; i++)
1373  {
1374  WriteMem_430Xv2(F_WORD, loadAddr, 0x3fff);
1375  loadAddr += 2;
1376  }
1377  }
1378 }
1379 
1380 //----------------------------------------------------------------------------
1386 word EraseCheck_430Xv2(unsigned long StartAddr, unsigned long Length)
1387 {
1388  return (VerifyPSA_430Xv2(StartAddr, Length, 0));
1389 }
1390 
1391 //----------------------------------------------------------------------------
1398 word VerifyMem_430Xv2(unsigned long StartAddr, unsigned long Length, unsigned short const *DataArray)
1399 {
1400  return (VerifyPSA_430Xv2(StartAddr, Length, DataArray));
1401 }
1402 
1403 //------------------------------------------------------------------------
1406 word ProgramLockKey(void)
1407 {
1408  word LockKey[2] = { 0x5555, 0x5555 };
1409 
1410  // write JTAG lock key
1411  WriteMemQuick_430Xv2(0xff80, 2, LockKey);
1412 
1413  // now perform a BOR via JTAG - we loose control of the device then...
1414  IR_Shift(IR_TEST_REG);
1415  DR_Shift16(0x0200);
1416  MsDelay(5); // wait some time until Bootcode is executed
1417 
1418  // -> get it under JTAG control again
1419  // and return result of "is fuse blown?"
1420  return(GetDevice_430Xv2() == STATUS_FUSEBLOWN);
1421 }
1422 
1423 //------------------------------------------------------------------------
1427 {
1428  word i;
1429 
1430  for (i = 3; i > 0; i--) // First trial could be wrong
1431  {
1432  IR_Shift(IR_CNTRL_SIG_CAPTURE);
1433  if (DR_Shift16(0xAAAA) == 0x5555)
1434  {
1435  return(STATUS_OK); // Fuse is blown
1436  }
1437  }
1438  return(STATUS_ERROR); // Fuse is not blown
1439 }
1440 
1441 #define FR4xx_LOCKREGISTER 0x160
1442 
1443 //------------------------------------------------------------------------
1448 {
1449  if(IR_Shift(IR_CNTRL_SIG_CAPTURE) == JTAG_ID98)
1450  {
1451  unsigned short newRegisterVal = ReadMem_430Xv2(F_WORD, FR4xx_LOCKREGISTER);
1452  newRegisterVal &= ~0xFF03;
1453  newRegisterVal |= 0xA500;
1454  // unlock MPU for FR4xx/FR2xx
1455  WriteMem_430Xv2(F_WORD, FR4xx_LOCKREGISTER, newRegisterVal);
1456  if((ReadMem_430Xv2(F_WORD, FR4xx_LOCKREGISTER) & 0x3) == 0x0)
1457  {
1458  return STATUS_OK;
1459  }
1460  return STATUS_ERROR;
1461  }
1462  else
1463  {
1464  unsigned short MPUCTL0 =0x0000;
1465  unsigned short FramCtlKey = 0xA500;
1466 
1467  // first read out the MPU control register 0
1468  MPUCTL0 = ReadMem_430Xv2(F_WORD,0x05A0);
1469 
1470  // check MPUENA bit: if MPU is not enabled just return no error
1471  if((MPUCTL0 & 0x1)==0)
1472  {
1473  return(STATUS_OK);
1474  }
1475  // check MPULOCK bit: if MPULOCK is set write access to all MPU
1476  // registers is disabled until a POR/BOR occurs
1477  if((MPUCTL0 & 0x3)!=0x1)
1478  {
1479  // feed in magic pattern to stop code execution after BOR
1480  if( i_WriteJmbIn16(STOP_DEVICE) == STATUS_ERROR)
1481  {
1482  return(STATUS_ERROR);
1483  }
1484  // Apply BOR to reset the device
1485  SetTST();
1486  MsDelay(20);
1487  ClrTST();
1488 
1489  SetRST();
1490  MsDelay(20);
1491  ClrRST();
1492  MsDelay(20);
1493 
1494  // connect to device again, apply entry sequence
1495  ConnectJTAG();
1496 
1497  // Apply again 4wire/SBW entry Sequence.
1498  if(INTERFACE == SPYBIWIRE_IF)
1499  {
1500  EntrySequences_RstHigh_SBW();
1501  }
1502  else
1503  {
1504  EntrySequences_RstHigh_JTAG();
1505  }
1506  // reset TAP state machine -> Run-Test/Idle
1507  ResetTAP();
1508  // get jtag control back
1509  if(STATUS_ERROR == SyncJtag_AssertPor())
1510  {
1511  return(STATUS_ERROR);
1512  }
1513  }
1514  // MPU Registers are unlocked. MPU can now be disabled.
1515  // Set MPUENA = 0, write Fram MPUCTL0 key
1516  WriteMem_430Xv2(F_WORD, 0x05A0, FramCtlKey);
1517 
1518  MPUCTL0 = ReadMem_430Xv2(F_WORD,0x05A0);
1519  // now check if MPU is disabled
1520  if((MPUCTL0 & 0x1)==0)
1521  {
1522  return STATUS_OK;
1523  }
1524  return STATUS_ERROR;
1525  }
1526 }
1527 
1528 //------------------------------------------------------------------------
1531 {
1532  word sysBslAddress = 0x0182;
1533  if(IR_Shift(IR_CNTRL_SIG_CAPTURE) == JTAG_ID98)
1534  {
1535  sysBslAddress = 0x0142;
1536  }
1537  unsigned short BslCur;
1538  // Read SYSBSLC register
1539  BslCur = ReadMem_430Xv2(F_WORD, sysBslAddress);
1540  // Disable BSL area protection
1541  BslCur &= ~SYSBSLPE;
1542  // Write back SYSBSLC register
1543  WriteMem_430Xv2(F_WORD, sysBslAddress, BslCur);
1544 }
1545 
1552 word EraseFRAMViaBootCode_430Xv2(word mailBoxMode, word data1, word data2)
1553 {
1554  short mailBoxError = 0;
1555  // restart device
1556  ClrTST();
1557  ClrRST();
1558  MsDelay(200);
1559 
1560  if(INTERFACE == SPYBIWIRE_IF)
1561  {
1562  EntrySequences_RstLow_SBW();
1563  }
1564  else
1565  {
1566  EntrySequences_RstLow_JTAG();
1567  }
1568 
1569  ResetTAP();
1570 
1571  if(mailBoxMode == MAIL_BOX_32BIT)// 32Bit Mode
1572  {
1573  mailBoxError = i_WriteJmbIn32(data1,data2);
1574  }
1575  else // 16 Bit Mode
1576  {
1577  mailBoxError = i_WriteJmbIn16(data1);
1578  }
1579  // restart device
1580  ClrTST();
1581  SetRST();
1582  MsDelay(200);
1583 
1584  if(INTERFACE == SPYBIWIRE_IF)
1585  {
1586  EntrySequences_RstHigh_SBW();
1587  }
1588  else
1589  {
1590  EntrySequences_RstHigh_JTAG();
1591  }
1592  ResetTAP();
1593  // wait until erase is done
1594  MsDelay(60);
1595 
1596  if(SyncJtag_AssertPor() != STATUS_OK)
1597  {
1598  return(STATUS_ERROR);
1599  }
1600 
1601  // check if mailbox input was ok
1602  if(mailBoxError == STATUS_ERROR)
1603  {
1604  return(STATUS_ERROR);
1605  }
1606  return STATUS_OK;
1607 }
1608 
1609 /****************************************************************************/
1610 /* END OF SOURCE FILE */
1611 /****************************************************************************/
word VerifyMem_430Xv2(unsigned long StartAddr, unsigned long Length, unsigned short const *DataArray)
This function performs a Verification over the given memory range.
#define V_RESET
Triggers a regular reset on device release from JTAG control.
short DownloadMsp430Code()
Download a program to target.
unsigned short FramWrite_o[]
Holds the target code for an FRAM write operation.
Definition: FramWrite.c:56
const unsigned long * startAddress
Array of start addresses of the sections.
void usDelay(word microseconds)
Delay function (resolution is ~1 us)
word DisableMpu_430Xv2(void)
This function disables the Memory Protection Unit (FRAM devices only)
word VerifyPSA_430Xv2(unsigned long StartAddr, unsigned long Length, unsigned short const *DataArray)
This function compares the computed PSA (Pseudo Signature Analysis) value to the PSA value shifted ou...
#define IN0RDY
JTAG mailbox constant -.
#define ClrTST()
SBW macro: clear TEST pin signal.
#define IR_CNTRL_SIG_CAPTURE
Read out the JTAG control signal register.
Definition: JTAGfunc430FR.h:98
void ReadMemQuick_430Xv2(unsigned long StartAddr, unsigned long Length, word *DataArray)
This function reads an array of words from the memory.
short DownloadProgram(struct_Program *program)
DownloadFile Load program data int memory sections.
#define IR_DATA_PSA
Switch JTAG data register to PSA mode.
#define IR_ADDR_16BIT
Set the MSP430 MAB to a specific 16-bit value.
#define JTAG_ID91
JTAG identification value for 430Xv2 architecture devices.
word IsLockKeyProgrammed(void)
This function checks if the JTAG lock key is programmed.
#define IR_DATA_16BIT
Set the MSP430 MDB to a specific 16-bit value with the next 16-bit data access.
#define SetTCLK()
SBW macro: set TCLK signal.
void EraseFRAM_430Xv2(unsigned long EraseAddr, unsigned long Length)
This function performs an erase of a user defined FRAM memory section. For FRAM devices the erase equ...
Funclet for FRAM write operations on FR2xx/FR4xx family devices.
#define JTAG_ID98
JTAG identification value for 430Xv2 architecture FR4XX/FR2xx devices.
void WriteMem_430Xv2(word Format, unsigned long Addr, word Data)
This function writes one byte/word at a given address ( <0xA00)
#define IR_CNTRL_SIG_16BIT
Set the JTAG control signal register.
Definition: JTAGfunc430FR.h:96
unsigned long AllShifts(word Format, unsigned long Data)
Shift a value into TDI (MSB first) and simultaneously shift out a value from TDO (MSB first)...
word ProgramLockKey(void)
This function blows the security fuse.
word UnlockDevice_430Xv2(unsigned short *password, unsigned long passwordLength)
This function unlocks the Fram memory when a JTAG password is set.
const unsigned long * sectionLength
Array of length information of the sections.
#define IR_DEVICE_ID
Instruction to determine device's DeviceID.
#define IR_ADDR_CAPTURE
Read out the MAB data on the next 16/20-bit data access.
#define SetTST()
SBW macro: set TEST pin signal.
Funclet for FRAM erase operations.
short WriteFram_430Xv2(unsigned long StartAddr, unsigned long Length, unsigned short const *DataArray)
This function programs/verifies an array of words into the Fram memory.
void configure_IO_JTAG(void)
Set JTAG pins to output direction - from REP430F to target.
word ReadMem_430Xv2(word Format, unsigned long Addr)
This function reads one byte/word from a given address in memory.
byte tdo_bit
Holds the value of TDO-bit.
#define SBWDATO
JTAG data_out pin in SBW mode -separate pin in MSP430F5437 - common IO translator.
word EraseFRAMViaBootCode_430Xv2(word mailBoxMode, word data1, word data2)
This function performs a Erase of FRxx devices using the JTAG mailbox.
#define MAX_ENTRY_TRY
Maximum number of tries for the determination of the core identification info.
Definition: Config430FR.h:125
#define MAIL_BOX_32BIT
JTAG mailbox mode 32 bit -.
word GetCoreipIdXv2()
Function to determine & compare core identification info (Xv2)
unsigned short FramErase_o[]
Holds the target code for an FRAM erase operation.
Definition: FramErase.c:56
#define IR_COREIP_ID
Instruction to determine device's CoreIP.
#define IR_JMB_EXCHANGE
Request a JTAG mailbox exchange.
#define OUTREQ
JTAG mailbox constant -.
#define IR_DATA_QUICK
Set the MSP430 MDB to a specific 16-bit value (RAM only)
#define STATUS_FUSEBLOWN
GetDevice returns this if the security fuse is blown.
void jResetJtagTap(void)
Reset target JTAG interface and perform fuse-HW check.
Definition: JSBW.c:154
void jsbwJtagUnlock(void)
Function for resetting the JTAG lock via JSBW.
Definition: JSBW.c:283
const unsigned short * textData
Array executable code and data sections.
#define SetTCK()
JTAG macro: set TCK signal.
#define V_BOR
Triggers a "brown-out" reset on device release from JTAG control.
Funclet for FRAM erase operations on FR2xx/FR4xx family devices.
unsigned long noSections
Number of sections.
#define ClrRST()
SBW macro: clear RST signal.
#define SetTMS()
JTAG macro: set TMS signal.
#define IR_SHIFT_OUT_PSA
Shift out the PSA pattern generated by IR_DATA_PSA.
short i_WriteJmbIn32(unsigned short dataX, unsigned short dataY)
Write a 32bit value into the JTAG mailbox system. The function timeouts if the mailbox is not empty a...
#define STATUS_OK
return 1 = no error
#define ClrTCLK()
SBW macro: clear TCLK signal.
word GetDevice_430Xv2(void)
Function to take target device under JTAG control. Disables the target watchdog. Sets the global DEVI...
void WriteMemQuick_430Xv2(unsigned long StartAddr, unsigned long Length, unsigned short const *DataArray)
This function writes an array of words into the target memory.
void StartJtagJSbw(byte states)
Start JTAG communication in JSBW mode.
Definition: JSBW.c:79
#define INREQ
JTAG mailbox constant -.
void MsDelay(word milliseconds)
Delay function (resolution is 1 ms)
void ReleaseDevice_430Xv2(unsigned long Addr)
Function to release the target device from JTAG control.
void jRelease(void)
Releases the JSBW logic.
Definition: JSBW.c:65
struct_Program prog
Executable code and meta data about downloaded program.
#define STATUS_ERROR
return 0 = error
#define IR_CNTRL_SIG_RELEASE
Release the CPU from JTAG control.
void JsbwMagicPattern(void)
Function for applying the magic pattern via JSBW.
Definition: JSBW.c:271
#define IR_TEST_3V_REG
Instruction for 3 volt test register in 5xx.
#define RAM_START_ADDRESS
Set the start address of the device RAM.
Definition: Config430FR.h:83
#define ClrTCK()
JTAG macro: clear TCK signal.
#define INTERFACE
Select the interface to be used to communicate with the device.
Definition: Config430FR.h:64
#define OUT1RDY
JTAG mailbox constant -.
#define SetTDI()
JTAG macro: set TDI signal.
void RlsSignals(void)
Release I/O pins.
Low Level function prototypes, macros, and pin-to-signal assignments regarding to user's hardware...
#define IR_TEST_REG
Instruction for test register in 5xx.
#define IR_DATA_TO_ADDR
Set the MSP430 MDB with a specific 16-bit value and write it to the memory address which is currently...
#define SPYBIWIRE_IF
Spy-Bi-Wire interface.
#define JTAG_ID99
JTAG identification value for 430Xv2 architecture FR59XX devices.
byte TCLK_saved
Holds the last value of TCLK before entering a JTAG sequence.
void UnlockBsl_430Xv2FRAM(void)
This function unlocks the BSL memory protection.
unsigned long start
Execution start address.
#define JMB32B
JTAG mailbox constant -.
#define SetRST()
SBW macro: set RST signal.
Funclet for FRAM write operations.
word EraseCheck_430Xv2(unsigned long StartAddr, unsigned long Length)
This function performs an Erase Check over the given memory range.
JTAG Function Prototypes and Definitions.
void DrvSignals(void)
Set up I/O pins for JTAG communication.
#define ClrTMS()
JTAG macro: clear TMS signal.

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