Instance: AON_WUC
Component: AON_WUC
Base address: 0x40091000
This component control the Wakeup controller residing in the AON domain.
Note: This module is only supporting 32 bit ReadWrite access from MCU
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4009 1000 |
|
RW |
32 |
0x0000 0001 |
0x0000 0004 |
0x4009 1004 |
|
RW |
32 |
0x0000 000F |
0x0000 0008 |
0x4009 1008 |
|
RW |
32 |
0x0000 0001 |
0x0000 000C |
0x4009 100C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x4009 1010 |
|
RW |
32 |
0x0380 0000 |
0x0000 0014 |
0x4009 1014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4009 1018 |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4009 1020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4009 1024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x4009 1030 |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x4009 1034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4009 1038 |
|
RW |
32 |
0x0000 0100 |
0x0000 0040 |
0x4009 1040 |
|
RW |
32 |
0x0B99 A02F |
0x0000 0044 |
0x4009 1044 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4009 1000 |
Instance |
AON_WUC |
Description |
MCU Clock Management |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||
2 |
RCOSC_HF_CAL_DONE |
MCU bootcode will set this bit when RCOSC_HF is calibrated. The FLASH can not be used until this bit is set. |
RW |
0 |
|||||||||||||||||
1:0 |
PWR_DWN_SRC |
Controls the clock source for the entire MCU domain while MCU is requesting powerdown.
|
RW |
0x0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4009 1004 |
Instance |
AON_WUC |
Description |
AUX Clock Management |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||
31:13 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
|||||||||||||||||||||||||||||||||||||
12:11 |
PWR_DWN_SRC |
When AUX requests powerdown with SCLK_HF as source, then WUC will switch over to this clock source during powerdown, and automatically switch back to SCLK_HF when AUX system is back in active mode
|
RW |
0x0 |
|||||||||||||||||||||||||||||||||||||
10:8 |
SCLK_HF_DIV |
Select the AUX clock divider for SCLK_HF
|
RW |
0x0 |
|||||||||||||||||||||||||||||||||||||
7:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
|||||||||||||||||||||||||||||||||||||
2:0 |
SRC |
Selects the clock source for AUX:
|
RW |
0x1 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4009 1008 |
Instance |
AON_WUC |
Description |
MCU Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||
31:18 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
|||||||||||||||||||||||||
17 |
VIRT_OFF |
Controls action taken when receiving a request to power-off MCU domain: |
RW |
0 |
|||||||||||||||||||||||||
16 |
FIXED_WU_EN |
Controls timing of MCU wakeup: |
RW |
0 |
|||||||||||||||||||||||||
15:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 |
|||||||||||||||||||||||||
3:0 |
SRAM_RET_EN |
MCU SRAM is partitioned into 4 banks . This register controls which of the banks that has retention during MCU power off
|
RW |
0xF |
Address offset |
0x0000 000C |
||
Physical address |
0x4009 100C |
Instance |
AON_WUC |
Description |
AUX Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:18 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
17 |
VIRT_OFF |
Controls action taken when receiving a request to power AUX domain off: |
RW |
0 |
||
16 |
FIXED_WU_EN |
Controls timing of AUX wakeup: |
RW |
0 |
||
15:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
0 |
RAM_RET_EN |
This bit controls retention mode for the AUX_RAM:BANK0: |
RW |
1 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4009 1010 |
Instance |
AON_WUC |
Description |
AUX Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
RESET_REQ |
Reset request for AUX. Writing 1 to this register will assert reset to AUX. The reset will be held until the bit is cleared again. |
RW |
0 |
||
30:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
2 |
SCE_RUN_EN |
Enables (1) or disables (0) AUX_SCE execution. AUX_SCE execution will begin when AUX Domain is powered and either this or AUX_SCE:CTL.CLK_EN is set. |
RW |
0 |
||
1 |
SWEV |
Writing 1 sets the software event to the AUX domain, which can be read through AUX_WUC:WUEVFLAGS.AON_SW. |
RW |
0 |
||
0 |
AUX_FORCE_ON |
Forces the AUX domain into active mode, overriding the requests from AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL. |
RW |
0 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4009 1014 |
Instance |
AON_WUC |
Description |
Power Status Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:30 |
SW |
General purpose Read/Write register that can be read through the test subsystem tap. This register is dedicated for the Power Profiler tool. |
RW |
0x0 |
||
29:26 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
25 |
VDDS_OK |
Observation of VDDS_BOD_OK signal from VDDS brown out detection circuit |
RO |
1 |
||
24 |
VDDR_OK |
Observation of VDDR_OK from VDDR brown out detection circuit |
RO |
1 |
||
23 |
VDD_OK |
Observation of VDD_BOD_OK signal from VDD brown out detection circuit |
RO |
1 |
||
22 |
OSC_GBIAS |
Indicates OSC GBIAS state: |
RO |
0 |
||
21 |
AUX_GBIAS |
Indicates AUX GBIAS state: |
RO |
0 |
||
20 |
MCU_GBIAS |
Indicates MCU GBIAS state: |
RO |
0 |
||
19 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
||
18 |
OSC_BGAP |
Indicates OSC BGAP state: |
RO |
0 |
||
17 |
AUX_BGAP |
Indicates AUX BGAP state: |
RO |
0 |
||
16 |
MCU_BGAP |
Indicates MCU BGAP state: |
RO |
0 |
||
15 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
||
14 |
GBIAS_ON99 |
Indicates GBIAS state: |
RO |
0 |
||
13 |
GBIAS_ON |
Indicates GBIAS state: |
RO |
0 |
||
12 |
BGAP_ON |
Indicates BGAP state: |
RO |
0 |
||
11:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
9 |
AUX_PWR_DWN |
Indicates the AUX powerdown state when AUX domain is powered up. |
RO |
0 |
||
8 |
MCU_PWR_DWN |
Indicates the MCU powerdown state when MCU is powered up. |
RO |
0 |
||
7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
||
6 |
JTAG_PD_ON |
Indicates JTAG power state: |
RO |
0 |
||
5 |
AUX_PD_ON |
Indicates AUX power state: |
RO |
0 |
||
4 |
MCU_PD_ON |
Indicates MCU power state: |
RO |
0 |
||
3 |
AUX_BUS_RESET_DONE |
Indicates Reset Done from AUX Bus: |
RO |
0 |
||
2 |
AUX_BUS_CONNECTED |
Indicates that AUX Bus is connected: |
RO |
0 |
||
1 |
AUX_RESET_DONE |
Indicates Reset Done from AUX: |
RO |
0 |
||
0 |
PWR_DWN |
Indicates state of power supply: |
RO |
0 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4009 1018 |
Instance |
AON_WUC |
Description |
Shutdown Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
JTAG_OVR |
This register is ignored. Shutdown requests can be overridden directly from WUC_TAP |
RW |
0 |
||
0 |
EN |
Writing a 1 to this bit forces a shutdown request to be registered and all I/O values to be latched - in the PAD ring, possibly enabling I/O wakeup. Writing 0 will cancel a registered shutdown request and open th I/O latches residing in the PAD ring. |
RW |
0 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4009 1020 |
Instance |
AON_WUC |
Description |
General Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
8 |
PWR_DWN_DIS |
Controls whether MCU and AUX requesting to be powered off will enable a transition to powerdown: |
RW |
0 |
||
7:4 |
FIXED_WU_PER |
Select a wakeup period for AUX and MCU wakeup. Wakeup time will take at least the number of SCLK_LF cycles specified in this register, when enabed by MCUCFG.FIXED_WU_EN and/or AUXCFG.FIXED_WU_EN |
RW |
0x0 |
||
3 |
Reserved |
Internal field controlled by TI provided startup code |
WO |
0 |
||
2 |
Reserved |
WO |
0 |
|||
1 |
Reserved |
RO |
0 |
|||
0 |
Reserved |
RO |
0 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4009 1024 |
Instance |
AON_WUC |
Description |
General Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
23:16 |
TAP_SECURITY_CTL |
Readback of security ctrl word of WUC_TAP |
RO |
0x00 |
||
15:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
9 |
Reserved |
RW |
0 |
|||
8 |
CHIP_ERASE |
Request set by WUC_TAP to request ROM FW to perform a Chip erase |
RW |
0 |
||
7:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
1 |
MCU_RESET_SRC |
Indicates source of last MCU Voltage Domain warm reset request: |
RW |
0 |
||
0 |
MCU_WARM_RESET |
Indicates type of last MCU Voltage Domain reset: |
RW |
0 |
Address offset |
0x0000 0030 |
||
Physical address |
0x4009 1030 |
Instance |
AON_WUC |
Description |
Recharge Controller Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
ADAPTIVE_EN |
Enable adaptive recharge |
RW |
0 |
||
30:24 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
23:20 |
C2 |
Gain factor for adaptive recharge algorithm |
RW |
0x0 |
||
19:16 |
C1 |
Gain factor for adaptive recharge algorithm |
RW |
0x0 |
||
15:11 |
MAX_PER_M |
This register defines the maximum period that the recharge algorithm can take, i.e. it defines the maximum number of cycles between 2 recharges. |
RW |
0x00 |
||
10:8 |
MAX_PER_E |
This register defines the maximum period that the recharge algorithm can take, i.e. it defines the maximum number of cycles between 2 recharges. |
RW |
0x0 |
||
7:3 |
PER_M |
Number of 32 KHz clocks between activation of recharge controller |
RW |
0x00 |
||
2:0 |
PER_E |
Number of 32 KHz clocks between activation of recharge controller |
RW |
0x0 |
Address offset |
0x0000 0034 |
||
Physical address |
0x4009 1034 |
Instance |
AON_WUC |
Description |
Recharge Controller Status |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:20 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 |
||
19:16 |
VDDR_SMPLS |
The last 4 VDDR samples, bit 0 being the newest. |
RO |
0x0 |
||
15:0 |
MAX_USED_PER |
The maximum value of recharge period seen with VDDR>threshold. |
RW |
0x0000 |
Address offset |
0x0000 0038 |
||
Physical address |
0x4009 1038 |
Instance |
AON_WUC |
Description |
Oscillator Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:3 |
PER_M |
Number of 32 KHz clocks between oscillator amplitude calibrations. |
RW |
0x00 |
||
2:0 |
PER_E |
Number of 32 KHz clocks between oscillator amplitude calibrations. |
RW |
0x0 |
Address offset |
0x0000 0040 |
||
Physical address |
0x4009 1040 |
Instance |
AON_WUC |
Description |
JTAG Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
8 |
JTAG_PD_FORCE_ON |
Controls JTAG PowerDomain power state: |
RW |
1 |
||
7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
||
6 |
PBIST2_TAP |
Internal field controlled by TI provided startup code |
RW |
0 |
||
5 |
PBIST1_TAP |
Internal field controlled by TI provided startup code |
RW |
0 |
||
4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
||
3 |
TEST_TAP |
Internal field controlled by TI provided startup code |
RW |
0 |
||
2 |
WUC_TAP |
Internal field controlled by TI provided startup code |
RW |
0 |
||
1 |
PRCM_TAP |
Internal field controlled by TI provided startup code |
RW |
0 |
||
0 |
CPU_DAP |
Internal field controlled by TI provided startup code |
RW |
0 |
Address offset |
0x0000 0044 |
||
Physical address |
0x4009 1044 |
Instance |
AON_WUC |
Description |
JTAG USERCODE |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
USER_CODE |
Internal field controlled by TI provided startup code |
RW |
0x0B99 A02F |
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