Abbreviation/Signal |
Type |
Description |
Short |
Anti Aliasing Filter |
|
Short |
Reference clock from OSC_TOP to AUX. Source is selectable. This clock signal can be used as an event in AUX |
|
Short |
Audio Data line 0 |
|
Short |
Audio Data line 1 |
|
Short |
Audio Data line 2 |
|
Short |
Analog to Digital Converter |
|
Short |
ADC reference voltage |
|
Short |
DMA trigger from the ADC, triggering DMA channel #7 |
|
Short |
ADC conversion done event available in AUX |
|
Short |
Event in AUX signaling that there is only room for one more sample in the ADC FIFO |
|
Short |
Event from ADC/ADC_FIFO to MCU domain. For details see user guide |
|
Module |
Analog to Digital Interface |
|
Module |
Automatic Gain Control |
|
Short |
AMBA High-speed Bus |
|
Short |
Audio Inter Face |
|
Short |
Module controlling pins assigned to AUX |
|
Short |
Module controlling pins assigned to AUX |
|
Short |
Amplitude Compensation |
|
Short |
Voltage domain that is Always On |
|
Module |
Always on Event routing |
|
Module |
Always ON IOC |
|
Short |
Wake up event from AON to AUX. Up to three programmable sources OR'ed together to generate this event |
|
Module |
Always ON Real Time Clock |
|
Short |
Event from the AON_RTC channel 2 |
|
Module |
Always on part of SPI Slave module |
|
Short |
SW triggered event from AON to AUX |
|
Module |
Always ON WakeUp Control |
|
Short |
Advanced RISC Machines, Company |
|
Signal |
Trace data bus for in ATB interface port 1. Connects to ETM when ETM is present. Connects to ITM when ETM does not exist. |
|
Signal |
Trace data bus for in ATB interface port 2. Connects to ITM when ETM is present. Tied-off when ETM does not exist. |
|
Short |
Analog Test |
|
Short |
Analog test signal/bus |
|
Short |
Analog test signal/bus |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Module |
Auxiliary |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Analog/Digital General Purpose Input Output pin that can be mapped to AUX. For details see IOC |
|
Short |
Module controlling pins assigned to AUX |
|
Short |
Module controlling pins assigned to AUX |
|
Short |
Combined event from AUX to MCU domain. See user guide for details |
|
Short |
Comparator A. Analog peripheral of AUX. In AUX this can also refer to the event coming from this comparator |
|
Short |
Comparator B. Analog peripheral of AUX. In AUX this can also refer to the event coming from this comparator |
|
Short |
Auxiliary Sensor Domain Controller |
|
Short |
Special register in CPU used to prevent activation of exceptions based on their priority level |
|
Short |
Bulk Acoustic Wave |
|
Signal |
Internal Signal |
|
Short |
Bit clock for the WCLK and serial audio data signals. This signal is an input when using an external clock source and output when using the internal clock source. |
|
Short |
Bus Fault Status Register |
|
Short |
Bandgap |
|
Short |
CPU instruction, BreaKPoinT |
|
Short |
Interconnect or power domain including interconnect |
|
Short |
BandWidth |
|
Short |
CPU instruction, Branch and eXchange instruction set |
|
Short |
Capture Compare PWL |
|
Module |
Power domain that contains clock management for MCU system |
|
Short |
||
Signal |
Internal Signal |
|
Module |
Comparator A. |
|
Module |
Comparator B |
|
Signal |
Internal Signal |
|
Short |
Special register in CPU used to control selector for main stack/process stack and selector for privileged/unpriviledged modes |
|
Short |
Cycles Per Instruction |
|
Short |
Central processing unit or power domain including system CPU |
|
Short |
Cyclical Redundancy Check algorithm |
|
Module |
Encryption engine |
|
Short |
Clear To Send, primary input to UART module from Ios |
|
Short |
Digital to Analog Converter |
|
Signal |
DAC Reference |
|
Short |
Debug Access Port |
|
Module |
DCDC regulator for regulating VDDR |
|
Module |
Didital to Digital Interface |
|
Short |
DeepSleep Mode for CPU |
|
Short |
Digital IO |
|
Short |
Direct Memory Access |
|
Module |
Frequency doubling sub-module |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Short |
Single Phase Audio Interface Format |
|
Short |
||
Short |
Execution PSR |
|
Short |
Enhanced Trace Macrocell |
|
Module |
Event Fabric |
|
Signal |
A pre-defined value saved to LR on exception entry. This value indicates the required return stack and processor mode when returning from the exception |
|
Short |
Special register in CPU used to prevent activation of all exceptions except NMI |
|
Short |
Feed-Forward cell 1 gain. This is one of the loop filter gm-cells which adjusts the noise shaping characteristics. |
|
Short |
Feed-Forward cell 2 gain. This is one of the loop filter gm-cells which adjusts the noise shaping characteristics. |
|
Short |
Feed-Forward cell 3 gain. This is one of the loop filter gm-cells which adjusts the noise shaping characteristics. |
|
Short |
First In First Output |
|
Signal |
Internal Signal |
|
Module |
FLASH |
|
Module |
Flash Memory Controller |
|
Short |
||
Short |
Finite State Machine |
|
Short |
Serial Frame signal for SSI interface |
|
Short |
Firmware |
|
Short |
Global Bias |
|
Module |
||
Module |
General Purpose Input/Output |
|
Short |
General Purpose RAM |
|
Module |
General Purpose Timer |
|
Module |
GPT module 0 |
|
Module |
GPT module 1 |
|
Module |
GPT module 2 |
|
Module |
GPT module 3 |
|
Short |
High Frequency |
|
Signal |
State |
|
Short |
High Performance / High Power |
|
Short |
High Performance/Power Mode |
|
Signal |
State |
|
Signal |
State |
|
Signal |
State |
|
Short |
Hardware |
|
Module |
Inter-Integrated Circuit, a multimaster serial single-ended computer bus |
|
Module |
Inter-IC Sound, our audio interface |
|
Short |
Bias Current |
|
Signal |
State |
|
Signal |
State |
|
Short |
IDentification number |
|
Short |
||
Signal |
State |
|
Signal |
State |
|
Module |
Intermediate Frequency Analog to Digital Converter |
|
Module |
Intermediate Frequency AMPlifier |
|
Short |
Input/Output |
|
Module |
Input / Output Configurator |
|
Short |
Interrupt PSR |
|
Short |
Current Proportional to Absolute Temperature |
|
Short |
Constant current REFerence (REF) |
|
Short |
Interrupt Service Routine |
|
Short |
Current source |
|
Signal |
This signal clamps the output of the current source. The signal can also be used as an event in AUX |
|
Short |
CPU instruction, IF-THEN |
|
Short |
Instrumentation Trace Macrocell |
|
Short |
Joint Test Action Group. The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG. |
|
Short |
CPU instruction, Load Multiple |
|
Short |
Low Drop-Out voltage regulator |
|
Short |
CPU instruction, Load Register |
|
Short |
CPU instruction, Doubleword Load Register |
|
Short |
Linear Feedback Shift Register |
|
Short |
Dual Phased Left Justified Audio Interface Format |
|
Short |
Low-Noise Amplifier |
|
Short |
Low Power |
|
Short |
Low Power Buffer |
|
Short |
Low Power Mode |
|
Signal |
Internal Signal |
|
Signal |
State |
|
Short |
Link Register 12 from Cortex M Processor |
|
Short |
Least Significant Bit |
|
Short |
Load Store Unit |
|
Short |
High-speed master clock used for sample conversion in the external audio device. This signal is not unused when using an external clock source. |
|
Short |
Microcontroller Unit |
|
Short |
Undivided MCU system clock |
|
Short |
Power doamin that is always powered when MCU voltage domain is powered |
|
Module |
Always on interface module |
|
Short |
Event from MCU domain to AUX. Source is configurable in event fabric |
|
Short |
Memory Manage Fault Status Register |
|
Short |
Memory Protection Unit |
|
Short |
CPU instruction, Move the contents of a special register to a general-purpose register |
|
Short |
Most Significant Bit |
|
Short |
Main Stack Pointer |
|
Module |
Submodule generating nA bias currents |
|
Short |
Non-Maskable Interrupt |
|
Short |
N-channel MOS transistor |
|
Short |
Nominal value |
|
Short |
Non-Return-to-Zero |
|
Short |
Non Return-to-Zero |
|
Short |
Nested Vectored Interrupt Controller |
|
Short |
In AUX this refers to bit 0 of the signals that can be routed from the observability mux to AUX |
|
Short |
In AUX this refers to bit 1 of the signals that can be routed from the observability mux to AUX |
|
Short |
In AUX this refers to bit 2 of the signals that can be routed from the observability mux to AUX |
|
Short |
In AUX this refers to bit 3 of the signals that can be routed from the observability mux to AUX |
|
Short |
Oscillator (see also ANAOSC) |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Module |
Oscillators Digital control |
|
Module |
Oscillator System Top level. One of the main blocks in top level analog. |
|
Module |
Power Amplifier |
|
Short |
Program Counter |
|
Short |
Power domain including peripheral modules |
|
Short |
Phase Locked Loop |
|
Short |
P-channel MOS transistor |
|
Short |
CPU instruction, Pop register(s) off the stack |
|
Short |
Psueudo Random Bit Sequence number 2, delayed |
|
Short |
Psuedo Random Bit Sequence 2, delayed. Can be used for generation of dither noise to remove tones, or it can be output on the IFADC data outputs to check the integrity of the digital output path from the ADC. |
|
Module |
Power Reset Clock Manager |
|
Short |
Special register in CPU used to prevent activation of all exceptions with configurable priority |
|
Short |
Process Stack Pointer |
|
Short |
Program Status Register |
|
Short |
Pulse Width Modulation |
|
Short |
XTAL oscillator input node |
|
Short |
XTAL oscillator output node |
|
Short |
General-purpose Register 0 from Cortex M Processor |
|
Short |
General-purpose Register 1 from Cortex M Processor |
|
Short |
General-purpose Register 10 from Cortex M Processor |
|
Short |
General-purpose Register 11 from Cortex M Processor |
|
Short |
General-purpose Register 12 from Cortex M Processor |
|
Short |
General-purpose Register 2 from Cortex M Processor |
|
Short |
General-purpose Register 3 from Cortex M Processor |
|
Short |
General-purpose Register 4 from Cortex M Processor |
|
Short |
General-purpose Register 5 from Cortex M Processor |
|
Short |
General-purpose Register 6 from Cortex M Processor |
|
Short |
General-purpose Register 7 from Cortex M Processor |
|
Short |
General-purpose Register 8 from Cortex M Processor |
|
Short |
General-purpose Register 9 from Cortex M Processor |
|
Short |
||
Short |
Digital Control for RADC |
|
Short |
Resistor Capacitor |
|
Short |
RC Oscillator |
|
Short |
See rcosc_hf |
|
Short |
High Frequency RC Oscillator |
|
Signal |
Internal Signal |
|
Short |
Low Frequency RC Oscillator |
|
Signal |
Internal Signal |
|
Short |
Reference System. Module generating refernce voltages and reference currents for use in analog blocks. |
|
Module |
Radio Frequency |
|
Module |
RF Core |
|
Module |
||
Signal |
RF Negative net |
|
Signal |
RF Positive net |
|
Module |
||
Short |
Dual Phased Right Justified Audio Interface Format |
|
Short |
Read Only Memory |
|
Short |
Real Time Clock |
|
Short |
4 kHz signal coming from the RTC counter. Can be used by timers in AUX |
|
Short |
Event that goes high every time the RTC channel 2 generates an event |
|
Signal |
16 KHz signal used to synchronize the radio timer to RTC |
|
Short |
Real-Time Operating System |
|
Short |
Request To Send, primary output from UART module to Ios |
|
Short |
Return-to-Zero |
|
Short |
Receive |
|
Short |
||
Short |
||
Short |
Successive Approximation Register (used for Binary Search) |
|
Short |
||
short |
Serial CLock, I2C clock line |
|
Short |
System Clock High Frequency |
|
Short |
System Clock Low Frequency |
|
Short |
System Clock Medium Frequency |
|
Signal |
||
Signal |
||
Short |
CPU instruction, Signed Divide |
|
Signal |
||
Short |
Power domain including serial modules |
|
Short |
CPU instruction, Send Event |
|
Short |
Lowest possible powermode, where all but the VDDS domain is powered off |
|
Module |
Synth LDO |
|
Short |
Serial Modem Interface |
|
Short |
A semaphore has been released to c3po using the AUTOTAKE feature in AUX_SMPH module |
|
Short |
Not a good term... |
|
Short |
Not a good term... |
|
Short |
Stack Pointer |
|
Short |
Serial Peripheral Interface |
|
Module |
Serial Peripheral Interface Slave |
|
Short |
Static Random Access Memory |
|
Short |
Synchronous Serial Interface |
|
Module |
Instance 0 of SSI Module |
|
Module |
Instance 1 of SSI Module |
|
Short |
CPU instruction, Store Multiple |
|
Short |
CPU instruction, Doubleword Store Register |
|
Short |
CPU instruction, Supervisor Call |
|
Short |
Software |
|
Short |
SW triggered event 0 from AUX to AON. Triggered by writes to AUX_EVCTL:SWEVSET |
|
Short |
SW triggered event 1 from AUX to AON. Triggered by writes to AUX_EVCTL:SWEVSET |
|
Short |
SW triggered event 2 from AUX to AON. Triggered by writes to AUX_EVCTL:SWEVSET |
|
Short |
Serial Wire Output |
|
Signal |
Serial Wire Viewer Debug Signal from CPU Module |
|
Short |
CPU system bus |
|
Short |
Test Access Port |
|
Signal |
JTAG compliant pin (test clock) |
|
Short |
Time to Digital Converter |
|
Short |
Time to Digital Conversion done. Event available in AUX |
|
Signal |
Time to digital prescaler output. Can be used as an event in the TDC |
|
Short |
Test Data In for JTAG interface |
|
Short |
Test Data Out for JTAG interface |
|
Short |
Texas Instruments |
|
Short |
Event from timer0 in AUX. Event triggered when timer count >= target value |
|
Short |
Event from timer1 in AUX. Event triggered when timer count >= target value |
|
Short |
Trace Port Analyzer |
|
Short |
||
Signal |
Trace Clock Signal From CPU Module |
|
Signal |
Trace Data Bus signal From CPU Module |
|
Module |
True Random Number Generator |
|
Short |
Transmit |
|
Short |
||
Short |
Temperature Compensated Crysal Oscillator, alternalive to simple XTAL |
|
Short |
Universal Asynchronous Receiver/Transmitter |
|
Module |
Instance 0 of UART Module |
|
Short |
Receive input, Primary input to UART module from Ios |
|
Short |
Transmit output, Primary output from UART module to Ios |
|
Short |
CPU instruction, Unsigned Divide |
|
Module |
Micro DMA |
|
Short |
Usage Fault Status Register |
|
Short |
Voltage to Current |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Short |
Votage Controlled Oscillator |
|
Module |
||
Signal |
Internal Signal |
|
Signal |
Regulated supply voltage for digital domain. |
|
Signal |
Positive supply voltage |
|
Signal |
Regulated (1.7V?) supply voltage. |
|
Signal |
Signal indicating that VDDR Supply voltage is good |
|
Signal |
Main supply voltage (battery). |
|
Signal |
Supply pin for IO cells on segment 2 |
|
Signal |
Supply pin for IO cells on segment 3 |
|
Signal |
Signal indicating that VDDS Supply voltage is good |
|
Signal |
Signal indicating that VDD Supply voltage is good |
|
Signal |
Internal Signal |
|
Short |
Power domain including Flash memory |
|
Short |
Voltage Max |
|
Short |
Voltage Min |
|
Signal |
Voltage Reference |
|
Short |
Wireless Audio Streaming Protocol |
|
Short |
Sample framing signal/clock that defines the sample frequency and the word boundaries in the serial data stream. The WCLK frequency is identical to the sample frequency. This signal is an input when using an external clock source and output when using the internal clock source. |
|
Module |
Watch Dog Timer |
|
Short |
CPU instruction, Wait For Event |
|
Short |
CPU instruction, Wait For Interrupt |
|
Module |
Wakeup Interrupt Controller |
|
Module |
Wake Up Controller |
|
Short |
Wake Up Controller Test Access Port |
|
Short |
Pin on device dedicated to 48MHz xtal/oscillator |
|
Short |
eXecute Never |
|
Short |
Xrystal Oscillator |
|
Short |
See xosc_hf |
|
Short |
High Frequency Xrystal Oscillator |
|
Short |
Low Frequency Xrystal Oscillator |
|
Short |
Program Status Register |
|
Short |
Crystall |
|
Signal |
Same as ACLK_REF |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Short |
Parts Per Million |
|
Signal |
RC-oscillator High Frequency module or the clock signal outputted by this module |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
RC-oscillator Low Frequency module or the clock signal outputted by this module |
|
Signal |
Internal Signal |
|
Signal |
System Clock High Frequency |
|
Signal |
System Clock, Low Frequency |
|
Signal |
Internal Signal |
|
Short |
See uDIG |
|
Short |
||
Module |
Micropower Low Drop-out Voltage Regulator |
|
Signal |
XOSC High frequency module or the clock signal outputted by this module |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
XOSC Low frequency module or the clock signal outputted by this module |
|
Signal |
Internal Signal |
|
Signal |
Internal Signal |
|
Signal |
See xosc_lf |