AUX_SCE

Instance: AUX_SCE
Component: AUX_SCE
Base address: 0x400e1000

 

AUX Sensor Control Engine Control Module

 

TOP:AUX_SCE Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CTL

RW

32

0x0000 0000

0x0000 0000

0x400E 1000

FETCHSTAT

RO

32

0x0000 0000

0x0000 0004

0x400E 1004

CPUSTAT

RO

32

0x0000 0000

0x0000 0008

0x400E 1008

WUSTAT

RO

32

0x0000 0000

0x0000 000C

0x400E 100C

REG1_0

RO

32

0x0000 0000

0x0000 0010

0x400E 1010

REG3_2

RO

32

0x0000 0000

0x0000 0014

0x400E 1014

REG5_4

RO

32

0x0000 0000

0x0000 0018

0x400E 1018

REG7_6

RO

32

0x0000 0000

0x0000 001C

0x400E 101C

LOOPADDR

RO

32

0x0000 0000

0x0000 0020

0x400E 1020

LOOPCNT

RO

32

0x0000 0000

0x0000 0024

0x400E 1024

TOP:AUX_SCE Register Descriptions

TOP:AUX_SCE:CTL

Address offset

0x0000 0000

Physical address

0x400E 1000

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

FORCE_EV_LOW

Internal

RW

0x00

23:16

FORCE_EV_HIGH

Internal

RW

0x00

15:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

11:8

RESET_VECTOR

Internal

RW

0x0

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

6

DBG_FREEZE_EN

Internal

WO

0

5

FORCE_WU_LOW

Internal

RW

0

4

FORCE_WU_HIGH

Internal

RW

0

3

RESTART

Internal

RW

0

2

SINGLE_STEP

Internal

RW

0

1

SUSPEND

Internal

RW

0

0

CLK_EN

Internal

RW

0



TOP:AUX_SCE:FETCHSTAT

Address offset

0x0000 0004

Physical address

0x400E 1004

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

OPCODE

Internal

RO

0x0000

15:0

PC

Internal

RO

0x0000



TOP:AUX_SCE:CPUSTAT

Address offset

0x0000 0008

Physical address

0x400E 1008

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

11

BUS_ERROR

Internal

RO

0

10

SLEEP

Internal

RO

0

9

WEV

Internal

RO

0

8

SELF_STOP

Internal

RO

0

7:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

3

V_FLAG

Internal

RO

0

2

C_FLAG

Internal

RO

0

1

N_FLAG

Internal

RO

0

0

Z_FLAG

Internal

RO

0



TOP:AUX_SCE:WUSTAT

Address offset

0x0000 000C

Physical address

0x400E 100C

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

19:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

17:16

EXC_VECTOR

Internal

RO

0x0

15:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

8

WU_SIGNAL

Internal

RO

0

7:0

EV_SIGNALS

Internal

RO

0x00



TOP:AUX_SCE:REG1_0

Address offset

0x0000 0010

Physical address

0x400E 1010

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

REG1

Internal

RO

0x0000

15:0

REG0

Internal

RO

0x0000



TOP:AUX_SCE:REG3_2

Address offset

0x0000 0014

Physical address

0x400E 1014

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

REG3

Internal

RO

0x0000

15:0

REG2

Internal

RO

0x0000



TOP:AUX_SCE:REG5_4

Address offset

0x0000 0018

Physical address

0x400E 1018

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

REG5

Internal

RO

0x0000

15:0

REG4

Internal

RO

0x0000



TOP:AUX_SCE:REG7_6

Address offset

0x0000 001C

Physical address

0x400E 101C

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

REG7

Internal

RO

0x0000

15:0

REG6

Internal

RO

0x0000



TOP:AUX_SCE:LOOPADDR

Address offset

0x0000 0020

Physical address

0x400E 1020

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

STOP

Internal

RO

0x0000

15:0

START

Internal

RO

0x0000



TOP:AUX_SCE:LOOPCNT

Address offset

0x0000 0024

Physical address

0x400E 1024

Instance

AUX_SCE

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

ITER_LEFT

Internal

RO

0x00