Instance: ADI_0_RF
Component: ADI_0_RF
Base address: 0x0
ADI for LNA, IFAMP, PA, IFADC modules.
Registers Fields should be considered static unless otherwise noted (as dynamic)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
8 |
0x0000 0000 |
0x0000 0000 |
0x0000 0000 |
|
RW |
8 |
0x0000 0000 |
0x0000 0001 |
0x0000 0001 |
|
RW |
8 |
0x0000 0000 |
0x0000 0002 |
0x0000 0002 |
|
RW |
8 |
0x0000 0000 |
0x0000 0003 |
0x0000 0003 |
|
RW |
8 |
0x0000 0000 |
0x0000 0004 |
0x0000 0004 |
|
RW |
8 |
0x0000 0000 |
0x0000 0005 |
0x0000 0005 |
|
RW |
8 |
0x0000 0000 |
0x0000 0006 |
0x0000 0006 |
|
RW |
8 |
0x0000 0000 |
0x0000 0007 |
0x0000 0007 |
|
RW |
8 |
0x0000 0000 |
0x0000 0008 |
0x0000 0008 |
|
RW |
8 |
0x0000 0000 |
0x0000 0009 |
0x0000 0009 |
|
RW |
8 |
0x0000 0000 |
0x0000 000A |
0x0000 000A |
|
RW |
8 |
0x0000 0000 |
0x0000 000B |
0x0000 000B |
|
RW |
8 |
0x0000 0000 |
0x0000 000C |
0x0000 000C |
|
RW |
8 |
0x0000 0000 |
0x0000 000D |
0x0000 000D |
|
RW |
8 |
0x0000 0000 |
0x0000 000E |
0x0000 000E |
|
RW |
8 |
0x0000 0000 |
0x0000 000F |
0x0000 000F |
|
RW |
8 |
0x0000 0000 |
0x0000 0010 |
0x0000 0010 |
|
RW |
8 |
0x0000 0000 |
0x0000 0012 |
0x0000 0012 |
|
RW |
8 |
0x0000 0000 |
0x0000 0013 |
0x0000 0013 |
|
RW |
8 |
0x0000 0000 |
0x0000 0018 |
0x0000 0018 |
|
RW |
8 |
0x0000 0000 |
0x0000 0019 |
0x0000 0019 |
|
RW |
8 |
0x0000 0000 |
0x0000 001A |
0x0000 001A |
|
RW |
8 |
0x0000 0000 |
0x0000 001B |
0x0000 001B |
|
RW |
8 |
0x0000 0000 |
0x0000 001C |
0x0000 001C |
|
RW |
8 |
0x0000 0000 |
0x0000 001D |
0x0000 001D |
|
RW |
8 |
0x0000 0000 |
0x0000 001E |
0x0000 001E |
|
RO |
8 |
0x0000 0000 |
0x0000 001F |
0x0000 001F |
Address offset |
0x0000 0000 |
||
Physical address |
0x0000 0000 |
Instance |
ADI_0_RF |
Description |
LNA and Antenna Diversity Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||
7:4 |
MIX_AD |
Antenna diversity control in mixers.
|
RW |
0x0 |
|||||||||||||||||
3:2 |
LNA_AD |
Antenna diversity control.
|
RW |
0x0 |
|||||||||||||||||
1 |
BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
|||||||||||||||||
0 |
EN |
LNA enable signal.
|
RW |
0 |
Address offset |
0x0000 0001 |
||
Physical address |
0x0000 0001 |
Instance |
ADI_0_RF |
Description |
LNA Gain and Input Device Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||
7:6 |
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
|||||||||||||||||||||||||
5:4 |
DEV_CTL |
LNA input device control. |
RW |
0x0 |
|||||||||||||||||||||||||
3:0 |
GAIN |
LNA gain control. Thermometer encoded.
|
RW |
0x0 |
Address offset |
0x0000 0002 |
||
Physical address |
0x0000 0002 |
Instance |
ADI_0_RF |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:6 |
RXTX_PIN |
Control of RXTX pin. TheRXTXpin is used when LNA uses external bias. See LNACTL2.EXT_BIAS. |
RW |
0x0 |
||
5 |
RESERVED5 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
4 |
EXT_BIAS |
LNA bias method |
RW |
0 |
||
3:0 |
IB |
LNA bias current control. Linear steps. Will be trimmed in production test. |
RW |
0x0 |
Address offset |
0x0000 0003 |
||
Physical address |
0x0000 0003 |
Instance |
ADI_0_RF |
Description |
IFAMP Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7:3 |
TRIM |
Trim bits for IFAMP gain. The trim circuit consist of a binary weighted resistor ladder which gives a non-linear gain versus bit value curve. |
RW |
0x00 |
|||||||||||||
2 |
BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
|||||||||||||
1 |
EN_Q |
Q-channel IFAMP enable signal
|
RW |
0 |
|||||||||||||
0 |
EN_I |
I-channel IFAMP enable signal
|
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x0000 0004 |
Instance |
ADI_0_RF |
Description |
IFAMP Gain Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||
7:6 |
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
|||||||||||||||||||||||||||||||||
5:0 |
GAIN |
IFAMP gain control. Thermometer encoded.
|
RW |
0x00 |
Address offset |
0x0000 0005 |
||
Physical address |
0x0000 0005 |
Instance |
ADI_0_RF |
Description |
IFAMP Output Attenuation Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||
7:3 |
RESERVED3 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
|||||||||||||||||||||||||||||||||||||
2:0 |
ATTN |
IFAMP output attenuation control in 3 dB steps
|
0x0 |
Address offset |
0x0000 0006 |
||
Physical address |
0x0000 0006 |
Instance |
ADI_0_RF |
Description |
PA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7:3 |
TRIM |
Trim of bias current to get constant output power over process and temperature. Will be trimmed in production test. |
RW |
0x00 |
|||||||||||||
2 |
PEAKDET_EN |
PA peakdetect circuit enable signal.
|
RW |
0 |
|||||||||||||
1 |
BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
|||||||||||||
0 |
EN |
PA enable signal.
|
RW |
0 |
Address offset |
0x0000 0007 |
||
Physical address |
0x0000 0007 |
Instance |
ADI_0_RF |
Description |
PA Gain and Power Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:6 |
GAIN |
Gain control in PA 1st stage. |
RW |
0x0 |
||
5:0 |
IB |
PA output power control |
RW |
0x00 |
Address offset |
0x0000 0008 |
||
Physical address |
0x0000 0008 |
Instance |
ADI_0_RF |
Description |
PA Antenna Diversity Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:5 |
RXTX |
Control of RFP and RFN when used to control external range extender device. (ie. If RFP is used as a single ended RF input, RFN is available to be used as a control output) |
RW |
0x0 |
||
4:3 |
CM |
Debug / experimental registers. Do not use! |
RW |
0x0 |
||
2:0 |
AD |
When PACTL0.EN = 1: |
RW |
0x0 |
Address offset |
0x0000 0009 |
||
Physical address |
0x0000 0009 |
Instance |
ADI_0_RF |
Description |
RFLDO Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7:6 |
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
|||||||||||||
5 |
ATEST_I_EN |
Enable test current (2% of pass device current) to ATEST. |
RW |
0 |
|||||||||||||
4 |
ATEST_V_EN |
Enables regulated output voltage to ATEST. |
RW |
0 |
|||||||||||||
3 |
BYPASS_REG_EN |
Bypass LDO and short VDDR to PA, LNA and Mixer. RFLDO0.EN must be 0b1 to use this mode. |
RW |
0 |
|||||||||||||
2 |
RDY_EN |
Enables generation of the LDO ready signal. Read result from STAT.RF_LDO. RFLDO0.EN must be 0b1 in order to use this feature.
|
RW |
0 |
|||||||||||||
1 |
BIAS_DIS |
Disable dummy bias current.
|
RW |
0 |
|||||||||||||
0 |
EN |
Enable signal for RFLDO. Powers PA, LNA and Mixer
|
RW |
0 |
Address offset |
0x0000 000A |
||
Physical address |
0x0000 000A |
Instance |
ADI_0_RF |
Description |
RFLDO Output Trim |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7 |
RESERVED7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
6:0 |
TRIM_OUT |
Trims output voltage in steps of approximately 5mV linear steps. |
RW |
0x00 |
Address offset |
0x0000 000B |
||
Physical address |
0x0000 000B |
Instance |
ADI_0_RF |
Description |
RFLDO Compensation Trim |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:6 |
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
5:3 |
COMP_RES |
Trim compensation resistor in series with Miller cap in nonlinear steps. Default should be 0x1. Unsigned number. |
RW |
0x0 |
||
2:0 |
COMP_CAP |
Trim compensation Miller cap in linear steps of 0.5 pF. Default should be 0x6. Unsigned number. |
RW |
0x0 |
Address offset |
0x0000 000C |
||
Physical address |
0x0000 000C |
Instance |
ADI_0_RF |
Description |
Intermediate Frequency ADC Trim and Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7:4 |
INT2ADJ |
Adjust integrator 2 gain, given by gm/C. The list below indicates the resulting gm while C is fixed (~235fF). Note MSB signifies high power (1) vs. Low power (0) mode. |
RW |
0x0 |
|||||||||||||
3:2 |
AAFCAP |
Adjust AAF damping |
RW |
0x0 |
|||||||||||||
1 |
BIAS_DIS |
Disable dummy bias current.
|
RW |
0 |
|||||||||||||
0 |
Reserved |
RW |
0 |
Address offset |
0x0000 000D |
||
Physical address |
0x0000 000D |
Instance |
ADI_0_RF |
Description |
Intermediate Frequency ADC Trim and Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:4 |
FF1ADJ |
Adjust FF1 gain (transconductance/gm from first integrator into quantizer), note MSB signifies high power (1) vs. Low power (0) mode. |
RW |
0x0 |
||
3:0 |
INT3ADJ |
Adjust integrator 3 gain, see |
RW |
0x0 |
Address offset |
0x0000 000E |
||
Physical address |
0x0000 000E |
Instance |
ADI_0_RF |
Description |
Intermediate Frequency ADC Trim and Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:4 |
FF3ADJ |
Adjust FF3 gain (transconductance/gm from third integrator into quantizer). See IFADCLFCFG0.FF1ADJ for values. Default value is 0x4 |
RW |
0x0 |
||
3:0 |
FF2ADJ |
Adjust FF2 gain (transconductance/gm from second integrator into quantizer). See IFADCLFCFG0.FF1ADJ for values. Default value is 0x3 |
RW |
0x0 |
Address offset |
0x0000 000F |
||
Physical address |
0x0000 000F |
Instance |
ADI_0_RF |
Description |
Intermediate Frequency ADC Ttrim and Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7 |
MODE |
Selects DAC return to zero mode
|
RW |
0 |
|||||||||||||
6:1 |
TRIM |
Trim feedback-DAC current in uA. Increasing this current will give a more aggressive noise shaping but it also reduce the gain into the IFADC. |
RW |
0x00 |
|||||||||||||
0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
Address offset |
0x0000 0010 |
||
Physical address |
0x0000 0010 |
Instance |
ADI_0_RF |
Description |
IFADC Quantizer Trim and Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:6 |
Reserved |
Internal |
RW |
0x0 |
||
5:4 |
Reserved |
Internal |
RW |
0x0 |
||
3 |
AUTOCAL_EN |
Quantizer auto calibrate enable. |
RW |
0 |
||
2:0 |
TH |
Threshold adjust for quantizer. NOM is ~25mV. |
RW |
0x0 |
Address offset |
0x0000 0012 |
||
Physical address |
0x0000 0012 |
Instance |
ADI_0_RF |
Description |
Intermediate Frequency ADC Trim and Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
7:5 |
DITHERTRIM |
Adjust dither output current |
RW |
0x0 |
|||||||||||||||||||||
4 |
ADCIEN |
Enable I-channel IFADC
|
RW |
0 |
|||||||||||||||||||||
3 |
ADCQEN |
Enable Q-channel IFADC
|
RW |
0 |
|||||||||||||||||||||
2:1 |
DITHEREN |
Dither algorithm select.
|
RW |
0x0 |
|||||||||||||||||||||
0 |
Reserved |
RW |
0 |
Address offset |
0x0000 0013 |
||
Physical address |
0x0000 0013 |
Instance |
ADI_0_RF |
Description |
Intermediate Frequency ADC Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7 |
RESETN |
Reset all digital blocks (active low).
|
RW |
0 |
|||||||||||||
6 |
CLKGENEN |
Enable clock generator module
|
RW |
0 |
|||||||||||||
5 |
ADCDIGCLKEN |
Enable clock output from IFADC to decimator
|
RW |
0 |
|||||||||||||
4 |
Reserved |
Internal |
RW |
0 |
|||||||||||||
3:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
|||||||||||||
1 |
INVCLKOUT |
Control phase inversion of IFADC clock output
|
RW |
0 |
|||||||||||||
0 |
Reserved |
RW |
0 |
Address offset |
0x0000 0018 |
||
Physical address |
0x0000 0018 |
Instance |
ADI_0_RF |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7:5 |
RESERVED5 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
|||||||||||||
4 |
ERR_AMP_ZERO_EN |
Enables a zero in the LDO error amplifier's output to improve stability at the cost of bandwidth.
|
RW |
0 |
|||||||||||||
3 |
BYPASS_REG_EN |
Bypass LDO and short VDDR on LDO output to IFADC. |
RW |
0 |
|||||||||||||
2 |
RDY_EN |
Enable LDO Ready Signal. Read result in STAT.IFLDOS_RDY.
|
RW |
0 |
|||||||||||||
1 |
BIAS_DIS |
Disable dummy bias current.
|
RW |
0 |
|||||||||||||
0 |
EN |
Enable IFADC's regulator for analog blocks.
|
RW |
0 |
Address offset |
0x0000 0019 |
||
Physical address |
0x0000 0019 |
Instance |
ADI_0_RF |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:5 |
COMP_CAP |
Trim compensation Miller cap in linear steps of 0.5 pF. Default should be 0x6. Unsigned. Tradeoff stability for speed. |
RW |
0x0 |
||
4:0 |
TRIM_OUT |
Trim LDO's output voltage linearly with a signed 2's complement number. Step size is approximately 8 mV. |
RW |
0x00 |
Address offset |
0x0000 001A |
||
Physical address |
0x0000 001A |
Instance |
ADI_0_RF |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:5 |
RESERVED5 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
4 |
ATEST_V_EN |
Enables regulated output voltage to ATEST. Used to trim the LDO. |
RW |
0 |
||
3 |
ATEST_I_EN |
Enable test current (8.33% or 1/12 of LDO load current) to ATEST. |
RW |
0 |
||
2:0 |
COMP_RES |
Trim compensation resistor in series with Miller cap in nonlinear steps. Default should be 0x0. Unsigned number. |
RW |
0x0 |
Address offset |
0x0000 001B |
||
Physical address |
0x0000 001B |
Instance |
ADI_0_RF |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7:4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
|||||||||||||
3 |
BYPASS_REG_EN |
Bypass LDO and short VDDR to LDO's output to ADC.
|
RW |
0 |
|||||||||||||
2 |
RDY_EN |
Enable LDO Ready Signal. Read result in STAT.IFLDOS_RDY.
|
RW |
0 |
|||||||||||||
1 |
BIAS_DIS |
Disable dummy bias current.
|
RW |
0 |
|||||||||||||
0 |
EN |
Enable IFADC LDO for digital blocks.
|
RW |
0 |
Address offset |
0x0000 001C |
||
Physical address |
0x0000 001C |
Instance |
ADI_0_RF |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:5 |
COMP_CAP |
Trim compensation Miller cap in linear steps of 0.5 pF. Default should be 0x6. Unsigned. |
RW |
0x0 |
||
4:0 |
TRIM_OUT |
Trim LDO's output voltage linearly with a signed 2's complement number. Step size is approximately 8 mV. |
RW |
0x00 |
Address offset |
0x0000 001D |
||
Physical address |
0x0000 001D |
Instance |
ADI_0_RF |
Description |
IFADC Digital **Supply LDO** |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7:5 |
RESERVED5 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
|||||||||||||
4 |
ATEST_V_EN |
Enables regulated output voltage to ATEST. Used to trim the LDO.
|
RW |
0 |
|||||||||||||
3 |
ATEST_I_EN |
Enable test current (10% of LDO load current) to ATEST.
|
RW |
0 |
|||||||||||||
2:0 |
COMP_RES |
Trim compensation resistor in series with Miller cap in nonlinear steps. Default should be 0x0. Unsigned number. |
RW |
0x0 |
Address offset |
0x0000 001E |
||
Physical address |
0x0000 001E |
Instance |
ADI_0_RF |
Description |
IFAMP Bias Current Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7 |
RESERVED7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
6:4 |
AAF_CAP_EN |
AAF capacitor control. Linear cap steps (ie. Non-linear BW steps) |
RW |
0x0 |
||
3:0 |
IB |
IFAMP bias current control. Linear steps. |
RW |
0x0 |
Address offset |
0x0000 001F |
||
Physical address |
0x0000 001F |
Instance |
ADI_0_RF |
Description |
Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:3 |
IFADC_CALVAL_OUT |
Quant Cal values from either I or Q quantizer |
RO |
0x00 |
||
2 |
IFADC_CALDONE |
IFADC quantizer calibration done |
RO |
0 |
||
1 |
IFLDOS_RDY |
IFADC LDOs Ready (if only one is enabled the bit indicate the status of the enabled LDO) |
RO |
0 |
||
0 |
RF_LDO |
RO |
0 |
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