Instance: PRCM
Component: PRCM
Base address: 0x40082000
Power, Reset and Clock Management
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4008 2000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4008 2004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4008 2008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4008 200C |
|
RW |
32 |
0x0000 0002 |
0x0000 0028 |
0x4008 2028 |
|
RW |
32 |
0x0000 0001 |
0x0000 002C |
0x4008 202C |
|
RW |
32 |
0x0000 0003 |
0x0000 0030 |
0x4008 2030 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x4008 203C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x4008 2040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4008 2044 |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x4008 2048 |
|
RW |
32 |
0x0000 0000 |
0x0000 004C |
0x4008 204C |
|
RW |
32 |
0x0000 0000 |
0x0000 0050 |
0x4008 2050 |
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0x4008 2054 |
|
RW |
32 |
0x0000 0000 |
0x0000 0058 |
0x4008 2058 |
|
RW |
32 |
0x0000 0000 |
0x0000 005C |
0x4008 205C |
|
RW |
32 |
0x0000 0000 |
0x0000 0060 |
0x4008 2060 |
|
RW |
32 |
0x0000 0000 |
0x0000 0064 |
0x4008 2064 |
|
RW |
32 |
0x0000 0000 |
0x0000 0068 |
0x4008 2068 |
|
RW |
32 |
0x0000 0000 |
0x0000 006C |
0x4008 206C |
|
RW |
32 |
0x0000 0000 |
0x0000 0070 |
0x4008 2070 |
|
RW |
32 |
0x0000 0000 |
0x0000 0074 |
0x4008 2074 |
|
RW |
32 |
0x0000 0000 |
0x0000 0078 |
0x4008 2078 |
|
RW |
32 |
0x0000 0000 |
0x0000 007C |
0x4008 207C |
|
RW |
32 |
0x0000 0000 |
0x0000 0080 |
0x4008 2080 |
|
RW |
32 |
0x0000 0000 |
0x0000 0084 |
0x4008 2084 |
|
RW |
32 |
0x0000 0000 |
0x0000 0088 |
0x4008 2088 |
|
RW |
32 |
0x0000 0000 |
0x0000 008C |
0x4008 208C |
|
RW |
32 |
0x0000 0000 |
0x0000 00B4 |
0x4008 20B4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00B8 |
0x4008 20B8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00BC |
0x4008 20BC |
|
RW |
32 |
0x0000 0000 |
0x0000 00C4 |
0x4008 20C4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00C8 |
0x4008 20C8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00CC |
0x4008 20CC |
|
RW |
32 |
0x0000 0000 |
0x0000 00D0 |
0x4008 20D0 |
|
RW |
32 |
0x0000 0000 |
0x0000 00D4 |
0x4008 20D4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00D8 |
0x4008 20D8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00DC |
0x4008 20DC |
|
RW |
32 |
0x0000 0000 |
0x0000 00F0 |
0x4008 20F0 |
|
RW |
32 |
0x0000 0000 |
0x0000 00F4 |
0x4008 20F4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00F8 |
0x4008 20F8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00FC |
0x4008 20FC |
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0x4008 2100 |
|
RW |
32 |
0x0000 0000 |
0x0000 0104 |
0x4008 2104 |
|
RW |
32 |
0x0000 0000 |
0x0000 0108 |
0x4008 2108 |
|
RW |
32 |
0x0000 0000 |
0x0000 010C |
0x4008 210C |
|
RW |
32 |
0x0000 0000 |
0x0000 0110 |
0x4008 2110 |
|
RW |
32 |
0x0000 0000 |
0x0000 012C |
0x4008 212C |
|
RW |
32 |
0x0000 0000 |
0x0000 0130 |
0x4008 2130 |
|
RW |
32 |
0x0000 0000 |
0x0000 0134 |
0x4008 2134 |
|
RW |
32 |
0x0000 0000 |
0x0000 0138 |
0x4008 2138 |
|
RO |
32 |
0x0000 0000 |
0x0000 0140 |
0x4008 2140 |
|
RO |
32 |
0x0000 0000 |
0x0000 0144 |
0x4008 2144 |
|
RO |
32 |
0x0000 0000 |
0x0000 0148 |
0x4008 2148 |
|
RO |
32 |
0x0000 0000 |
0x0000 014C |
0x4008 214C |
|
RW |
32 |
0x0000 000A |
0x0000 017C |
0x4008 217C |
|
RW |
32 |
0x0000 0001 |
0x0000 0184 |
0x4008 2184 |
|
RW |
32 |
0x0000 0000 |
0x0000 0188 |
0x4008 2188 |
|
RW |
32 |
0x0000 0001 |
0x0000 018C |
0x4008 218C |
|
RO |
32 |
0x0000 001A |
0x0000 0194 |
0x4008 2194 |
|
RO |
32 |
0x0000 0001 |
0x0000 0198 |
0x4008 2198 |
|
RO |
32 |
0x0000 0000 |
0x0000 019C |
0x4008 219C |
|
RO |
32 |
0x0000 0001 |
0x0000 01A0 |
0x4008 21A0 |
|
RO |
32 |
0x0000 0001 |
0x0000 01A4 |
0x4008 21A4 |
|
RW |
32 |
0x0000 0000 |
0x0000 01D0 |
0x4008 21D0 |
|
RW |
32 |
0x0000 0003 |
0x0000 0224 |
0x4008 2224 |
|
RW |
32 |
0x0000 00E7 |
0x0000 022C |
0x4008 222C |
|
RW |
32 |
0x0000 0003 |
0x0000 0250 |
0x4008 2250 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4008 2000 |
Instance |
PRCM |
Description |
Infrastructure Clock Division Factor For Run Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||
1:0 |
RATIO |
Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode. Division ratio affects both infrastructure clock and perbusull clock.
|
RW |
0x0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4008 2004 |
Instance |
PRCM |
Description |
Infrastructure Clock Division Factor For Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||
1:0 |
RATIO |
Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode. Division ratio affects both infrastructure clock and perbusull clock.
|
RW |
0x0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4008 2008 |
Instance |
PRCM |
Description |
Infrastructure Clock Division Factor For DeepSleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||
1:0 |
RATIO |
Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode. Division ratio affects both infrastructure clock and perbusull clock.
|
RW |
0x0 |
Address offset |
0x0000 000C |
||
Physical address |
0x4008 200C |
Instance |
PRCM |
Description |
MCU Voltage Domain Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
2 |
MCU_VD |
Request WUC to power down the MCU voltage domain |
RW |
0 |
||
1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
0 |
ULDO |
Request WUC to switch to uLDO. |
RW |
0 |
Address offset |
0x0000 0028 |
||
Physical address |
0x4008 2028 |
Instance |
PRCM |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
LOAD_DONE |
Status of LOAD. |
RO |
1 |
||
0 |
LOAD |
|
WO |
0 |
Address offset |
0x0000 002C |
||
Physical address |
0x4008 202C |
Instance |
PRCM |
Description |
RFC Clock Gate |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
CLK_EN |
|
RW |
1 |
Address offset |
0x0000 0030 |
||
Physical address |
0x4008 2030 |
Instance |
PRCM |
Description |
VIMS Clock Gate |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1:0 |
CLK_EN |
00: Disable clock |
RW |
0x3 |
Address offset |
0x0000 003C |
||
Physical address |
0x4008 203C |
Instance |
PRCM |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
8 |
DMA_CLK_EN |
|
RW |
0 |
||
7:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
1 |
TRNG_CLK_EN |
|
RW |
0 |
||
0 |
CRYPTO_CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0040 |
||
Physical address |
0x4008 2040 |
Instance |
PRCM |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
8 |
DMA_CLK_EN |
|
RW |
0 |
||
7:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
1 |
TRNG_CLK_EN |
|
RW |
0 |
||
0 |
CRYPTO_CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0044 |
||
Physical address |
0x4008 2044 |
Instance |
PRCM |
Description |
SEC (TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
8 |
DMA_CLK_EN |
|
RW |
0 |
||
7:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
1 |
TRNG_CLK_EN |
|
RW |
0 |
||
0 |
CRYPTO_CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0048 |
||
Physical address |
0x4008 2048 |
Instance |
PRCM |
Description |
GPIO Clock Gate For Run Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 004C |
||
Physical address |
0x4008 204C |
Instance |
PRCM |
Description |
GPIO Clock Gate For Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0050 |
||
Physical address |
0x4008 2050 |
Instance |
PRCM |
Description |
GPIO Clock Gate For Deep Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0054 |
||
Physical address |
0x4008 2054 |
Instance |
PRCM |
Description |
GPT Clock Gate For Run Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||
3:0 |
CLK_EN |
Each bit below has the following meaning:
|
RW |
0x0 |
Address offset |
0x0000 0058 |
||
Physical address |
0x4008 2058 |
Instance |
PRCM |
Description |
GPT Clock Gate For Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||
3:0 |
CLK_EN |
Each bit below has the following meaning:
|
RW |
0x0 |
Address offset |
0x0000 005C |
||
Physical address |
0x4008 205C |
Instance |
PRCM |
Description |
GPT Clock Gate For Deep Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||
3:0 |
CLK_EN |
Each bit below has the following meaning:
|
RW |
0x0 |
Address offset |
0x0000 0060 |
||
Physical address |
0x4008 2060 |
Instance |
PRCM |
Description |
I2C Clock Gate For Run Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0064 |
||
Physical address |
0x4008 2064 |
Instance |
PRCM |
Description |
I2C Clock Gate For Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0068 |
||
Physical address |
0x4008 2068 |
Instance |
PRCM |
Description |
I2C Clock Gate For Deep Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 006C |
||
Physical address |
0x4008 206C |
Instance |
PRCM |
Description |
UART Clock Gate For Run Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0070 |
||
Physical address |
0x4008 2070 |
Instance |
PRCM |
Description |
UART Clock Gate For Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0074 |
||
Physical address |
0x4008 2074 |
Instance |
PRCM |
Description |
UART Clock Gate For Deep Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0078 |
||
Physical address |
0x4008 2078 |
Instance |
PRCM |
Description |
SSI Clock Gate For Run Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||
1:0 |
CLK_EN |
|
RW |
0x0 |
Address offset |
0x0000 007C |
||
Physical address |
0x4008 207C |
Instance |
PRCM |
Description |
SSI Clock Gate For Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||
1:0 |
CLK_EN |
|
RW |
0x0 |
Address offset |
0x0000 0080 |
||
Physical address |
0x4008 2080 |
Instance |
PRCM |
Description |
SSI Clock Gate For Deep Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||
1:0 |
CLK_EN |
|
RW |
0x0 |
Address offset |
0x0000 0084 |
||
Physical address |
0x4008 2084 |
Instance |
PRCM |
Description |
I2S Clock Gate For Run Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 0088 |
||
Physical address |
0x4008 2088 |
Instance |
PRCM |
Description |
I2S Clock Gate For Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 008C |
||
Physical address |
0x4008 208C |
Instance |
PRCM |
Description |
I2S Clock Gate For Deep Sleep Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
CLK_EN |
|
RW |
0 |
Address offset |
0x0000 00B4 |
||
Physical address |
0x4008 20B4 |
Instance |
PRCM |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||||||||||
2:0 |
RATIO |
Internal
|
RW |
0x0 |
Address offset |
0x0000 00B8 |
||
Physical address |
0x4008 20B8 |
Instance |
PRCM |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||
0 |
RATIO |
Internal
|
RW |
0 |
Address offset |
0x0000 00BC |
||
Physical address |
0x4008 20BC |
Instance |
PRCM |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
3:0 |
RATIO |
Internal
|
RW |
0x0 |
Address offset |
0x0000 00C4 |
||
Physical address |
0x4008 20C4 |
Instance |
PRCM |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
3:0 |
RATIO |
Internal
|
RW |
0x0 |
Address offset |
0x0000 00C8 |
||
Physical address |
0x4008 20C8 |
Instance |
PRCM |
Description |
I2S Clock Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
0 |
SRC |
BCLK source selector |
RW |
0 |
Address offset |
0x0000 00CC |
||
Physical address |
0x4008 20CC |
Instance |
PRCM |
Description |
GPT Scalar |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
3:0 |
RATIO |
Scalar used for GPTs. The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when it is slower than the PERBUSCPUCLKDIV.RATIO setting. When set faster than PERBUSCPUCLKDIV.RATIO setting the PERBUSCPUCLKDIV.RATIO will be used.
|
RW |
0x0 |
Address offset |
0x0000 00D0 |
||
Physical address |
0x4008 20D0 |
Instance |
PRCM |
Description |
I2S Clock Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
SMPL_ON_POSEDGE |
On the I2S serial interface, data and WCLK is sampled and clocked out on opposite edges of BCLK. |
RW |
0 |
||
2:1 |
WCLK_PHASE |
Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV). |
RW |
0x0 |
||
0 |
EN |
|
RW |
0 |
Address offset |
0x0000 00D4 |
||
Physical address |
0x4008 20D4 |
Instance |
PRCM |
Description |
MCLK Division Ratio |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
9:0 |
MDIV |
An unsigned factor of the division ratio used to generate MCLK [2-1024]: |
RW |
0x000 |
Address offset |
0x0000 00D8 |
||
Physical address |
0x4008 20D8 |
Instance |
PRCM |
Description |
BCLK Division Ratio |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
9:0 |
BDIV |
An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: |
RW |
0x000 |
Address offset |
0x0000 00DC |
||
Physical address |
0x4008 20DC |
Instance |
PRCM |
Description |
WCLK Division Ratio |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
WDIV |
If I2SCLKCTL.WCLK_PHASE = 0, Single phase. |
RW |
0x0000 |
Address offset |
0x0000 00F0 |
||
Physical address |
0x4008 20F0 |
Instance |
PRCM |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
8 |
DMA |
Write 1 to reset. HW cleared. |
WO |
0 |
||
7:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
1 |
TRNG |
Write 1 to reset. HW cleared. |
WO |
0 |
||
0 |
CRYPTO |
Write 1 to reset. HW cleared. |
WO |
0 |
Address offset |
0x0000 00F4 |
||
Physical address |
0x4008 20F4 |
Instance |
PRCM |
Description |
RESET For GPIO IPs |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
GPIO |
|
WO |
0 |
Address offset |
0x0000 00F8 |
||
Physical address |
0x4008 20F8 |
Instance |
PRCM |
Description |
RESET For GPT Ips |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||
3:0 |
GPT |
|
WO |
0x0 |
Address offset |
0x0000 00FC |
||
Physical address |
0x4008 20FC |
Instance |
PRCM |
Description |
RESET For I2C IPs |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0 |
||
0 |
I2C |
|
WO |
0 |
Address offset |
0x0000 0100 |
||
Physical address |
0x4008 2100 |
Instance |
PRCM |
Description |
RESET For UART IPs |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0 |
||
0 |
UART |
|
WO |
0 |
Address offset |
0x0000 0104 |
||
Physical address |
0x4008 2104 |
Instance |
PRCM |
Description |
RESET For SSI IPs |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1:0 |
SSI |
SSI 0: |
WO |
0x0 |
Address offset |
0x0000 0108 |
||
Physical address |
0x4008 2108 |
Instance |
PRCM |
Description |
RESET For I2S IP |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
I2S |
|
WO |
0 |
Address offset |
0x0000 010C |
||
Physical address |
0x4008 210C |
Instance |
PRCM |
Description |
SW Initiated Resets |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
MCU |
|
WO |
0 |
||
1 |
RFC |
|
WO |
0 |
||
0 |
CPU |
|
WO |
0 |
Address offset |
0x0000 0110 |
||
Physical address |
0x4008 2110 |
Instance |
PRCM |
Description |
WARM Reset Control And Status |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
WR_TO_PINRESET |
|
RW |
0 |
||
1 |
LOCKUP_STAT |
|
RO |
0 |
||
0 |
WDT_STAT |
|
RO |
0 |
Address offset |
0x0000 012C |
||
Physical address |
0x4008 212C |
Instance |
PRCM |
Description |
Power Domain Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
PERIPH_ON |
PERIPH Power domain. |
RW |
0 |
||
1 |
SERIAL_ON |
SERIAL Power domain. |
RW |
0 |
||
0 |
RFC_ON |
|
RW |
0 |
Address offset |
0x0000 0130 |
||
Physical address |
0x4008 2130 |
Instance |
PRCM |
Description |
RFC Power Domain Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
Alias for PDCTL0.RFC_ON |
RW |
0 |
Address offset |
0x0000 0134 |
||
Physical address |
0x4008 2134 |
Instance |
PRCM |
Description |
SERIAL Power Domain Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
Alias for PDCTL0.SERIAL_ON |
RW |
0 |
Address offset |
0x0000 0138 |
||
Physical address |
0x4008 2138 |
Instance |
PRCM |
Description |
PERIPH Power Domain Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
Alias for PDCTL0.PERIPH_ON |
RW |
0 |
Address offset |
0x0000 0140 |
||
Physical address |
0x4008 2140 |
Instance |
PRCM |
Description |
Power Domain Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
PERIPH_ON |
PERIPH Power domain. |
RO |
0 |
||
1 |
SERIAL_ON |
SERIAL Power domain. |
RO |
0 |
||
0 |
RFC_ON |
RFC Power domain |
RO |
0 |
Address offset |
0x0000 0144 |
||
Physical address |
0x4008 2144 |
Instance |
PRCM |
Description |
RFC Power Domain Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
Alias for PDSTAT0.RFC_ON |
RO |
0 |
Address offset |
0x0000 0148 |
||
Physical address |
0x4008 2148 |
Instance |
PRCM |
Description |
SERIAL Power Domain Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
Alias for PDSTAT0.SERIAL_ON |
RO |
0 |
Address offset |
0x0000 014C |
||
Physical address |
0x4008 214C |
Instance |
PRCM |
Description |
PERIPH Power Domain Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
Alias for PDSTAT0.PERIPH_ON |
RO |
0 |
Address offset |
0x0000 017C |
||
Physical address |
0x4008 217C |
Instance |
PRCM |
Description |
Power Domain Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
3 |
VIMS_MODE |
|
RW |
1 |
||
2 |
RFC_ON |
|
RW |
0 |
||
1 |
CPU_ON |
|
RW |
1 |
||
0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
Address offset |
0x0000 0184 |
||
Physical address |
0x4008 2184 |
Instance |
PRCM |
Description |
CPU Power Domain Direct Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
This is an alias for PDCTL1.CPU_ON |
RW |
1 |
Address offset |
0x0000 0188 |
||
Physical address |
0x4008 2188 |
Instance |
PRCM |
Description |
RFC Power Domain Direct Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
This is an alias for PDCTL1.RFC_ON |
RW |
0 |
Address offset |
0x0000 018C |
||
Physical address |
0x4008 218C |
Instance |
PRCM |
Description |
VIMS mode Direct Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
This is an alias for PDCTL1.VIMS_MODE |
RW |
1 |
Address offset |
0x0000 0194 |
||
Physical address |
0x4008 2194 |
Instance |
PRCM |
Description |
Power Manager Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4 |
BUS_ON |
|
RO |
1 |
||
3 |
VIMS_MODE |
|
RO |
1 |
||
2 |
RFC_ON |
|
RO |
0 |
||
1 |
CPU_ON |
|
RO |
1 |
||
0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
Address offset |
0x0000 0198 |
||
Physical address |
0x4008 2198 |
Instance |
PRCM |
Description |
BUS Power Domain Direct Read Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
This is an alias for PDSTAT1.BUS_ON |
RO |
1 |
Address offset |
0x0000 019C |
||
Physical address |
0x4008 219C |
Instance |
PRCM |
Description |
RFC Power Domain Direct Read Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
This is an alias for PDSTAT1.RFC_ON |
RO |
0 |
Address offset |
0x0000 01A0 |
||
Physical address |
0x4008 21A0 |
Instance |
PRCM |
Description |
CPU Power Domain Direct Read Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
This is an alias for PDSTAT1.CPU_ON |
RO |
1 |
Address offset |
0x0000 01A4 |
||
Physical address |
0x4008 21A4 |
Instance |
PRCM |
Description |
VIMS mode Direct Read Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ON |
This is an alias for PDSTAT1.VIMS_MODE |
RO |
1 |
Address offset |
0x0000 01D0 |
||
Physical address |
0x4008 21D0 |
Instance |
PRCM |
Description |
Selected RFC Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||||||||||||||||||
2:0 |
CURR |
Written by MCU - Outputs to RFC. Only modes permitted by RFCMODEHWOPT.AVAIL are writeable.
|
RW |
0x0 |
Address offset |
0x0000 0224 |
||
Physical address |
0x4008 2224 |
Instance |
PRCM |
Description |
Memory Retention Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
RFC |
|
RW |
0 |
||
1:0 |
VIMS |
|
RW |
0x3 |
Address offset |
0x0000 022C |
||
Physical address |
0x4008 222C |
Instance |
PRCM |
Description |
Power Domain Retention Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
1 |
||
6 |
PERIPH |
|
RW |
1 |
||
5 |
SERIAL |
Domain not designed for retention. Writing this bit will have no effect. |
RW |
1 |
||
4 |
RFC |
Domain not designed for retention. Writing this bit will have no effect. |
RW |
0 |
||
3 |
BUS |
Domain not designed for retention. Writing this bit will have no effect. |
RW |
0 |
||
2 |
Reserved |
Internal field controlled by TI provided startup code |
RW |
1 |
||
1 |
CPU |
|
RW |
1 |
||
0 |
CLKCTL |
Domain not designed for retention. Writing this bit will have no effect. |
RW |
1 |
Address offset |
0x0000 0250 |
||
Physical address |
0x4008 2250 |
Instance |
PRCM |
Description |
CONFIG SIZE For SRAM |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||
1:0 |
SIZE |
Internal field controlled by TI provided startup code
|
RW |
0x3 |
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