Instance: CPU_TIPROP
Component: CPU_TIPROP
Base address: 0xe00fe000
Cortex-M's TI proprietary registers
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0FF8 |
0xE00F EFF8 |
|
RW |
32 |
0x0000 0000 |
0x0000 0FFC |
0xE00F EFFC |
Address offset |
0x0000 0FF8 |
||
Physical address |
0xE00F EFF8 |
Instance |
CPU_TIPROP |
Description |
Mux Selector for SWV or TRACECLK |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:1 |
RESERVED |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 0000 |
|||||||||||||
0 |
TRACECLK_N_SWV |
Mux selector for SWV or TRACECLK
|
RW |
0 |
Address offset |
0x0000 0FFC |
||
Physical address |
0xE00F EFFC |
Instance |
CPU_TIPROP |
Description |
Clock Gating Scheme Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
RESERVED |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 0000 |
||
1:0 |
DYN_CG |
Clock gating scheme configuration: |
RW |
0x0 |
© 2015. Texas Instruments | All Rights Reserved |