Instance: CRYPTO
Component: CRYPTO
Base address: 0x40024000
Crypto core with DMA capability and local key storage
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4002 4000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4002 4004 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4002 400C |
|
RO |
32 |
0x0000 0000 |
0x0000 0018 |
0x4002 4018 |
|
WO |
32 |
0x0000 0000 |
0x0000 001C |
0x4002 401C |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4002 4020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4002 4024 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x4002 402C |
|
RW |
32 |
0x0000 2400 |
0x0000 0078 |
0x4002 4078 |
|
RO |
32 |
0x0000 0000 |
0x0000 007C |
0x4002 407C |
|
RO |
32 |
0x0101 2ED1 |
0x0000 00FC |
0x4002 40FC |
|
RW |
32 |
0x0000 0000 |
0x0000 0400 |
0x4002 4400 |
|
RW |
32 |
0x0000 0000 |
0x0000 0404 |
0x4002 4404 |
|
RW |
32 |
0x0000 0001 |
0x0000 0408 |
0x4002 4408 |
|
RW |
32 |
0x0000 0008 |
0x0000 040C |
0x4002 440C |
|
WO |
32 |
0x0000 0000 |
0x0000 0500-0x0000 050C |
0x4002 4500- 0x4002 450C |
|
WO |
32 |
0x0000 0000 |
0x0000 0510-0x0000 051C |
0x4002 4510- 0x4002 451C |
|
RW |
32 |
0x0000 0000 |
0x0000 0540-0x0000 054C |
0x4002 4540- 0x4002 454C |
|
RW |
32 |
0x8000 0000 |
0x0000 0550 |
0x4002 4550 |
|
WO |
32 |
0x0000 0000 |
0x0000 0554 |
0x4002 4554 |
|
WO |
32 |
0x0000 0000 |
0x0000 0558 |
0x4002 4558 |
|
WO |
32 |
0x0000 0000 |
0x0000 055C |
0x4002 455C |
|
WO |
32 |
0x0000 0000 |
0x0000 0560 |
0x4002 4560 |
|
RO |
32 |
0x0000 0000 |
0x0000 0560 |
0x4002 4560 |
|
WO |
32 |
0x0000 0000 |
0x0000 0564 |
0x4002 4564 |
|
RO |
32 |
0x0000 0000 |
0x0000 0564 |
0x4002 4564 |
|
WO |
32 |
0x0000 0000 |
0x0000 0568 |
0x4002 4568 |
|
RO |
32 |
0x0000 0000 |
0x0000 0568 |
0x4002 4568 |
|
WO |
32 |
0x0000 0000 |
0x0000 056C |
0x4002 456C |
|
RO |
32 |
0x0000 0000 |
0x0000 056C |
0x4002 456C |
|
RO |
32 |
0x0000 0000 |
0x0000 0570-0x0000 057C |
0x4002 4570- 0x4002 457C |
|
RW |
32 |
0x0000 0000 |
0x0000 0700 |
0x4002 4700 |
|
RW |
32 |
0x0000 0000 |
0x0000 0704 |
0x4002 4704 |
|
RW |
32 |
0x0000 0000 |
0x0000 0740 |
0x4002 4740 |
|
RW |
32 |
0x0000 0000 |
0x0000 0780 |
0x4002 4780 |
|
RW |
32 |
0x0000 0000 |
0x0000 0784 |
0x4002 4784 |
|
WO |
32 |
0x0000 0000 |
0x0000 0788 |
0x4002 4788 |
|
WO |
32 |
0x0000 0000 |
0x0000 078C |
0x4002 478C |
|
RO |
32 |
0x0000 0000 |
0x0000 0790 |
0x4002 4790 |
|
RO |
32 |
0x9111 8778 |
0x0000 07FC |
0x4002 47FC |
Address offset |
0x0000 0000 |
||
Physical address |
0x4002 4000 |
Instance |
CRYPTO |
Description |
DMA Channel 0 Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 0000 |
|||||||||||||
1 |
PRIO |
Channel priority:
|
RW |
0 |
|||||||||||||
0 |
EN |
DMA Channel 0 Control
|
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4002 4004 |
Instance |
CRYPTO |
Description |
DMA Channel 0 External Address |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
ADDR |
Channel external address value. |
RW |
0x0000 0000 |
Address offset |
0x0000 000C |
||
Physical address |
0x4002 400C |
Instance |
CRYPTO |
Description |
DMA Channel 0 Length |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 |
||
15:0 |
LEN |
DMA transfer length in bytes. |
RW |
0x0000 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4002 4018 |
Instance |
CRYPTO |
Description |
DMA Controller Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:18 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
17 |
PORT_ERR |
Reflects possible transfer errors on the AHB port. |
RO |
0 |
||
16:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
1 |
CH1_ACTIVE |
This register field indicates if DMA channel 1 is active or not. |
RO |
0 |
||
0 |
CH0_ACTIVE |
This register field indicates if DMA channel 0 is active or not. |
RO |
0 |
Address offset |
0x0000 001C |
||
Physical address |
0x4002 401C |
Instance |
CRYPTO |
Description |
DMA Controller Software Reset |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0000 0000 |
||
0 |
RESET |
Software reset enable |
WO |
0 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4002 4020 |
Instance |
CRYPTO |
Description |
DMA Channel 1 Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 0000 |
|||||||||||||
1 |
PRIO |
Channel priority:
|
RW |
0 |
|||||||||||||
0 |
EN |
Channel enable:
|
RW |
0 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4002 4024 |
Instance |
CRYPTO |
Description |
DMA Channel 1 External Address |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
ADDR |
Channel external address value. |
RW |
0x0000 0000 |
Address offset |
0x0000 002C |
||
Physical address |
0x4002 402C |
Instance |
CRYPTO |
Description |
DMA Channel 1 Length |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 |
||
15:0 |
LEN |
DMA transfer length in bytes. |
RW |
0x0000 |
Address offset |
0x0000 0078 |
||
Physical address |
0x4002 4078 |
Instance |
CRYPTO |
Description |
DMA Controller Master Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 |
|||||||||||||||||||||||||
15:12 |
AHB_MST1_BURST_SIZE |
Maximum burst size that can be performed on the AHB bus
|
RW |
0x2 |
|||||||||||||||||||||||||
11 |
AHB_MST1_IDLE_EN |
Idle transfer insertion between consecutive burst transfers on AHB
|
RW |
0 |
|||||||||||||||||||||||||
10 |
AHB_MST1_INCR_EN |
Burst length type of AHB transfer
|
RW |
1 |
|||||||||||||||||||||||||
9 |
AHB_MST1_LOCK_EN |
Locked transform on AHB
|
RW |
0 |
|||||||||||||||||||||||||
8 |
AHB_MST1_BIGEND |
Endianess for the AHB master
|
RW |
0 |
|||||||||||||||||||||||||
7:0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 |
Address offset |
0x0000 007C |
||
Physical address |
0x4002 407C |
Instance |
CRYPTO |
Description |
DMA Controller Port Error |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:13 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
||
12 |
AHB_ERR |
A 1 indicates that the Crypto peripheral has detected an AHB bus error |
RO |
0 |
||
11:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
9 |
LAST_CH |
Indicates which channel was serviced last (channel 0 or channel 1) by the AHB master port. |
RO |
0 |
||
8:0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 |
Address offset |
0x0000 00FC |
||
Physical address |
0x4002 40FC |
Instance |
CRYPTO |
Description |
DMA Controller Version |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:28 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
27:24 |
HW_MAJOR_VER |
Major version number |
RO |
0x1 |
||
23:20 |
HW_MINOR_VER |
Minor version number |
RO |
0x0 |
||
19:16 |
HW_PATCH_LVL |
Patch level. |
RO |
0x1 |
||
15:8 |
VER_NUM_COMPL |
Bit-by-bit complement of the VER_NUM field bits. |
RO |
0x2E |
||
7:0 |
VER_NUM |
Version number of the DMA Controller (209) |
RO |
0xD1 |
Address offset |
0x0000 0400 |
||
Physical address |
0x4002 4400 |
Instance |
CRYPTO |
Description |
Key Write Area |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 0000 |
|||||||||||||
7 |
RAM_AREA7 |
Represents an area of 128 bits.
|
RW |
0 |
|||||||||||||
6 |
RAM_AREA6 |
Represents an area of 128 bits.
|
RW |
0 |
|||||||||||||
5 |
RAM_AREA5 |
Represents an area of 128 bits.
|
RW |
0 |
|||||||||||||
4 |
RAM_AREA4 |
Represents an area of 128 bits.
|
RW |
0 |
|||||||||||||
3 |
RAM_AREA3 |
Represents an area of 128 bits.
|
RW |
0 |
|||||||||||||
2 |
RAM_AREA2 |
Represents an area of 128 bits.
|
RW |
0 |
|||||||||||||
1 |
RAM_AREA1 |
Represents an area of 128 bits.
|
RW |
0 |
|||||||||||||
0 |
RAM_AREA0 |
Represents an area of 128 bits.
|
RW |
0 |
Address offset |
0x0000 0404 |
||
Physical address |
0x4002 4404 |
Instance |
CRYPTO |
Description |
Key Written Area Status |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 0000 |
|||||||||||||
7 |
RAM_AREA_WRITTEN7 |
On read this bit returns the key area written status.
|
RW |
0 |
|||||||||||||
6 |
RAM_AREA_WRITTEN6 |
On read this bit returns the key area written status.
|
RW |
0 |
|||||||||||||
5 |
RAM_AREA_WRITTEN5 |
On read this bit returns the key area written status.
|
RW |
0 |
|||||||||||||
4 |
RAM_AREA_WRITTEN4 |
On read this bit returns the key area written status.
|
RW |
0 |
|||||||||||||
3 |
RAM_AREA_WRITTEN3 |
On read this bit returns the key area written status.
|
RW |
0 |
|||||||||||||
2 |
RAM_AREA_WRITTEN2 |
On read this bit returns the key area written status.
|
RW |
0 |
|||||||||||||
1 |
RAM_AREA_WRITTEN1 |
On read this bit returns the key area written status.
|
RW |
0 |
|||||||||||||
0 |
RAM_AREA_WRITTEN0 |
On read this bit returns the key area written status.
|
RW |
0 |
Address offset |
0x0000 0408 |
||
Physical address |
0x4002 4408 |
Instance |
CRYPTO |
Description |
Key Size |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 0000 |
|||||||||||||||||
1:0 |
SIZE |
Key size
|
RW |
0x1 |
Address offset |
0x0000 040C |
||
Physical address |
0x4002 440C |
Instance |
CRYPTO |
Description |
Key Read Area |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31 |
BUSY |
Key store operation busy status flag (read only) |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||
30:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
3:0 |
RAM_AREA |
Selects the area of the key store RAM from where the key needs to be read that will be written to the AES engine.
|
RW |
0x8 |
Address offset |
0x0000 0500-0x0000 050C |
||
Physical address |
0x4002 4500- 0x4002 450C |
Instance |
CRYPTO |
Description |
Clear AES_KEY2/GHASH Key |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
KEY2 |
AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register array. |
WO |
0x0000 0000 |
Address offset |
0x0000 0510-0x0000 051C |
||
Physical address |
0x4002 4510- 0x4002 451C |
Instance |
CRYPTO |
Description |
Clear AES_KEY3 |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
KEY3 |
AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register arrary. |
WO |
0x0000 0000 |
Address offset |
0x0000 0540-0x0000 054C |
||
Physical address |
0x4002 4540- 0x4002 454C |
Instance |
CRYPTO |
Description |
AES Initialization Vector |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
IV |
The interpretation of this field depends on the crypto operation mode. |
RW |
0x0000 0000 |
Address offset |
0x0000 0550 |
||
Physical address |
0x4002 4550 |
Instance |
CRYPTO |
Description |
AES Input/Output Buffer Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31 |
CONTEXT_RDY |
If 1, this status bit indicates that the context data registers can be overwritten and the Host is permitted to write the next context. Writing a context means writing either a mode, the crypto length or AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers |
RO |
1 |
|||||||||||||||||||||
30 |
SAVED_CONTEXT_RDY |
If read as 1, this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the Host to retrieve. This bit is only asserted if SAVE_CONTEXT is set to 1. The bit is mutually exclusive with CONTEXT_RDY. |
RW |
0 |
|||||||||||||||||||||
29 |
SAVE_CONTEXT |
IV must be read before the AES engine can start a new operation. |
RW |
0 |
|||||||||||||||||||||
28:25 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
|||||||||||||||||||||
24:22 |
CCM_M |
Defines M that indicates the length of the authentication field for CCM operations; the authentication field length equals two times the value of CCM_M plus one. |
RW |
0x0 |
|||||||||||||||||||||
21:19 |
CCM_L |
Defines L that indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM_L plus one. All values are supported. |
RW |
0x0 |
|||||||||||||||||||||
18 |
CCM |
AES-CCM mode enable. |
RW |
0 |
|||||||||||||||||||||
17:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
|||||||||||||||||||||
15 |
CBC_MAC |
MAC mode enable. |
RW |
0 |
|||||||||||||||||||||
14:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 |
|||||||||||||||||||||
8:7 |
CTR_WIDTH |
Specifies the counter width for AES-CTR mode
|
RW |
0x0 |
|||||||||||||||||||||
6 |
CTR |
AES-CTR mode enable |
RW |
0 |
|||||||||||||||||||||
5 |
CBC |
CBC mode enable |
RW |
0 |
|||||||||||||||||||||
4:3 |
KEY_SIZE |
This field specifies the key size. |
RO |
0x0 |
|||||||||||||||||||||
2 |
DIR |
Direction. |
RW |
0 |
|||||||||||||||||||||
1 |
INPUT_RDY |
If read as 1, this status bit indicates that the 16-byte AES input buffer is empty. The Host is permitted to write the next block of data. |
RW |
0 |
|||||||||||||||||||||
0 |
OUTPUT_RDY |
If read as 1, this status bit indicates that an AES output block is available to be retrieved by the Host. |
RW |
0 |
Address offset |
0x0000 0554 |
||
Physical address |
0x4002 4554 |
Instance |
CRYPTO |
Description |
Crypto Data Length LSW |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
LEN_LSW |
Used to write the Length values to the Crypto peripheral. |
WO |
0x0000 0000 |
Address offset |
0x0000 0558 |
||
Physical address |
0x4002 4558 |
Instance |
CRYPTO |
Description |
Crypto Data Length MSW |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:29 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0 |
||
28:0 |
LEN_MSW |
Bits [60:32] of the combined data length. |
WO |
0x0000 0000 |
Address offset |
0x0000 055C |
||
Physical address |
0x4002 455C |
Instance |
CRYPTO |
Description |
AES Authentication Length |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
LEN |
Authentication data length in bytes for combined mode, CCM only. |
WO |
0x0000 0000 |
Address offset |
0x0000 0560 |
||
Physical address |
0x4002 4560 |
Instance |
CRYPTO |
Description |
AES Data Input/Output 0 |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DATA |
Data registers for input block data to the Crypto peripheral. |
WO |
0x0000 0000 |
Address offset |
0x0000 0560 |
||
Physical address |
0x4002 4560 |
Instance |
CRYPTO |
Description |
Data Input/Output |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DATA |
Data register 0 for output block data from the Crypto peripheral. |
RO |
0x0000 0000 |
Address offset |
0x0000 0564 |
||
Physical address |
0x4002 4564 |
Instance |
CRYPTO |
Description |
AES Data Input/Output 1 |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DATA |
Data registers for input block data to the Crypto peripheral. |
WO |
0x0000 0000 |
Address offset |
0x0000 0564 |
||
Physical address |
0x4002 4564 |
Instance |
CRYPTO |
Description |
AES Data Input/Output 3 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DATA |
Data registers for output block data from the Crypto peripheral. |
RO |
0x0000 0000 |
Address offset |
0x0000 0568 |
||
Physical address |
0x4002 4568 |
Instance |
CRYPTO |
Description |
AES Data Input/Output 2 |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DATA |
Data registers for input block data to the Crypto peripheral. |
WO |
0x0000 0000 |
Address offset |
0x0000 0568 |
||
Physical address |
0x4002 4568 |
Instance |
CRYPTO |
Description |
AES Data Input/Output 2 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DATA |
Data registers for output block data from the Crypto peripheral. |
RO |
0x0000 0000 |
Address offset |
0x0000 056C |
||
Physical address |
0x4002 456C |
Instance |
CRYPTO |
Description |
Data Input/Output |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DATA |
Data registers for input block data to the Crypto peripheral. |
WO |
0x0000 0000 |
Address offset |
0x0000 056C |
||
Physical address |
0x4002 456C |
Instance |
CRYPTO |
Description |
AES Data Input/Output 3 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DATA |
Data registers for output block data from the Crypto peripheral. |
RO |
0x0000 0000 |
Address offset |
0x0000 0570-0x0000 057C |
||
Physical address |
0x4002 4570- 0x4002 457C |
Instance |
CRYPTO |
Description |
AES Tag Output |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TAG |
This register contains the authentication TAG for the combined and authentication-only modes. |
RO |
0x0000 0000 |
Address offset |
0x0000 0700 |
||
Physical address |
0x4002 4700 |
Instance |
CRYPTO |
Description |
Master Algorithm Select |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
TAG |
If this bit is cleared to 0, the DMA operation involves only data. |
RW |
0 |
||
30:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 0000 |
||
1 |
AES |
If set to 1, the AES data is loaded via DMA |
RW |
0 |
||
0 |
KEY_STORE |
If set to 1, selects the Key Store to be loaded via DMA. |
RW |
0 |
Address offset |
0x0000 0704 |
||
Physical address |
0x4002 4704 |
Instance |
CRYPTO |
Description |
Master Protection Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 0000 |
||
0 |
EN |
Select AHB transfer protection control for DMA transfers using the key store area as destination. |
RW |
0 |
Address offset |
0x0000 0740 |
||
Physical address |
0x4002 4740 |
Instance |
CRYPTO |
Description |
Software Reset |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 0000 |
||
0 |
RESET |
If this bit is set to 1, the following modules are reset: |
RW |
0 |
Address offset |
0x0000 0780 |
||
Physical address |
0x4002 4780 |
Instance |
CRYPTO |
Description |
Interrupt Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 0000 |
||
0 |
IEN |
Interrupt enable. This bit must be set to 1 to enable interrupts from the Crypto peripheral. |
RW |
0 |
Address offset |
0x0000 0784 |
||
Physical address |
0x4002 4784 |
Instance |
CRYPTO |
Description |
Interrupt Enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 0000 |
||
1 |
DMA_IN_DONE |
This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. |
RW |
0 |
||
0 |
RESULT_AVAIL |
This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. |
RW |
0 |
Address offset |
0x0000 0788 |
||
Physical address |
0x4002 4788 |
Instance |
CRYPTO |
Description |
Interrupt Clear |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
DMA_BUS_ERR |
If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared. |
WO |
0 |
||
30 |
KEY_ST_WR_ERR |
If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared. |
WO |
0 |
||
29 |
KEY_ST_RD_ERR |
If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared. |
WO |
0 |
||
28:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x000 0000 |
||
1 |
DMA_IN_DONE |
If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. |
WO |
0 |
||
0 |
RESULT_AVAIL |
If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. |
WO |
0 |
Address offset |
0x0000 078C |
||
Physical address |
0x4002 478C |
Instance |
CRYPTO |
Description |
Interrupt Set |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0000 0000 |
||
1 |
DMA_IN_DONE |
If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. |
WO |
0 |
||
0 |
RESULT_AVAIL |
If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. |
WO |
0 |
Address offset |
0x0000 0790 |
||
Physical address |
0x4002 4790 |
Instance |
CRYPTO |
Description |
Interrupt Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
DMA_BUS_ERR |
This bit is set when a DMA bus error is detected during a DMA operation. The value of this register is held until it is cleared via IRQCLR.DMA_BUS_ERR |
RO |
0 |
||
30 |
KEY_ST_WR_ERR |
This bit is set when a write error is detected during the DMA write operation to the key store memory. The value of this register is held until it is cleared via IRQCLR.KEY_ST_WR_ERR |
RO |
0 |
||
29 |
KEY_ST_RD_ERR |
This bit will be set when a read error is detected during the read of a key from the key store, while copying it to the AES engine. The value of this register is held until it is cleared via IRQCLR.KEY_ST_RD_ERR. |
RO |
0 |
||
28:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
1 |
DMA_IN_DONE |
This bit returns the status of DMA data in done interrupt. |
RO |
0 |
||
0 |
RESULT_AVAIL |
This bit is set high when the Crypto peripheral has a result available. |
RO |
0 |
Address offset |
0x0000 07FC |
||
Physical address |
0x4002 47FC |
Instance |
CRYPTO |
Description |
CTRL Module Version |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:28 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x9 |
||
27:24 |
HW_MAJOR_VER |
Major version number |
RO |
0x1 |
||
23:20 |
HW_MINOR_VER |
Minor version number |
RO |
0x1 |
||
19:16 |
HW_PATCH_LVL |
Patch level, starts at 0 at first delivery of this version. |
RO |
0x1 |
||
15:8 |
VER_NUM_COMPL |
These bits simply contain the complement of VER_NUM (0x87), used by a driver to ascertain that the Crypto peripheral register is indeed read. |
RO |
0x87 |
||
7:0 |
VER_NUM |
The version number for the Crypto peripheral, this field contains the value 120 (decimal) or 0x78. |
RO |
0x78 |
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