Instance: RFC_RFE
Component: RFC_RFE
Base address: 0x40046000
Component for rfe register bank
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4004 6000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4004 6004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4004 6008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4004 600C |
|
RO |
32 |
0x0000 0000 |
0x0000 0010 |
0x4004 6010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x4004 6014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4004 6018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x4004 601C |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4004 6020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4004 6024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4004 6028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x4004 602C |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x4004 6030 |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x4004 6034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4004 6038 |
|
RO |
32 |
0x0000 0000 |
0x0000 003C |
0x4004 603C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x4004 6040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4004 6044 |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x4004 6048 |
|
RW |
32 |
0x0000 0000 |
0x0000 004C |
0x4004 604C |
|
RO |
32 |
0x0000 0000 |
0x0000 0050 |
0x4004 6050 |
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0x4004 6054 |
|
RW |
32 |
0x0000 0000 |
0x0000 0058 |
0x4004 6058 |
|
RW |
32 |
0x0000 0000 |
0x0000 005C |
0x4004 605C |
|
RW |
32 |
0x0000 0000 |
0x0000 0060 |
0x4004 6060 |
|
RW |
32 |
0x0000 0000 |
0x0000 0064 |
0x4004 6064 |
|
RO |
32 |
0x0000 0000 |
0x0000 0068 |
0x4004 6068 |
|
RO |
32 |
0x0000 0000 |
0x0000 006C |
0x4004 606C |
|
RW |
32 |
0x0000 0000 |
0x0000 0070 |
0x4004 6070 |
|
RO |
32 |
0x0000 0000 |
0x0000 0074 |
0x4004 6074 |
|
RO |
32 |
0x0000 0000 |
0x0000 0078 |
0x4004 6078 |
|
RW |
32 |
0x0000 0000 |
0x0000 007C |
0x4004 607C |
|
RW |
32 |
0x0000 0000 |
0x0000 0080 |
0x4004 6080 |
|
RW |
32 |
0x0000 0000 |
0x0000 0084 |
0x4004 6084 |
|
RW |
32 |
0x0000 0000 |
0x0000 0088 |
0x4004 6088 |
|
RW |
32 |
0x0000 0000 |
0x0000 008C |
0x4004 608C |
|
RW |
32 |
0x0000 0000 |
0x0000 0090 |
0x4004 6090 |
|
RW |
32 |
0x0000 0000 |
0x0000 0094 |
0x4004 6094 |
|
RW |
32 |
0x0000 0000 |
0x0000 0098 |
0x4004 6098 |
|
RW |
32 |
0x0000 0000 |
0x0000 009C |
0x4004 609C |
|
RW |
32 |
0x0000 0000 |
0x0000 00A0 |
0x4004 60A0 |
|
RW |
32 |
0x0000 0000 |
0x0000 00A4 |
0x4004 60A4 |
|
RO |
32 |
0x0000 0000 |
0x0000 00A8 |
0x4004 60A8 |
|
RO |
32 |
0x0000 0000 |
0x0000 00AC |
0x4004 60AC |
|
RW |
32 |
0x0000 0000 |
0x0000 00B0 |
0x4004 60B0 |
|
RO |
32 |
0x0000 0000 |
0x0000 00B4 |
0x4004 60B4 |
|
RW |
32 |
0x0000 0000 |
0x0000 00B8 |
0x4004 60B8 |
|
RW |
32 |
0x0000 0000 |
0x0000 00BC |
0x4004 60BC |
|
RW |
32 |
0x0000 0000 |
0x0000 00C0 |
0x4004 60C0 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4004 6000 |
Instance |
RFC_RFE |
Description |
RF Engine Enable Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
ACC1 |
Enables the Magnitude Accumulator 1 |
RW |
0 |
||
2 |
ACC0 |
Enables the Magnitude Accumulator 0 |
RW |
0 |
||
1 |
LOC_TIM |
Enables the Local timer |
RW |
0 |
||
0 |
TOPSM |
Enables the TOPsm (RFE) |
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4004 6004 |
Instance |
RFC_RFE |
Description |
RF Engine Initialization Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
ACC1 |
Synch reset Magnitude Accumulator 1 |
RW |
0 |
||
2 |
ACC0 |
Sunch reset Magnitude Accumulator 0 |
RW |
0 |
||
1 |
LOC_TIM |
Synch reset Local timer |
RW |
0 |
||
0 |
TOPSM |
Synch reset TOPsm (RFE) |
RW |
0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4004 6008 |
Instance |
RFC_RFE |
Description |
RF Engine Power-down Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
TOPSMPDREQ |
Requests power down for TOPsm core. If the TOPsm has an ongoing memory access, the hardware will safely gate the clock after the transaction has completed. |
RW |
0 |
Address offset |
0x0000 000C |
||
Physical address |
0x4004 600C |
Instance |
RFC_RFE |
Description |
RF Engine (RFE) Strobe Register 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
EVENT2 |
Firmware defined event 2 |
RW |
0 |
||
2 |
EVENT1 |
Firmware defined event 1 |
RW |
0 |
||
1 |
EVENT0 |
Firmware defined event 0 |
RW |
0 |
||
0 |
CMDDONE |
Signal command done to CPE |
RW |
0 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4004 6010 |
Instance |
RFC_RFE |
Description |
RFE Event Flag Register 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
EVENT |
Event flags for timer, counter, accumulators and command handling |
RO |
0x0000 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4004 6014 |
Instance |
RFC_RFE |
Description |
RFE Event Mask Register 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
EVENTMSK |
Event mask for timer, counter, accumulators and command handling |
RW |
0x0000 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4004 6018 |
Instance |
RFC_RFE |
Description |
RFE Event Clear Register 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
EVENTCLR |
Clear event flag for timer, counter, accumulators and command handling |
RW |
0x0000 |
Address offset |
0x0000 001C |
||
Physical address |
0x4004 601C |
Instance |
RFC_RFE |
Description |
RFE Program Source Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||
3:1 |
ROMBANK |
RFE ROM configuration
|
RW |
0x0 |
|||||||||||||||||||||||||||||
0 |
RAMROM |
Map RFE RAM as ROM
|
RW |
0 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4004 6020 |
Instance |
RFC_RFE |
Description |
RFE API Command Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4:0 |
RFECMD |
RFE Command |
RW |
0x00 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4004 6024 |
Instance |
RFC_RFE |
Description |
RFE Command Parameter 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PAR0 |
Parameter 0 |
RW |
0x0000 |
Address offset |
0x0000 0028 |
||
Physical address |
0x4004 6028 |
Instance |
RFC_RFE |
Description |
RFE Command Parameter 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PAR1 |
Parameter 1 |
RW |
0x0000 |
Address offset |
0x0000 002C |
||
Physical address |
0x4004 602C |
Instance |
RFC_RFE |
Description |
RFE Command Status and Message Box Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
MSG |
Diverse status, error, report bits from RFE |
RW |
0x0000 |
Address offset |
0x0000 0030 |
||
Physical address |
0x4004 6030 |
Instance |
RFC_RFE |
Description |
CPE Interrupt Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
CMDSTACHG |
The CMDSTA has changed (not implemented) |
RW |
0 |
||
0 |
MSGBOX |
There is something in the MSGBOX (not implemented) |
RW |
0 |
Address offset |
0x0000 0034 |
||
Physical address |
0x4004 6034 |
Instance |
RFC_RFE |
Description |
CPE Interrupt Mask Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
CMDSTACHGMSK |
'1' to allow RFE_CMDSTACHG IRQ to CPE (Note: RFECPEIRQ has no hardware implementation, so this bit can be used by software) |
RW |
0 |
||
0 |
MSGBOXMSK |
'1' to allow MSGBOX IRQ to CPE (Note: RFECPEIRQ has no hardware implementation, so this bit can be used by software) |
RW |
0 |
Address offset |
0x0000 0038 |
||
Physical address |
0x4004 6038 |
Instance |
RFC_RFE |
Description |
RFE-to-MCE Send Command Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
RFECMD |
Command to send to the MCE. Writing to this register will trigger an event in the MCE, and the command value written here will be readable in RFC_MDM:RFERCEV register. |
RW |
0x0000 |
Address offset |
0x0000 003C |
||
Physical address |
0x4004 603C |
Instance |
RFC_RFE |
Description |
MCE-to-RFE Receive Command Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
MCECMD |
Command received from MCE |
RO |
0x0000 |
Address offset |
0x0000 0040 |
||
Physical address |
0x4004 6040 |
Instance |
RFC_RFE |
Description |
ADI Interface 0 Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||
1 |
WRSIZE |
Transaction write size. (The read size is always half register, i.e. 4 bits).
|
RW |
0 |
|||||||||||||
0 |
WREN |
Write enable configuration.
|
RW |
0 |
Address offset |
0x0000 0044 |
||
Physical address |
0x4004 6044 |
Instance |
RFC_RFE |
Description |
ADI Interface 0 Clock |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
CLK |
Generates one clock transaction on the ADI when written to 1. To be used after configuring the desired transaction type in ADI0CTL and address in ADI0ADDRWRDATA registers to perform either one read or write transaction. |
RW |
0 |
Address offset |
0x0000 0048 |
||
Physical address |
0x4004 6048 |
Instance |
RFC_RFE |
Description |
ADI Interface 0 Clear Request |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
REQ0 |
Clears the REQ toggler signal to zero. |
RW |
0 |
Address offset |
0x0000 004C |
||
Physical address |
0x4004 604C |
Instance |
RFC_RFE |
Description |
ADI Interface 0 Address and Write Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:14 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
||
13:8 |
ADDR |
The ADI0 is connected to the [ANATOP_MMAP::ADI_0_RF.*] analog register bank, and uses addresses in range 0..63. The register bank contains 32 registers, each of 8 bits. The address number refers to the register bank in half register (half byte) increments. E.g. address 0 means bits [3:0] of analog register 0, address 1 means bits [7:4] of analog register 0, address 2 means bits [3:0] of analog register 1, (...), and finally, the address 63 means bits [7:4] of analog register 31. |
RW |
0x00 |
||
7:0 |
WRDATA |
ADI0 write data when write mode is enabled. For full register write accesses (ADI0CTL.WRSIZE = 0), this should be the 8 bits data to be written to the two half registers at address ADDR and ADDR + 1. For half register masked write (ADI0CTL.WRSIZE = 1), this should be concatenation of a 4 bit write mask and 4 bits data. The order of the write mask and the data depends on the value of the address. When ADDR is an even value (i.e. referring lower half of a register), the WRDATA should contain the write mask in bits [7:4] and data in [3:0]. When ADDR is an odd value (i.e. referring to upper half of a register), the WRDATA should contain the data in bits [7:4] and write mask in [3:0]. For half register write accesses, only the bits where the write mask bits are set to 1 will be written using the data value, and other register bits will remain unchanged. |
RW |
0x00 |
Address offset |
0x0000 0050 |
||
Physical address |
0x4004 6050 |
Instance |
RFC_RFE |
Description |
ADI Interface 0 Read Data |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4 |
ACK |
Self-timed read transaction is done. Read data in RDDATA is not valid until this reads as 1. |
RO |
0 |
||
3:0 |
RDDATA |
ADI half register read data. |
RO |
0x0 |
Address offset |
0x0000 0054 |
||
Physical address |
0x4004 6054 |
Instance |
RFC_RFE |
Description |
RSSI Offset Adjustment Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
OFFSET |
Offset to convert to dBm (unsigned). This is used by the RFE to adjust its RSSI calculations. |
RW |
0x00 |
Address offset |
0x0000 0058 |
||
Physical address |
0x4004 6058 |
Instance |
RFC_RFE |
Description |
RSSI Value Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
VALUE |
Current RSSI value (signed). If this register reads as -128 (0x80) it means that the value is not yet valid. |
RW |
0x00 |
Address offset |
0x0000 005C |
||
Physical address |
0x4004 605C |
Instance |
RFC_RFE |
Description |
RSSI Maximum Value Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
VALUE |
Maximum RSSI value since start of measurements cycle. If this field reads as -128 (0x80) it means that the value is not yet valid. |
RW |
0x00 |
Address offset |
0x0000 0060 |
||
Physical address |
0x4004 6060 |
Instance |
RFC_RFE |
Description |
Magnitude estimator 0 control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:13 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
|||||||||||||||||||||||||||||||||||||||||
12 |
ACC0PERMODE |
Enable periodic mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||||||
11:8 |
ACC0SCALE |
Scaling value, by factor 1/2^(acc0scale)
|
RW |
0x0 |
|||||||||||||||||||||||||||||||||||||||||
7:0 |
ACC0PERIOD |
Accumulation period, in incoming samples |
RW |
0x00 |
Address offset |
0x0000 0064 |
||
Physical address |
0x4004 6064 |
Instance |
RFC_RFE |
Description |
Magnitude estimator 1 control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:13 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
|||||||||||||||||||||||||||||||||||||||||
12 |
ACC1PERMODE |
Enable periodic mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||||||
11:8 |
ACC1SCALE |
Scaling value, by factor 1/2^(acc1scale)
|
RW |
0x0 |
|||||||||||||||||||||||||||||||||||||||||
7:0 |
ACC1PERIOD |
Accumulation period, in incoming samples |
RW |
0x00 |
Address offset |
0x0000 0068 |
||
Physical address |
0x4004 6068 |
Instance |
RFC_RFE |
Description |
Magnitude estimator 0 accumulator value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
ACCVAL |
Accumulated magnitude over the period |
RO |
0x0000 |
Address offset |
0x0000 006C |
||
Physical address |
0x4004 606C |
Instance |
RFC_RFE |
Description |
Magnitude estimator 1 accumulator value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
ACCVAL |
Accumulated magnitude over the period |
RO |
0x0000 |
Address offset |
0x0000 0070 |
||
Physical address |
0x4004 6070 |
Instance |
RFC_RFE |
Description |
Math accellerator input value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VAL |
Input value in linear units |
RW |
0x0000 |
Address offset |
0x0000 0074 |
||
Physical address |
0x4004 6074 |
Instance |
RFC_RFE |
Description |
Lin2Log output register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
6:0 |
LOGVAL |
Logarithmic output value. Calculation performed: LIN2LOGOUT = 20*log10(MATHACCELIN). |
RO |
0x00 |
Address offset |
0x0000 0078 |
||
Physical address |
0x4004 6078 |
Instance |
RFC_RFE |
Description |
Divide by three output register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3:0 |
DIV3 |
Divider output value. Calculation performed: DIVBY3OUT = MATHACCELIN/3. Supports up to 46 as input value, higher values are saturated. |
RO |
0x0 |
Address offset |
0x0000 007C |
||
Physical address |
0x4004 607C |
Instance |
RFC_RFE |
Description |
RFE gain control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||
3:2 |
BDE1DVGA |
DVGA settings for BDE1. The DVGA control for BDE1 is shared with the MCE in its RFC_MDM:DEMMISC3.BDE1DVGA register. Software should determine who uses them. Please note that if both processors attempt to control it, the resulting setting will be the two settings ORed together.
|
RW |
0x0 |
|||||||||||||||||||||
1:0 |
BDE2DVGA |
DVGA settings for BDE2. The DVGA control for BDE2 is shared with the MCE in its RFC_MDM:DEMMISC3.BDE2DVGA register. Software should determine who uses them. Please note that if both processors attempt to control it, the resulting setting will be the two settings ORed together.
|
RW |
0x0 |
Address offset |
0x0000 0080 |
||
Physical address |
0x4004 6080 |
Instance |
RFC_RFE |
Description |
RF front-end gain value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
DBGAIN |
Current RF front-end gain, in dB |
RW |
0x00 |
Address offset |
0x0000 0084 |
||
Physical address |
0x4004 6084 |
Instance |
RFC_RFE |
Description |
Spare Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VAL |
Spare register for use by firmware. |
RW |
0x0000 |
Address offset |
0x0000 0088 |
||
Physical address |
0x4004 6088 |
Instance |
RFC_RFE |
Description |
Spare Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VAL |
Spare register for use by firmware. |
RW |
0x0000 |
Address offset |
0x0000 008C |
||
Physical address |
0x4004 608C |
Instance |
RFC_RFE |
Description |
Spare Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VAL |
Spare register for use by firmware. |
RW |
0x0000 |
Address offset |
0x0000 0090 |
||
Physical address |
0x4004 6090 |
Instance |
RFC_RFE |
Description |
Spare Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VAL |
Spare register for use by firmware. |
RW |
0x0000 |
Address offset |
0x0000 0094 |
||
Physical address |
0x4004 6094 |
Instance |
RFC_RFE |
Description |
Spare Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VAL |
Spare register for use by firmware. |
RW |
0x0000 |
Address offset |
0x0000 0098 |
||
Physical address |
0x4004 6098 |
Instance |
RFC_RFE |
Description |
Spare Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VAL |
Spare register for use by firmware. |
RW |
0x0000 |
Address offset |
0x0000 009C |
||
Physical address |
0x4004 609C |
Instance |
RFC_RFE |
Description |
RFE Timer and Counter Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:14 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
|||||||||||||||||||||
13:8 |
CAPTURESOURCE |
Selects bit number from event bus to use for a counter capture. Event number in range 0 to 63. |
RW |
0x00 |
|||||||||||||||||||||
7 |
ENABLECAPTURE |
Enable counter capture on event. Upon a capture event, the counter value will be captured in RFETIMCAPT register.
|
RW |
0 |
|||||||||||||||||||||
6:5 |
COUNTERSOURCE |
Select event source for counter
|
RW |
0x0 |
|||||||||||||||||||||
4 |
CLEARCOUNTER |
Clear counter value in RFETIMCOUNTER to zero when this bit is set to 1. |
RW |
0 |
|||||||||||||||||||||
3 |
ENABLECOUNTER |
Enable 16-bit counter when set to 1. The counter will continue from its current value. |
RW |
0 |
|||||||||||||||||||||
2:1 |
TIMERSOURCE |
Select timer tick source for timer
|
RW |
0x0 |
|||||||||||||||||||||
0 |
ENABLETIMER |
Enable 16-bit timer. It will generate a timer interrupt after RFETIMPERIOD timer ticks. Note that the internal timer value is not readable from the RFE. If this is needed the counter should be used instead of the timer.
|
RW |
0 |
Address offset |
0x0000 00A0 |
||
Physical address |
0x4004 60A0 |
Instance |
RFC_RFE |
Description |
RFE Counter Increment Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
INCUNIT |
Programmable increment for the counter. For each counter event: RFETIMCOUNTER = RFETIMCOUNTER + (RFETIMINC.INCUNIT + 1). |
RW |
0x0000 |
Address offset |
0x0000 00A4 |
||
Physical address |
0x4004 60A4 |
Instance |
RFC_RFE |
Description |
RFE Timer/Counter Period Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PERIOD |
Configurable 16 bit period that can be used for either the timer or the counter. In timer context, when timer value reach the timer period (i.e. it expires) a TIMER_IRQ event will occur, and the timer will restart from zero (until the timer is manually disabled). In counter context, a COUNTER_IRQ event will occur when the counter is equal to or higher than the period value. |
RW |
0x0000 |
Address offset |
0x0000 00A8 |
||
Physical address |
0x4004 60A8 |
Instance |
RFC_RFE |
Description |
RFE Counter Value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VALUE |
16 bit value of counter |
RO |
0x0000 |
Address offset |
0x0000 00AC |
||
Physical address |
0x4004 60AC |
Instance |
RFC_RFE |
Description |
RFE Counter Capture Value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VALUE |
Captured value of counter |
RO |
0x0000 |
Address offset |
0x0000 00B0 |
||
Physical address |
0x4004 60B0 |
Instance |
RFC_RFE |
Description |
RFE Tracer Send Trigger Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
SEND |
Sends a command to the tracer |
RW |
0 |
Address offset |
0x0000 00B4 |
||
Physical address |
0x4004 60B4 |
Instance |
RFC_RFE |
Description |
RFE Tracer Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
BUSY |
Checks if the tracer is busy |
RO |
0 |
Address offset |
0x0000 00B8 |
||
Physical address |
0x4004 60B8 |
Instance |
RFC_RFE |
Description |
RFE Tracer Commmand Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
9:8 |
PARCNT |
Number of parameters |
RW |
0x0 |
||
7:0 |
PKTHDR |
Packet header |
RW |
0x00 |
Address offset |
0x0000 00BC |
||
Physical address |
0x4004 60BC |
Instance |
RFC_RFE |
Description |
RFE Tracer Command Parameter Register 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PAR0 |
Parameter 0 |
RW |
0x0000 |
Address offset |
0x0000 00C0 |
||
Physical address |
0x4004 60C0 |
Instance |
RFC_RFE |
Description |
RFE Tracer Command Parameter Register 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PAR1 |
Parameter 1 |
RW |
0x0000 |
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