Instance: AON
Component: AON_WUC
Base address: 0x60000000
Register Name |
Type |
Register Width (Bits) |
IR |
RO |
8 |
0 |
|
WO |
8 |
1 |
|
WO |
28 |
2 |
|
RO |
28 |
3 |
|
WO |
28 |
3 |
|
WO |
9 |
4 |
|
RO |
9 |
5 |
|
WO |
9 |
5 |
|
WO |
19 |
6 |
|
RO |
19 |
7 |
|
WO |
19 |
7 |
|
WO |
9 |
8 |
|
RO |
9 |
9 |
|
WO |
9 |
9 |
|
WO |
12 |
10 |
|
RO |
12 |
11 |
|
WO |
12 |
11 |
|
WO |
7 |
12 |
|
WO |
5 |
13 |
IR |
0 |
||
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
7 |
RES7 |
Reserved for future use |
RO |
0 |
||
6 |
RES6 |
Reserved for future use |
RO |
0 |
||
5 |
RES5 |
Reserved for future use |
RO |
0 |
||
4 |
RES4 |
Reserved for future use |
RO |
0 |
||
3 |
RES3 |
Reserved for future use |
RO |
0 |
||
2 |
RES2 |
Reserved for future use |
RO |
0 |
||
1 |
RES1 |
Reserved for future use |
RO |
0 |
||
0 |
BDACK |
Back door key acknowledge |
RO |
0 |
IR |
1 |
||
Description |
|||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
7 |
RES7 |
Reserved |
WO |
0 |
||
6 |
RES6 |
Reserved |
WO |
0 |
||
5 |
MCU_RESET_REQ |
Mcu reset request |
WO |
0 |
||
4 |
AUX_RESET_REQ |
Aux reset request |
WO |
0 |
||
3 |
BDRDY |
Backdoor ready. ( bddat is read after this signal rises) |
WO |
0 |
||
2 |
BDDAT |
Backdoor data. |
WO |
0 |
||
1 |
TOTALERASE |
Total erase request. |
WO |
0 |
||
0 |
CHIPERASE |
Chip erase request. |
WO |
0 |
IR |
2 |
||
Description |
This is an override value register for SYSCTRL. |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
27 |
WR_EVENT_O_VAL |
To be described |
WO |
0 |
||
26 |
DEBUG_EN_CLR_VAL |
To be described |
WO |
0 |
||
25 |
DEBUG_EN_SET_VAL |
To be described |
WO |
0 |
||
24 |
SCLK_HF_EN_O_VAL |
To be described |
WO |
0 |
||
23 |
SYSCTRLPD_O_VAL |
Override of syscctrlpd signal going to osctop. |
WO |
0 |
||
22 |
CLK_ADC_EN_O_VAL |
Override of clk_adc_en, adc clock |
WO |
0 |
||
21 |
CLK_CHP_EN_O_VAL |
Override of clk_chp_en, charge pump clock (used by adc) |
WO |
0 |
||
20 |
FORCE_RCOSC_HF_O_VAL |
Override of force_rcosc_hf |
WO |
0 |
||
19 |
CLK_DCDC_EN_O_VAL |
Override of clk_dcdc_en |
WO |
0 |
||
18 |
RESET_VDDSZ_EN_O_VAL |
Override of reset_vddsz to Flash charge pump (3.3V) |
WO |
0 |
||
17 |
PAD_RING_SLEEP_N_O_VAL |
Override of sleep_n signal going to padring |
WO |
0 |
||
16 |
SHUTDOWN_O_VAL |
Override of shutdown signal |
WO |
0 |
||
15 |
BYPASS_OSCDIG_VAL |
Override to bypass oscdig |
WO |
0 |
||
14 |
VDD_BOD_EN_O_VAL |
Override for vdd_bod_en |
WO |
0 |
||
13 |
VREF_SH_O_VAL |
Overrride for vref_sh for VDD Regulators (uldo sample hold curcuit) |
WO |
0 |
||
12 |
VREF_TRIM_EN_O_VAL |
Overrride for vref_trim_en for VDD Regulators |
WO |
0 |
||
11 |
DIG_LDO_PRESLEEP_O_VAL |
Overrride for dig_ldo_presleep for VDD Regulators |
WO |
0 |
||
10 |
VDD_LDO_EN_O_VAL |
Overrride for vdd_ldo_en for VDD Regulators |
WO |
0 |
||
9 |
SLEEP_MODE_EN_O_VAL |
Override of sleep_mode for VDDR Regulators |
WO |
0 |
||
8 |
DCDC_EN_O_VAL |
Override of dcdc_en for VDDR Regulators |
WO |
0 |
||
7 |
VDDR_REG_EN_O_VAL |
Override of vddr_reg_en for VDDR Regulators |
WO |
0 |
||
6 |
GBIAS_EN_O_VAL |
Override of gbias_en |
WO |
0 |
||
5 |
BGAP_EN_O_VAL |
Override of bgap_en |
WO |
0 |
||
4 |
VDDS_BOD_EN_O_VAL |
Override of vdds_bod_en |
WO |
0 |
||
3 |
VDD_OK_OR_O_VAL |
Override of VDD brown out detect override. |
WO |
0 |
||
2 |
VDDR_OK_OR_O_VAL |
Override of VDDR brown out detect override. |
WO |
0 |
||
1 |
VDDS_OK_OR_O_VAL |
Override of VDDS brown out detect override. |
WO |
0 |
||
0 |
CLK_LOSS_OR_N_O_VAL |
Overrride for clock_loss_or_n signal between sysctrl12 and sysctrl33. |
WO |
0 |
IR |
3 |
||
Description |
Sysctrl observation registers |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
27:7 |
SYSCTRL_NC |
Not connected |
RO |
0x00 0000 |
||
6 |
SYSCTRL_VDDR_OK_I |
Observation of the VDDR measurement result that was seen just prior to last recharge. |
RO |
0 |
||
5:2 |
SYSCTRL_FSMSTATE |
The state of the sysctrl12 state machine |
RO |
0x0 |
||
1 |
VDDR_OK |
VDDR_OK from VDDR Regulators |
RO |
0 |
||
0 |
VDDS_BOD_OK |
Brown out detect signal from VDDS |
RO |
0 |
IR |
3 |
||
Description |
This is the override enable register for SYSCTRL. |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
27 |
WR_EVENT_O_OR |
To be documented |
WO |
0 |
||
26 |
DEBUG_EN_CLR_OR |
To be documented |
WO |
0 |
||
25 |
DEBUG_EN_SET_OR |
To be documented |
WO |
0 |
||
24 |
SCLK_HF_EN_O_OR |
To be documented |
WO |
0 |
||
23 |
SYSCTRLPD_O_OR |
Override enable of syscctrlpd signal going to osctop. |
WO |
0 |
||
22 |
CLK_ADC_EN_O_OR |
Override enable of clk_adc_en, adc clock |
WO |
0 |
||
21 |
CLK_CHP_EN_O_OR |
Override enable of clk_chp_en, charge pump clock (used by adc) |
WO |
0 |
||
20 |
FORCE_RCOSC_HF_O_OR |
Override enable of force_rcosc_hf |
WO |
0 |
||
19 |
CLK_DCDC_EN_O_OR |
Override enable of clk_dcdc_en |
WO |
0 |
||
18 |
RESET_VDDSZ_EN_O_OR |
Override enable of reset_vddsz to Flash charge pump (3.3V) |
WO |
0 |
||
17 |
PAD_RING_SLEEP_N_O_OR |
Override enable of sleep_n signal going to padring |
WO |
0 |
||
16 |
SHUTDOWN_O_OR |
Override enable of shutdown signal |
WO |
0 |
||
15 |
BYPASS_OSCDIG_OR |
Override enable to bypass oscdig |
WO |
0 |
||
14 |
VDD_BOD_EN_O_OR |
Override enable for vdd_bod_en |
WO |
0 |
||
13 |
VREF_SH_O_OR |
Override enable for vref_sh for VDD Regulators (uldo sample hold curcuit) 0: Override disabled 1: Override enabled |
WO |
0 |
||
12 |
VREF_TRIM_EN_O_OR |
Override enable for vref_trim_en for VDD Regulators |
WO |
0 |
||
11 |
DIG_LDO_PRESLEEP_O_OR |
Override enable for dig_ldo_presleep for VDD Regulators |
WO |
0 |
||
10 |
VDD_LDO_EN_O_OR |
Override enable for vdd_ldo_en for VDD Regulators |
WO |
0 |
||
9 |
SLEEP_MODE_EN_O_OR |
Override enable of sleep_mode for VDDR Regulators |
WO |
0 |
||
8 |
DCDC_EN_O_OR |
Override enable of dcdc_en for VDDR Regulators |
WO |
0 |
||
7 |
VDDR_REG_EN_O_OR |
Override enable of vddr_reg_en for VDDR Regulators |
WO |
0 |
||
6 |
GBIAS_EN_O_OR |
Override enable of gbias_en |
WO |
0 |
||
5 |
BGAP_EN_O_OR |
Override enable of bgap_en |
WO |
0 |
||
4 |
VDDS_BOD_EN_O_OR |
Override enable of vdds_bod_en |
WO |
0 |
||
3 |
VDD_OK_OR_O_OR |
Override enable of VDD brown out detect override. |
WO |
0 |
||
2 |
VDDR_OK_OR_O_OR |
Override enable of VDDR brown out detect override. |
WO |
0 |
||
1 |
VDDS_OK_OR_O_OR |
Override enable of VDDS brown out detect override. |
WO |
0 |
||
0 |
CLK_LOSS_OR_N_O_OR |
Override enable for clock_loss_or_n signal between sysctrl12 and sysctrl33. |
WO |
0 |
IR |
4 |
||
Description |
This is an override value register for miscallenious signals. |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
8:7 |
MISC_NC |
Reserved for future use |
WO |
0x0 |
||
6 |
MCU_CLK_HF_FREQ_O_VAL |
Override of mcu_clk_hf_freq signal. High frequency indication towards prcm |
WO |
0 |
||
5 |
SCLK_LF_STOP_VAL |
1: Stop the LF clock to all aon modules. The signal controls EN of a clock gater at root of AON (LF CLOCK keeps running in OSCTOP). |
WO |
0 |
||
4 |
JTAG_DONOTRESET_WUCTAP_VAL |
1: Do not reset wuc tap when JTAG power domain is powered down. |
WO |
0 |
||
3 |
REPAIR_DONE_VAL |
Override of repair_done signal. |
WO |
0 |
||
2 |
GOTO_ACT_MODE_VAL |
0 or 1: Force goto_act signal high |
WO |
0 |
||
1 |
GOTO_PD_MODE_VAL |
0 or 1: Force goto_pd signal high |
WO |
0 |
||
0 |
JTAG_DONOTPOWERUP_VAL |
1: Prevent JTAG domain from being powered up from ICEMELTER |
WO |
0 |
IR |
5 |
||
Description |
Miscellanious observation registers |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
8:7 |
NC7 |
Not connected |
RO |
0x0 |
||
6 |
JTAG_PGOODIN |
Feed back from PGOODIN chain in JTAG domain. |
RO |
0 |
||
5 |
JTAG_PONIN |
Feed back from PONIN chain in JTAG domain. |
RO |
0 |
||
4:3 |
JTAG_STATE |
Observation of JTAG state |
RO |
0x0 |
||
2:0 |
PM_STATE |
The state of the WUC PM state machine. |
RO |
0x0 |
IR |
5 |
||
Description |
This is the override enable register for miscellaneous signals |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
8:7 |
MISC_NC7 |
Reserved for future use |
WO |
0x0 |
||
6 |
MCU_CLK_HF_FREQ_O_OR |
Override of mcu_clk_hf_freq signal. High frequency indication towards prcm |
WO |
0 |
||
5 |
MISC_NC5 |
1: Stop the LF clock to all aon modules. The signal controls EN of a clock gater at root of AON (LF CLOCK keeps running in OSCTOP). |
WO |
0 |
||
4 |
MISC_NC4 |
1: Do not reset wuc tap when JTAG power domain is powered down. |
WO |
0 |
||
3 |
REPAIR_DONE_OR |
Override of repair_done signal. |
WO |
0 |
||
2 |
GOTO_ACT_MODE_OR |
0 or 1: Force goto_act signal high |
WO |
0 |
||
1 |
GOTO_PD_MODE_OR |
0 or 1: Force goto_pd signal high |
WO |
0 |
||
0 |
MISC_NC0 |
1: Prevent JTAG domain from being powered up from ICEMELTER |
WO |
0 |
IR |
6 |
||
Description |
This is an override value register for MCU VD signals |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
18 |
MCU_LATCH_EN_VAL |
Override mcu_latch_en signal 1: Close register latches in AON domain for 0: Open register latches in AON domain |
WO |
0 |
||
17 |
MCU_RESET_N_O_VAL |
Override of mcu_reset_n signal 1: Foce mcu_reset_n to 1 ( preventing reset ) 0: Force mcu_reset_n to 0 ( forcing reset of all in mcu domain, including registers for aon) |
WO |
0 |
||
16 |
MCU_ISO_EN_VAL |
Override of isolation signal for muc power domain |
WO |
0 |
||
15 |
MCU_VDD_PON_VAL |
Override of weak switches for mcu power domain |
WO |
0 |
||
14 |
MCU_VDD_PGOOD_VAL |
Override of strong switches for mcu power domain |
WO |
0 |
||
13 |
MCU_SRAM_PGOOD_VAL |
Override of mcu_sram_pgood signal |
WO |
0 |
||
12 |
MCU_SRAM_PON_VAL |
Override of mcu_sram_pon signal |
WO |
0 |
||
11 |
MCU_SRAM_ERASE_VAL |
Override of mcu_sram_erase signal |
WO |
0 |
||
10:7 |
MCU_SRAM_AGOOD_VAL |
Override of mcu_sram_good[3:0] bus. |
WO |
0x0 |
||
6:3 |
MCU_SRAM_AON_VAL |
Override of mcu_sram_aon[3:0] bus. |
WO |
0x0 |
||
2 |
MCU_SRAM_ISO_VAL |
Override of mcu_sram_iso |
WO |
0 |
||
1 |
MCU_SRAM_RETGOOD_VAL |
Override of MCU SRAM RETGOOD signal. |
WO |
0 |
||
0 |
MCU_SRAM_RETON_VAL |
Override of MCU SRAM RETON signal. |
WO |
0 |
IR |
7 |
||
Description |
MCUVD observation registers |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
18:4 |
NC |
Not connected |
RO |
0x0000 |
||
3:0 |
MCU_VDDCTRL_STATE |
State of MCU Voltage domain controller |
RO |
0x0 |
IR |
7 |
||
Description |
This is the override enable register for MCU VD |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
18 |
MCU_LATCH_EN_OR |
Override enable for mcu_latch_en |
WO |
0 |
||
17 |
MCU_RESET_N_O_OR |
Override enable for mcu_reset_n_o |
WO |
0 |
||
16 |
MCU_ISO_EN_OR |
Override enable for mcu_iso_en |
WO |
0 |
||
15 |
MCU_VDD_PON_OR |
Override enable for mcu_vdd_pon |
WO |
0 |
||
14 |
MCU_VDD_PGOOD_OR |
Override enable for mcu_vdd_pgood |
WO |
0 |
||
13 |
MCU_SRAM_PGOOD_OR |
Override enable for mcu_sram_pgood |
WO |
0 |
||
12 |
MCU_SRAM_PON_OR |
Override enable for mcu_sram_pon |
WO |
0 |
||
11 |
MCU_SRAM_ERASE_OR |
Override enable for mcu_sram_erase |
WO |
0 |
||
10:7 |
MCU_SRAM_AGOOD_OR |
Override enable for mcu_sram_agood[3:0] |
WO |
0x0 |
||
6:3 |
MCU_SRAM_AON_OR |
Override enable for mcu_sram_aon[3:0] |
WO |
0x0 |
||
2 |
MCU_SRAM_ISO_OR |
Override enable for mcu_sram_iso |
WO |
0 |
||
1 |
MCU_SRAM_RETGOOD_OR |
Override enable for mcu_sram_retgood |
WO |
0 |
||
0 |
MCU_SRAM_RETON_OR |
Override enable for mcu_sram_reton |
WO |
0 |
IR |
8 |
||
Description |
This is an override value register for CLK signals |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
8:6 |
AUX_CLK_SRC_VAL |
Clock source for AUX domain |
WO |
0x0 |
||
5:3 |
MCU_CLK_SRC_VAL |
Clock source for mcu domain |
WO |
0x0 |
||
2 |
HF_CLK_O_VAL |
Override for single step of hf clock. |
WO |
0 |
||
1 |
MF_CLK_O_VAL |
Override for single step of mf clock. |
WO |
0 |
||
0 |
LF_CLK_O_VAL |
Override for single step of lf clock. |
WO |
0 |
IR |
9 |
||
Description |
CLK observation registers |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
8:6 |
AUX_CLK_STATUS |
Output of the state of the clock mux for AUX clock. |
RO |
0x0 |
||
5:3 |
MCU_CLK_STATUS |
Output of the state of the clock mux for MCU clock. |
RO |
0x0 |
||
2:0 |
CLK_NC |
Not connected |
RO |
0x0 |
IR |
9 |
||
Description |
This is the override enable register for CLK |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
8:6 |
AUX_CLK_SRC_OR |
Override enable for aux_clk_src |
WO |
0x0 |
||
5:3 |
MCU_CLK_SRC_OR |
Override enable for mcu_clk_src |
WO |
0x0 |
||
2 |
HF_CLK_O_OR |
Override enable for hf_clk_o |
WO |
0 |
||
1 |
MF_CLK_O_OR |
Override enable for mf_clk_o |
WO |
0 |
||
0 |
LF_CLK_O_OR |
Override enable for lf_clk_o |
WO |
0 |
IR |
10 |
||
Description |
This is an override value register for AUX VD signals |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
11 |
AUX_RESET_N_O_VAL |
Override of aux_reset_n signal |
0 |
|||
10 |
MCU_ISO_EN_VAL |
Override of isolation signal for muc power domain |
0 |
|||
9 |
MCU_VDD_PON_VAL |
Override of weak switches for mcu power domain |
0 |
|||
8 |
MCU_VDD_PGOOD_VAL |
Override of strong switches for mcu power domain |
0 |
|||
7 |
AUX_SRAM_PGOOD_VAL |
Override of aux_sram_pgood signal |
0 |
|||
6 |
AUX_SRAM_PON_VAL |
Override of aux_sram_pon signal |
0 |
|||
5 |
AUX_SRAM_ERASE_VAL |
Override of aux_sram_erase signal |
0 |
|||
4 |
AUX_SRAM_AGOOD_VAL |
Override of aux_sram_good. |
0 |
|||
3 |
AUX_SRAM_AON_VAL |
Override of aux_sram_aon |
0 |
|||
2 |
AUX_SRAM_ISO_VAL |
Override of aux_sram_iso |
0 |
|||
1 |
AUX_SRAM_RETGOOD_VAL |
Override of AUX SRAM RETGOOD signal. |
0 |
|||
0 |
AUX_SRAM_RETON_VAL |
Override of AUX SRAM RETON signal. |
0 |
IR |
11 |
||
Description |
AUX VD observation signals |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
11:10 |
AUX_VDCTRL10 |
Not connected |
0x0 |
|||
9 |
AUX_VDD_PGOODOUT |
Observation of aux vdd pgoodout |
0 |
|||
8 |
AUX_VDD_PONOUT |
Observation of aux_vdd_ponout |
0 |
|||
7:4 |
AUX_VDCTRL4 |
Not connected |
0x0 |
|||
3:0 |
AUX_VDDCTRL_STATE |
State of AUX Voltage domain controller |
0x0 |
IR |
11 |
||
Description |
This is the override enable register for AUX VD |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
11 |
AUX_RESET_N_O_OR |
Override enable for aux_reset_n_o |
0 |
|||
10 |
MCU_ISO_EN_OR |
Override enable for mcu_iso_en |
0 |
|||
9 |
MCU_VDD_PON_OR |
Override enable for mcu_vdd_pon |
0 |
|||
8 |
MCU_VDD_PGOOD_OR |
Override enable for mcu_vdd_pgood |
0 |
|||
7 |
AUX_SRAM_PGOOD_OR |
Override enable for aux_sram_pgood |
0 |
|||
6 |
AUX_SRAM_PON_OR |
Override enable for aux_sram_pon |
0 |
|||
5 |
AUX_SRAM_ERASE_OR |
Override enable for aux_sram_erase |
0 |
|||
4 |
AUX_SRAM_AGOOD_OR |
Override enable for aux_sram_agood |
0 |
|||
3 |
AUX_SRAM_AON_OR |
Override enable for aux_sram_aon |
0 |
|||
2 |
AUX_SRAM_ISO_OR |
Override enable for aux_sram_iso |
0 |
|||
1 |
AUX_SRAM_RETGOOD_OR |
Override enable for aux_sram_retgood |
0 |
|||
0 |
AUX_SRAM_RETON_OR |
Override enable for aux_sram_reton |
0 |
IR |
12 |
||
Description |
|||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
6 |
MCU_FORCEACTIVE_O |
1: MCU Domain is forced on. |
WO |
0 |
||
5 |
TMS_EC |
Set EC value for TMS pad (Default 0) |
WO |
0 |
||
4 |
TMS_SC |
Set SC value for TMS pad (Default 0) |
WO |
0 |
||
3 |
TMS_HC |
Set HC value for TMS pad (Default 1) |
WO |
0 |
||
2:0 |
TMS_STRIN |
Set STRIN value for the TMS pad (Default 0 which is adaptive drivestrength) |
WO |
0x0 |
IR |
13 |
||
Description |
|||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
4 |
WUC_PSCON_SPARE |
Reserved for DFT purposes. Needs more documentation.... |
WO |
0 |
||
3 |
WUC_PSCON_AONONLY_SEL |
Reserved for DFT purposes. Needs more documentation.... |
WO |
0 |
||
2 |
WUC_PSCON_TSTCLK_BYPASS |
Reserved for DFT purposes. Needs more documentation.... |
WO |
0 |
||
1 |
WUC_PSCON_BLOCKOUT |
Reserved for DFT purposes. Needs more documentation.... |
WO |
0 |
||
0 |
WUC_PSCON_MODE |
Reserved for DFT purposes. Needs more documentation.... |
WO |
0 |
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