Instance: CPU_SCS
Component: CPU_SCS
Base address: 0xe000e000
Cortex-M's System Control Space (SCS)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x0000 0001 |
0x0000 0004 |
0xE000 E004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 E008 |
|
RW |
32 |
0x0000 0004 |
0x0000 0010 |
0xE000 E010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0xE000 E014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0xE000 E018 |
|
RO |
32 |
0xC007 5300 |
0x0000 001C |
0xE000 E01C |
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0xE000 E100 |
|
RW |
32 |
0x0000 0000 |
0x0000 0104 |
0xE000 E104 |
|
RW |
32 |
0x0000 0000 |
0x0000 0180 |
0xE000 E180 |
|
RW |
32 |
0x0000 0000 |
0x0000 0184 |
0xE000 E184 |
|
RW |
32 |
0x0000 0000 |
0x0000 0200 |
0xE000 E200 |
|
RW |
32 |
0x0000 0000 |
0x0000 0204 |
0xE000 E204 |
|
RW |
32 |
0x0000 0000 |
0x0000 0280 |
0xE000 E280 |
|
RW |
32 |
0x0000 0000 |
0x0000 0284 |
0xE000 E284 |
|
RO |
32 |
0x0000 0000 |
0x0000 0300 |
0xE000 E300 |
|
RO |
32 |
0x0000 0000 |
0x0000 0304 |
0xE000 E304 |
|
RW |
32 |
0x0000 0000 |
0x0000 0400 |
0xE000 E400 |
|
RW |
32 |
0x0000 0000 |
0x0000 0404 |
0xE000 E404 |
|
RW |
32 |
0x0000 0000 |
0x0000 0408 |
0xE000 E408 |
|
RW |
32 |
0x0000 0000 |
0x0000 040C |
0xE000 E40C |
|
RW |
32 |
0x0000 0000 |
0x0000 0410 |
0xE000 E410 |
|
RW |
32 |
0x0000 0000 |
0x0000 0414 |
0xE000 E414 |
|
RW |
32 |
0x0000 0000 |
0x0000 0418 |
0xE000 E418 |
|
RW |
32 |
0x0000 0000 |
0x0000 041C |
0xE000 E41C |
|
RW |
32 |
0x0000 0000 |
0x0000 0420 |
0xE000 E420 |
|
RO |
32 |
0x412F C231 |
0x0000 0D00 |
0xE000 ED00 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D04 |
0xE000 ED04 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D08 |
0xE000 ED08 |
|
RW |
32 |
0xFA05 0000 |
0x0000 0D0C |
0xE000 ED0C |
|
RW |
32 |
0x0000 0000 |
0x0000 0D10 |
0xE000 ED10 |
|
RW |
32 |
0x0000 0200 |
0x0000 0D14 |
0xE000 ED14 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D18 |
0xE000 ED18 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D1C |
0xE000 ED1C |
|
RW |
32 |
0x0000 0000 |
0x0000 0D20 |
0xE000 ED20 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D24 |
0xE000 ED24 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D28 |
0xE000 ED28 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D2C |
0xE000 ED2C |
|
RW |
32 |
0x0000 0000 |
0x0000 0D30 |
0xE000 ED30 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D34 |
0xE000 ED34 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D38 |
0xE000 ED38 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D3C |
0xE000 ED3C |
|
RO |
32 |
0x0000 0030 |
0x0000 0D40 |
0xE000 ED40 |
|
RO |
32 |
0x0000 0200 |
0x0000 0D44 |
0xE000 ED44 |
|
RO |
32 |
0x0010 0000 |
0x0000 0D48 |
0xE000 ED48 |
|
RO |
32 |
0x0000 0000 |
0x0000 0D4C |
0xE000 ED4C |
|
RO |
32 |
0x0010 0030 |
0x0000 0D50 |
0xE000 ED50 |
|
RO |
32 |
0x0000 0000 |
0x0000 0D54 |
0xE000 ED54 |
|
RO |
32 |
0x0100 0000 |
0x0000 0D58 |
0xE000 ED58 |
|
RO |
32 |
0x0000 0000 |
0x0000 0D5C |
0xE000 ED5C |
|
RO |
32 |
0x0110 1110 |
0x0000 0D60 |
0xE000 ED60 |
|
RO |
32 |
0x0211 1000 |
0x0000 0D64 |
0xE000 ED64 |
|
RO |
32 |
0x2111 2231 |
0x0000 0D68 |
0xE000 ED68 |
|
RO |
32 |
0x0111 1110 |
0x0000 0D6C |
0xE000 ED6C |
|
RO |
32 |
0x0131 0132 |
0x0000 0D70 |
0xE000 ED70 |
|
RW |
32 |
0x0000 0000 |
0x0000 0D88 |
0xE000 ED88 |
|
RW |
32 |
0x0000 0000 |
0x0000 0DF0 |
0xE000 EDF0 |
|
WO |
32 |
0x0000 0000 |
0x0000 0DF4 |
0xE000 EDF4 |
|
RW |
32 |
0x0000 0000 |
0x0000 0DF8 |
0xE000 EDF8 |
|
RW |
32 |
0x0000 0000 |
0x0000 0DFC |
0xE000 EDFC |
|
WO |
32 |
0x0000 0000 |
0x0000 0F00 |
0xE000 EF00 |
Address offset |
0x0000 0004 |
||
Physical address |
0xE000 E004 |
Instance |
CPU_SCS |
Description |
Interrupt Control Type Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
RESERVED3 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 0000 |
||
2:0 |
INTLINESNUM |
Total number of interrupt lines in groups of 32. |
RO |
0x1 |
Address offset |
0x0000 0008 |
||
Physical address |
0xE000 E008 |
Instance |
CPU_SCS |
Description |
Auxiliary Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
RESERVED3 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0000 0000 |
||
2 |
DISFOLD |
Disables folding of IT instruction. |
RW |
0 |
||
1 |
DISDEFWBUF |
Disables write buffer use during default memory map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed. |
RW |
0 |
||
0 |
DISMCYCINT |
Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs. |
RW |
0 |
Address offset |
0x0000 0010 |
||
Physical address |
0xE000 E010 |
Instance |
CPU_SCS |
Description |
SysTick Control and Status Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:17 |
RESERVED17 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 |
||
16 |
COUNTFLAG |
Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, COUNTFLAG is not changed by the debugger read. |
RO |
0 |
||
15:3 |
RESERVED3 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 |
||
2 |
CLKSOURCE |
Clock source: |
RO |
1 |
||
1 |
TICKINT |
0: Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero. |
RW |
0 |
||
0 |
ENABLE |
Enable SysTick counter |
RW |
0 |
Address offset |
0x0000 0014 |
||
Physical address |
0xE000 E014 |
Instance |
CPU_SCS |
Description |
SysTick Reload Value Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
RESERVED24 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
||
23:0 |
RELOAD |
Value to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0. |
RW |
0x00 0000 |
Address offset |
0x0000 0018 |
||
Physical address |
0xE000 E018 |
Instance |
CPU_SCS |
Description |
SysTick Current Value Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
RESERVED24 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
||
23:0 |
CURRENT |
Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears STCSR.COUNTFLAG. |
RW |
0x00 0000 |
Address offset |
0x0000 001C |
||
Physical address |
0xE000 E01C |
Instance |
CPU_SCS |
Description |
SysTick Calibration Value Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
NOREF |
Reads as one. Indicates that no separate reference clock is provided. |
RO |
1 |
||
30 |
SKEW |
Reads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock. |
RO |
1 |
||
29:24 |
RESERVED24 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x00 |
||
23:0 |
TENMS |
An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. The value read is valid only when core clock is at 48MHz. |
RO |
0x07 5300 |
Address offset |
0x0000 0100 |
||
Physical address |
0xE000 E100 |
Instance |
CPU_SCS |
Description |
Irq 0 to 31 Set Enable Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
SETENA31 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
30 |
SETENA30 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
29 |
SETENA29 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
28 |
SETENA28 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
27 |
SETENA27 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
26 |
SETENA26 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
25 |
SETENA25 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
24 |
SETENA24 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
23 |
SETENA23 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
22 |
SETENA22 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
21 |
SETENA21 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
20 |
SETENA20 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
19 |
SETENA19 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
18 |
SETENA18 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
17 |
SETENA17 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
16 |
SETENA16 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
15 |
SETENA15 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
14 |
SETENA14 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
13 |
SETENA13 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
12 |
SETENA12 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
11 |
SETENA11 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
10 |
SETENA10 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
9 |
SETENA9 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
8 |
SETENA8 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
7 |
SETENA7 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
6 |
SETENA6 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
5 |
SETENA5 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
4 |
SETENA4 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
3 |
SETENA3 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
2 |
SETENA2 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
1 |
SETENA1 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
0 |
SETENA0 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
Address offset |
0x0000 0104 |
||
Physical address |
0xE000 E104 |
Instance |
CPU_SCS |
Description |
Irq 32 to 63 Set Enable Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0000 0000 |
||
1 |
SETENA33 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
0 |
SETENA32 |
Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
Address offset |
0x0000 0180 |
||
Physical address |
0xE000 E180 |
Instance |
CPU_SCS |
Description |
Irq 0 to 31 Clear Enable Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
CLRENA31 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
30 |
CLRENA30 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
29 |
CLRENA29 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
28 |
CLRENA28 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
27 |
CLRENA27 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
26 |
CLRENA26 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
25 |
CLRENA25 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
24 |
CLRENA24 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
23 |
CLRENA23 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
22 |
CLRENA22 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
21 |
CLRENA21 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
20 |
CLRENA20 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
19 |
CLRENA19 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
18 |
CLRENA18 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
17 |
CLRENA17 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
16 |
CLRENA16 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
15 |
CLRENA15 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
14 |
CLRENA14 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
13 |
CLRENA13 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
12 |
CLRENA12 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
11 |
CLRENA11 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
10 |
CLRENA10 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
9 |
CLRENA9 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
8 |
CLRENA8 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
7 |
CLRENA7 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
6 |
CLRENA6 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
5 |
CLRENA5 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
4 |
CLRENA4 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
3 |
CLRENA3 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
2 |
CLRENA2 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
1 |
CLRENA1 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
0 |
CLRENA0 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
Address offset |
0x0000 0184 |
||
Physical address |
0xE000 E184 |
Instance |
CPU_SCS |
Description |
Irq 32 to 63 Clear Enable Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0000 0000 |
||
1 |
CLRENA33 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
||
0 |
CLRENA32 |
Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. |
RW |
0 |
Address offset |
0x0000 0200 |
||
Physical address |
0xE000 E200 |
Instance |
CPU_SCS |
Description |
Irq 0 to 31 Set Pending Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
SETPEND31 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
30 |
SETPEND30 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
29 |
SETPEND29 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
28 |
SETPEND28 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
27 |
SETPEND27 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
26 |
SETPEND26 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
25 |
SETPEND25 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
24 |
SETPEND24 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
23 |
SETPEND23 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
22 |
SETPEND22 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
21 |
SETPEND21 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
20 |
SETPEND20 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
19 |
SETPEND19 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
18 |
SETPEND18 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
17 |
SETPEND17 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
16 |
SETPEND16 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
15 |
SETPEND15 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
14 |
SETPEND14 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
13 |
SETPEND13 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
12 |
SETPEND12 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
11 |
SETPEND11 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
10 |
SETPEND10 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
9 |
SETPEND9 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
8 |
SETPEND8 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
7 |
SETPEND7 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
6 |
SETPEND6 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
5 |
SETPEND5 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
4 |
SETPEND4 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
3 |
SETPEND3 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
2 |
SETPEND2 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
1 |
SETPEND1 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
0 |
SETPEND0 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. |
RW |
0 |
Address offset |
0x0000 0204 |
||
Physical address |
0xE000 E204 |
Instance |
CPU_SCS |
Description |
Irq 32 to 63 Set Pending Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0000 0000 |
||
1 |
SETPEND33 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
0 |
SETPEND32 |
Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. |
RW |
0 |
Address offset |
0x0000 0280 |
||
Physical address |
0xE000 E280 |
Instance |
CPU_SCS |
Description |
Irq 0 to 31 Clear Pending Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
CLRPEND31 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
30 |
CLRPEND30 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
29 |
CLRPEND29 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
28 |
CLRPEND28 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
27 |
CLRPEND27 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
26 |
CLRPEND26 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
25 |
CLRPEND25 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
24 |
CLRPEND24 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
23 |
CLRPEND23 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
22 |
CLRPEND22 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
21 |
CLRPEND21 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
20 |
CLRPEND20 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
19 |
CLRPEND19 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
18 |
CLRPEND18 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
17 |
CLRPEND17 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
16 |
CLRPEND16 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
15 |
CLRPEND15 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
14 |
CLRPEND14 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
13 |
CLRPEND13 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
12 |
CLRPEND12 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
11 |
CLRPEND11 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
10 |
CLRPEND10 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
9 |
CLRPEND9 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
8 |
CLRPEND8 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
7 |
CLRPEND7 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
6 |
CLRPEND6 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
5 |
CLRPEND5 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
4 |
CLRPEND4 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
3 |
CLRPEND3 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
2 |
CLRPEND2 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
1 |
CLRPEND1 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
0 |
CLRPEND0 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. |
RW |
0 |
Address offset |
0x0000 0284 |
||
Physical address |
0xE000 E284 |
Instance |
CPU_SCS |
Description |
Irq 32 to 63 Clear Pending Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0000 0000 |
||
1 |
CLRPEND33 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state. |
RW |
0 |
||
0 |
CLRPEND32 |
Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. |
RW |
0 |
Address offset |
0x0000 0300 |
||
Physical address |
0xE000 E300 |
Instance |
CPU_SCS |
Description |
Irq 0 to 31 Active Bit Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
ACTIVE31 |
Reading 0 from this bit implies that interrupt line 31 is not active. Reading 1 from this bit implies that the interrupt line 31 is active (See EVENT:CPUIRQSEL31.EV for details). |
RO |
0 |
||
30 |
ACTIVE30 |
Reading 0 from this bit implies that interrupt line 30 is not active. Reading 1 from this bit implies that the interrupt line 30 is active (See EVENT:CPUIRQSEL30.EV for details). |
RO |
0 |
||
29 |
ACTIVE29 |
Reading 0 from this bit implies that interrupt line 29 is not active. Reading 1 from this bit implies that the interrupt line 29 is active (See EVENT:CPUIRQSEL29.EV for details). |
RO |
0 |
||
28 |
ACTIVE28 |
Reading 0 from this bit implies that interrupt line 28 is not active. Reading 1 from this bit implies that the interrupt line 28 is active (See EVENT:CPUIRQSEL28.EV for details). |
RO |
0 |
||
27 |
ACTIVE27 |
Reading 0 from this bit implies that interrupt line 27 is not active. Reading 1 from this bit implies that the interrupt line 27 is active (See EVENT:CPUIRQSEL27.EV for details). |
RO |
0 |
||
26 |
ACTIVE26 |
Reading 0 from this bit implies that interrupt line 26 is not active. Reading 1 from this bit implies that the interrupt line 26 is active (See EVENT:CPUIRQSEL26.EV for details). |
RO |
0 |
||
25 |
ACTIVE25 |
Reading 0 from this bit implies that interrupt line 25 is not active. Reading 1 from this bit implies that the interrupt line 25 is active (See EVENT:CPUIRQSEL25.EV for details). |
RO |
0 |
||
24 |
ACTIVE24 |
Reading 0 from this bit implies that interrupt line 24 is not active. Reading 1 from this bit implies that the interrupt line 24 is active (See EVENT:CPUIRQSEL24.EV for details). |
RO |
0 |
||
23 |
ACTIVE23 |
Reading 0 from this bit implies that interrupt line 23 is not active. Reading 1 from this bit implies that the interrupt line 23 is active (See EVENT:CPUIRQSEL23.EV for details). |
RO |
0 |
||
22 |
ACTIVE22 |
Reading 0 from this bit implies that interrupt line 22 is not active. Reading 1 from this bit implies that the interrupt line 22 is active (See EVENT:CPUIRQSEL22.EV for details). |
RO |
0 |
||
21 |
ACTIVE21 |
Reading 0 from this bit implies that interrupt line 21 is not active. Reading 1 from this bit implies that the interrupt line 21 is active (See EVENT:CPUIRQSEL21.EV for details). |
RO |
0 |
||
20 |
ACTIVE20 |
Reading 0 from this bit implies that interrupt line 20 is not active. Reading 1 from this bit implies that the interrupt line 20 is active (See EVENT:CPUIRQSEL20.EV for details). |
RO |
0 |
||
19 |
ACTIVE19 |
Reading 0 from this bit implies that interrupt line 19 is not active. Reading 1 from this bit implies that the interrupt line 19 is active (See EVENT:CPUIRQSEL19.EV for details). |
RO |
0 |
||
18 |
ACTIVE18 |
Reading 0 from this bit implies that interrupt line 18 is not active. Reading 1 from this bit implies that the interrupt line 18 is active (See EVENT:CPUIRQSEL18.EV for details). |
RO |
0 |
||
17 |
ACTIVE17 |
Reading 0 from this bit implies that interrupt line 17 is not active. Reading 1 from this bit implies that the interrupt line 17 is active (See EVENT:CPUIRQSEL17.EV for details). |
RO |
0 |
||
16 |
ACTIVE16 |
Reading 0 from this bit implies that interrupt line 16 is not active. Reading 1 from this bit implies that the interrupt line 16 is active (See EVENT:CPUIRQSEL16.EV for details). |
RO |
0 |
||
15 |
ACTIVE15 |
Reading 0 from this bit implies that interrupt line 15 is not active. Reading 1 from this bit implies that the interrupt line 15 is active (See EVENT:CPUIRQSEL15.EV for details). |
RO |
0 |
||
14 |
ACTIVE14 |
Reading 0 from this bit implies that interrupt line 14 is not active. Reading 1 from this bit implies that the interrupt line 14 is active (See EVENT:CPUIRQSEL14.EV for details). |
RO |
0 |
||
13 |
ACTIVE13 |
Reading 0 from this bit implies that interrupt line 13 is not active. Reading 1 from this bit implies that the interrupt line 13 is active (See EVENT:CPUIRQSEL13.EV for details). |
RO |
0 |
||
12 |
ACTIVE12 |
Reading 0 from this bit implies that interrupt line 12 is not active. Reading 1 from this bit implies that the interrupt line 12 is active (See EVENT:CPUIRQSEL12.EV for details). |
RO |
0 |
||
11 |
ACTIVE11 |
Reading 0 from this bit implies that interrupt line 11 is not active. Reading 1 from this bit implies that the interrupt line 11 is active (See EVENT:CPUIRQSEL11.EV for details). |
RO |
0 |
||
10 |
ACTIVE10 |
Reading 0 from this bit implies that interrupt line 10 is not active. Reading 1 from this bit implies that the interrupt line 10 is active (See EVENT:CPUIRQSEL10.EV for details). |
RO |
0 |
||
9 |
ACTIVE9 |
Reading 0 from this bit implies that interrupt line 9 is not active. Reading 1 from this bit implies that the interrupt line 9 is active (See EVENT:CPUIRQSEL9.EV for details). |
RO |
0 |
||
8 |
ACTIVE8 |
Reading 0 from this bit implies that interrupt line 8 is not active. Reading 1 from this bit implies that the interrupt line 8 is active (See EVENT:CPUIRQSEL8.EV for details). |
RO |
0 |
||
7 |
ACTIVE7 |
Reading 0 from this bit implies that interrupt line 7 is not active. Reading 1 from this bit implies that the interrupt line 7 is active (See EVENT:CPUIRQSEL7.EV for details). |
RO |
0 |
||
6 |
ACTIVE6 |
Reading 0 from this bit implies that interrupt line 6 is not active. Reading 1 from this bit implies that the interrupt line 6 is active (See EVENT:CPUIRQSEL6.EV for details). |
RO |
0 |
||
5 |
ACTIVE5 |
Reading 0 from this bit implies that interrupt line 5 is not active. Reading 1 from this bit implies that the interrupt line 5 is active (See EVENT:CPUIRQSEL5.EV for details). |
RO |
0 |
||
4 |
ACTIVE4 |
Reading 0 from this bit implies that interrupt line 4 is not active. Reading 1 from this bit implies that the interrupt line 4 is active (See EVENT:CPUIRQSEL4.EV for details). |
RO |
0 |
||
3 |
ACTIVE3 |
Reading 0 from this bit implies that interrupt line 3 is not active. Reading 1 from this bit implies that the interrupt line 3 is active (See EVENT:CPUIRQSEL3.EV for details). |
RO |
0 |
||
2 |
ACTIVE2 |
Reading 0 from this bit implies that interrupt line 2 is not active. Reading 1 from this bit implies that the interrupt line 2 is active (See EVENT:CPUIRQSEL2.EV for details). |
RO |
0 |
||
1 |
ACTIVE1 |
Reading 0 from this bit implies that interrupt line 1 is not active. Reading 1 from this bit implies that the interrupt line 1 is active (See EVENT:CPUIRQSEL1.EV for details). |
RO |
0 |
||
0 |
ACTIVE0 |
Reading 0 from this bit implies that interrupt line 0 is not active. Reading 1 from this bit implies that the interrupt line 0 is active (See EVENT:CPUIRQSEL0.EV for details). |
RO |
0 |
Address offset |
0x0000 0304 |
||
Physical address |
0xE000 E304 |
Instance |
CPU_SCS |
Description |
Irq 32 to 63 Active Bit Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 0000 |
||
1 |
ACTIVE33 |
Reading 0 from this bit implies that interrupt line 33 is not active. Reading 1 from this bit implies that the interrupt line 33 is active (See EVENT:CPUIRQSEL33.EV for details). |
RO |
0 |
||
0 |
ACTIVE32 |
Reading 0 from this bit implies that interrupt line 32 is not active. Reading 1 from this bit implies that the interrupt line 32 is active (See EVENT:CPUIRQSEL32.EV for details). |
RO |
0 |
Address offset |
0x0000 0400 |
||
Physical address |
0xE000 E400 |
Instance |
CPU_SCS |
Description |
Irq 0 to 3 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_3 |
Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). |
RW |
0x00 |
||
23:16 |
PRI_2 |
Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). |
RW |
0x00 |
||
15:8 |
PRI_1 |
Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). |
RW |
0x00 |
||
7:0 |
PRI_0 |
Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). |
RW |
0x00 |
Address offset |
0x0000 0404 |
||
Physical address |
0xE000 E404 |
Instance |
CPU_SCS |
Description |
Irq 4 to 7 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_7 |
Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). |
RW |
0x00 |
||
23:16 |
PRI_6 |
Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). |
RW |
0x00 |
||
15:8 |
PRI_5 |
Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). |
RW |
0x00 |
||
7:0 |
PRI_4 |
Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). |
RW |
0x00 |
Address offset |
0x0000 0408 |
||
Physical address |
0xE000 E408 |
Instance |
CPU_SCS |
Description |
Irq 8 to 11 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_11 |
Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). |
RW |
0x00 |
||
23:16 |
PRI_10 |
Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). |
RW |
0x00 |
||
15:8 |
PRI_9 |
Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). |
RW |
0x00 |
||
7:0 |
PRI_8 |
Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). |
RW |
0x00 |
Address offset |
0x0000 040C |
||
Physical address |
0xE000 E40C |
Instance |
CPU_SCS |
Description |
Irq 12 to 15 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_15 |
Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). |
RW |
0x00 |
||
23:16 |
PRI_14 |
Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). |
RW |
0x00 |
||
15:8 |
PRI_13 |
Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). |
RW |
0x00 |
||
7:0 |
PRI_12 |
Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). |
RW |
0x00 |
Address offset |
0x0000 0410 |
||
Physical address |
0xE000 E410 |
Instance |
CPU_SCS |
Description |
Irq 16 to 19 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_19 |
Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). |
RW |
0x00 |
||
23:16 |
PRI_18 |
Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). |
RW |
0x00 |
||
15:8 |
PRI_17 |
Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). |
RW |
0x00 |
||
7:0 |
PRI_16 |
Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). |
RW |
0x00 |
Address offset |
0x0000 0414 |
||
Physical address |
0xE000 E414 |
Instance |
CPU_SCS |
Description |
Irq 20 to 23 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_23 |
Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). |
RW |
0x00 |
||
23:16 |
PRI_22 |
Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). |
RW |
0x00 |
||
15:8 |
PRI_21 |
Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). |
RW |
0x00 |
||
7:0 |
PRI_20 |
Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). |
RW |
0x00 |
Address offset |
0x0000 0418 |
||
Physical address |
0xE000 E418 |
Instance |
CPU_SCS |
Description |
Irq 24 to 27 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_27 |
Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). |
RW |
0x00 |
||
23:16 |
PRI_26 |
Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). |
RW |
0x00 |
||
15:8 |
PRI_25 |
Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). |
RW |
0x00 |
||
7:0 |
PRI_24 |
Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). |
RW |
0x00 |
Address offset |
0x0000 041C |
||
Physical address |
0xE000 E41C |
Instance |
CPU_SCS |
Description |
Irq 28 to 31 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_31 |
Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). |
RW |
0x00 |
||
23:16 |
PRI_30 |
Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). |
RW |
0x00 |
||
15:8 |
PRI_29 |
Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). |
RW |
0x00 |
||
7:0 |
PRI_28 |
Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). |
RW |
0x00 |
Address offset |
0x0000 0420 |
||
Physical address |
0xE000 E420 |
Instance |
CPU_SCS |
Description |
Irq 32 to 35 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
RESERVED16 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0000 |
||
15:8 |
PRI_33 |
Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). |
RW |
0x00 |
||
7:0 |
PRI_32 |
Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). |
RW |
0x00 |
Address offset |
0x0000 0D00 |
||
Physical address |
0xE000 ED00 |
Instance |
CPU_SCS |
Description |
CPUID Base Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
IMPLEMENTER |
Implementor code. |
RO |
0x41 |
||
23:20 |
VARIANT |
Implementation defined variant number. |
RO |
0x2 |
||
19:16 |
CONSTANT |
Reads as 0xF |
RO |
0xF |
||
15:4 |
PARTNO |
Number of processor within family. |
RO |
0xC23 |
||
3:0 |
REVISION |
Implementation defined revision number. |
RO |
0x1 |
Address offset |
0x0000 0D04 |
||
Physical address |
0xE000 ED04 |
Instance |
CPU_SCS |
Description |
Interrupt Control State Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
NMIPENDSET |
Set pending NMI bit. Setting this bit pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers. |
RW |
0 |
||
30:29 |
RESERVED29 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
28 |
PENDSVSET |
Set pending pendSV bit. |
RW |
0 |
||
27 |
PENDSVCLR |
Clear pending pendSV bit |
WO |
0 |
||
26 |
PENDSTSET |
Set a pending SysTick bit. |
RW |
0 |
||
25 |
PENDSTCLR |
Clear pending SysTick bit |
WO |
0 |
||
24 |
RESERVED24 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
||
23 |
ISRPREEMPT |
This field can only be used at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, the interrupt is serviced. |
RO |
0 |
||
22 |
ISRPENDING |
Interrupt pending flag. Excludes NMI and faults. |
RO |
0 |
||
21:18 |
RESERVED18 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 |
||
17:12 |
VECTPENDING |
Pending ISR number field. This field contains the interrupt number of the highest priority pending ISR. |
RO |
0x00 |
||
11 |
RETTOBASE |
Indicates whether there are preempted active exceptions: |
RO |
0 |
||
10:9 |
RESERVED9 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 |
||
8:0 |
VECTACTIVE |
Active ISR number field. Reset clears this field. |
RO |
0x000 |
Address offset |
0x0000 0D08 |
||
Physical address |
0xE000 ED08 |
Instance |
CPU_SCS |
Description |
Vector Table Offset Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:30 |
RESERVED30 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
29:7 |
TBLOFF |
Bits 29 down to 7 of the vector table base offset. |
RW |
0x00 0000 |
||
6:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
Address offset |
0x0000 0D0C |
||
Physical address |
0xE000 ED0C |
Instance |
CPU_SCS |
Description |
Application Interrupt/Reset Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:16 |
VECTKEY |
Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05. |
RW |
0xFA05 |
|||||||||||||
15 |
ENDIANESS |
Data endianness bit
|
RO |
0 |
|||||||||||||
14:11 |
RESERVED11 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 |
|||||||||||||
10:8 |
PRIGROUP |
Interrupt priority grouping field. This field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices. |
RW |
0x0 |
|||||||||||||
7:3 |
RESERVED3 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
|||||||||||||
2 |
SYSRESETREQ |
Requests a warm reset. Setting this bit does not prevent Halting Debug from running. |
WO |
0 |
|||||||||||||
1 |
VECTCLRACTIVE |
Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. This bit is for returning to a known state during debug. The bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set. |
WO |
0 |
|||||||||||||
0 |
VECTRESET |
System Reset bit. Resets the system, with the exception of debug components. This bit is reserved for debug use and can be written to 1 only when the core is halted. The bit self-clears. Writing this bit to 1 while core is not halted may result in unpredictable behavior. |
WO |
0 |
Address offset |
0x0000 0D10 |
||
Physical address |
0xE000 ED10 |
Instance |
CPU_SCS |
Description |
System Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:5 |
RESERVED5 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x000 0000 |
|||||||||||||
4 |
SEVONPEND |
Send Event on Pending bit: |
RW |
0 |
|||||||||||||
3 |
RESERVED3 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
|||||||||||||
2 |
SLEEPDEEP |
Controls whether the processor uses sleep or deep sleep as its low power mode
|
RW |
0 |
|||||||||||||
1 |
SLEEPONEXIT |
Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application. |
RW |
0 |
|||||||||||||
0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
Address offset |
0x0000 0D14 |
||
Physical address |
0xE000 ED14 |
Instance |
CPU_SCS |
Description |
Configuration Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:10 |
RESERVED10 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 0000 |
||
9 |
STKALIGN |
Stack alignment bit. |
RW |
1 |
||
8 |
BFHFNMIGN |
Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the HardFault, NMI, and FAULTMASK escalated handlers: |
RW |
0 |
||
7:5 |
RESERVED5 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
4 |
DIV_0_TRP |
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: |
RW |
0 |
||
3 |
UNALIGN_TRP |
Enables unaligned access traps: |
RW |
0 |
||
2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
1 |
USERSETMPEND |
Enables unprivileged software access to STIR: |
RW |
0 |
||
0 |
NONBASETHREDENA |
Indicates how the processor enters Thread mode: |
RW |
0 |
Address offset |
0x0000 0D18 |
||
Physical address |
0xE000 ED18 |
Instance |
CPU_SCS |
Description |
System Handlers 4-7 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 |
||
23:16 |
PRI_6 |
Priority of system handler 6. UsageFault |
RW |
0x00 |
||
15:8 |
PRI_5 |
Priority of system handler 5: BusFault |
RW |
0x00 |
||
7:0 |
PRI_4 |
Priority of system handler 4: MemManage |
RW |
0x00 |
Address offset |
0x0000 0D1C |
||
Physical address |
0xE000 ED1C |
Instance |
CPU_SCS |
Description |
System Handlers 8-11 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_11 |
Priority of system handler 11. SVCall |
RW |
0x00 |
||
23:0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 0000 |
Address offset |
0x0000 0D20 |
||
Physical address |
0xE000 ED20 |
Instance |
CPU_SCS |
Description |
System Handlers 12-15 Priority Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
PRI_15 |
Priority of system handler 15. SysTick exception |
RW |
0x00 |
||
23:16 |
PRI_14 |
Priority of system handler 14. Pend SV |
RW |
0x00 |
||
15:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 |
||
7:0 |
PRI_12 |
Priority of system handler 12. Debug Monitor |
RW |
0x00 |
Address offset |
0x0000 0D24 |
||
Physical address |
0xE000 ED24 |
Instance |
CPU_SCS |
Description |
System Handler Control and State Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:19 |
RESERVED19 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0000 |
|||||||||||||
18 |
USGFAULTENA |
Usage fault system handler enable
|
RW |
0 |
|||||||||||||
17 |
BUSFAULTENA |
Bus fault system handler enable
|
RW |
0 |
|||||||||||||
16 |
MEMFAULTENA |
MemManage fault system handler enable
|
RW |
0 |
|||||||||||||
15 |
SVCALLPENDED |
SVCall pending
|
RO |
0 |
|||||||||||||
14 |
BUSFAULTPENDED |
BusFault pending
|
RO |
0 |
|||||||||||||
13 |
MEMFAULTPENDED |
MemManage exception pending
|
RO |
0 |
|||||||||||||
12 |
USGFAULTPENDED |
Usage fault pending
|
RO |
0 |
|||||||||||||
11 |
SYSTICKACT |
SysTick active flag.
|
RO |
0 |
|||||||||||||
10 |
PENDSVACT |
PendSV active |
RO |
0 |
|||||||||||||
9 |
RESERVED9 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
|||||||||||||
8 |
MONITORACT |
Debug monitor active
|
RO |
0 |
|||||||||||||
7 |
SVCALLACT |
SVCall active
|
RO |
0 |
|||||||||||||
6:4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 |
|||||||||||||
3 |
USGFAULTACT |
UsageFault exception active
|
RO |
0 |
|||||||||||||
2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
|||||||||||||
1 |
BUSFAULTACT |
BusFault exception active
|
RO |
0 |
|||||||||||||
0 |
MEMFAULTACT |
MemManage exception active
|
RO |
0 |
Address offset |
0x0000 0D28 |
||
Physical address |
0xE000 ED28 |
Instance |
CPU_SCS |
Description |
Configurable Fault Status Registers |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:26 |
RESERVED26 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
||
25 |
DIVBYZERO |
When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. |
RW |
0 |
||
24 |
UNALIGNED |
When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. |
RW |
0 |
||
23:20 |
RESERVED20 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
19 |
NOCP |
Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions. |
RW |
0 |
||
18 |
INVPC |
Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC. |
RW |
0 |
||
17 |
INVSTATE |
Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state. |
RW |
0 |
||
16 |
UNDEFINSTR |
This bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction. |
RW |
0 |
||
15 |
BFARVALID |
This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten. |
RW |
0 |
||
14:13 |
RESERVED13 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
12 |
STKERR |
Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written. |
RW |
0 |
||
11 |
UNSTKERR |
Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written. |
RW |
0 |
||
10 |
IMPRECISERR |
Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written. |
RW |
0 |
||
9 |
PRECISERR |
Precise data bus error return. |
RW |
0 |
||
8 |
IBUSERR |
Instruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written. |
RW |
0 |
||
7 |
MMARVALID |
Memory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten. |
RW |
0 |
||
6:5 |
RESERVED5 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
4 |
MSTKERR |
Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written. |
RW |
0 |
||
3 |
MUNSTKERR |
Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written. |
RW |
0 |
||
2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
1 |
DACCVIOL |
Data access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access. |
RW |
0 |
||
0 |
IACCVIOL |
Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written. |
RW |
0 |
Address offset |
0x0000 0D2C |
||
Physical address |
0xE000 ED2C |
Instance |
CPU_SCS |
Description |
Hard Fault Status Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
DEBUGEVT |
This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated. |
RW |
0 |
||
30 |
FORCED |
Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause. |
RW |
0 |
||
29:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x000 0000 |
||
1 |
VECTTBL |
This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. |
RW |
0 |
||
0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
Address offset |
0x0000 0D30 |
||
Physical address |
0xE000 ED30 |
Instance |
CPU_SCS |
Description |
Debug Fault Status Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
RESERVED5 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x000 0000 |
||
4 |
EXTERNAL |
External debug request flag. The processor stops on next instruction boundary. |
RW |
0 |
||
3 |
VCATCH |
Vector catch flag. When this flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault. |
RW |
0 |
||
2 |
DWTTRAP |
Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction. |
RW |
0 |
||
1 |
BKPT |
BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction. |
RW |
0 |
||
0 |
HALTED |
Halt request flag. The processor is halted on the next instruction. |
RW |
0 |
Address offset |
0x0000 0D34 |
||
Physical address |
0xE000 ED34 |
Instance |
CPU_SCS |
Description |
Mem Manage Fault Address Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
ADDRESS |
Mem Manage fault address field. |
RW |
0x0000 0000 |
Address offset |
0x0000 0D38 |
||
Physical address |
0xE000 ED38 |
Instance |
CPU_SCS |
Description |
Bus Fault Address Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
ADDRESS |
Bus fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. |
RW |
0x0000 0000 |
Address offset |
0x0000 0D3C |
||
Physical address |
0xE000 ED3C |
Instance |
CPU_SCS |
Description |
Auxiliary Fault Status Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
IMPDEF |
Implementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0 |
RW |
0x0000 0000 |
Address offset |
0x0000 0D40 |
||
Physical address |
0xE000 ED40 |
Instance |
CPU_SCS |
Description |
Processor Feature Register 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
RESERVED8 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x00 0000 |
||
7:4 |
STATE1 |
State1 (T-bit == 1) |
RO |
0x3 |
||
3:0 |
STATE0 |
State0 (T-bit == 0) |
RO |
0x0 |
Address offset |
0x0000 0D44 |
||
Physical address |
0xE000 ED44 |
Instance |
CPU_SCS |
Description |
Processor Feature Register 1 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:12 |
RESERVED12 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 0000 |
||
11:8 |
MICROCONTROLLER_PROGRAMMERS_MODEL |
Microcontroller programmer's model |
RO |
0x2 |
||
7:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x00 |
Address offset |
0x0000 0D48 |
||
Physical address |
0xE000 ED48 |
Instance |
CPU_SCS |
Description |
Debug Feature Register 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
RESERVED24 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x00 |
||
23:20 |
MICROCONTROLLER_DEBUG_MODEL |
Microcontroller Debug Model - memory mapped |
RO |
0x1 |
||
19:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 0000 |
Address offset |
0x0000 0D4C |
||
Physical address |
0xE000 ED4C |
Instance |
CPU_SCS |
Description |
Auxiliary Feature Register0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 0000 |
Address offset |
0x0000 0D50 |
||
Physical address |
0xE000 ED50 |
Instance |
CPU_SCS |
Description |
Memory Model Feature Register 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0010 0030 |
Address offset |
0x0000 0D54 |
||
Physical address |
0xE000 ED54 |
Instance |
CPU_SCS |
Description |
Memory Model Feature Register 1 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 0000 |
Address offset |
0x0000 0D58 |
||
Physical address |
0xE000 ED58 |
Instance |
CPU_SCS |
Description |
Memory Model Feature Register 2 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:25 |
RESERVED28 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x00 |
||
24 |
WAIT_FOR_INTERRUPT_STALLING |
wait for interrupt stalling |
RO |
1 |
||
23:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x00 0000 |
Address offset |
0x0000 0D5C |
||
Physical address |
0xE000 ED5C |
Instance |
CPU_SCS |
Description |
Memory Model Feature Register3 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 0000 |
Address offset |
0x0000 0D60 |
||
Physical address |
0xE000 ED60 |
Instance |
CPU_SCS |
Description |
ISA Feature Register 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0110 1110 |
Address offset |
0x0000 0D64 |
||
Physical address |
0xE000 ED64 |
Instance |
CPU_SCS |
Description |
ISA Feature Register 1 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0211 1000 |
Address offset |
0x0000 0D68 |
||
Physical address |
0xE000 ED68 |
Instance |
CPU_SCS |
Description |
ISA Feature Register 2 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x2111 2231 |
Address offset |
0x0000 0D6C |
||
Physical address |
0xE000 ED6C |
Instance |
CPU_SCS |
Description |
ISA Feature Register 3 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0111 1110 |
Address offset |
0x0000 0D70 |
||
Physical address |
0xE000 ED70 |
Instance |
CPU_SCS |
Description |
ISA Feature Register 4 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0131 0132 |
Address offset |
0x0000 0D88 |
||
Physical address |
0xE000 ED88 |
Instance |
CPU_SCS |
Description |
Coprocessor Access Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0000 0000 |
Address offset |
0x0000 0DF0 |
||
Physical address |
0xE000 EDF0 |
Instance |
CPU_SCS |
Description |
Debug Halting Control and Status Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:26 |
RESERVED26 |
Software should not rely on the value of a reserved. |
RW |
0x00 |
||
25 |
S_RESET_ST |
Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still). |
RW |
0 |
||
24 |
S_RETIRE_ST |
Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch. |
RW |
0 |
||
23:20 |
RESERVED20 |
Software should not rely on the value of a reserved. |
RW |
0x0 |
||
19 |
S_LOCKUP |
Reads as one if the core is running (not halted) and a lockup condition is present. |
RW |
0 |
||
18 |
S_SLEEP |
Indicates that the core is sleeping (WFI, WFE, or SLEEP-ON-EXIT). Must use C_HALT to gain control or wait for interrupt to wake-up. |
RW |
0 |
||
17 |
S_HALT |
The core is in debug state when this bit is set. |
RW |
0 |
||
16 |
S_REGRDY |
Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete. |
RW |
0 |
||
15:6 |
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x000 |
||
5 |
C_SNAPSTALL |
If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE_ST can detect core stalls on load/store operations. |
RW |
0 |
||
4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
3 |
C_MASKINTS |
Mask interrupts when stepping or running in halted debug. This masking does not affect NMI, fault exceptions and SVC caused by execution of the instructions. This bit must only be modified when the processor is halted (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate). Modifying C_MASKINTS while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. |
RW |
0 |
||
2 |
C_STEP |
Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1). |
RW |
0 |
||
1 |
C_HALT |
Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. |
RW |
0 |
||
0 |
C_DEBUGEN |
Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself. |
RW |
0 |
Address offset |
0x0000 0DF4 |
||
Physical address |
0xE000 EDF4 |
Instance |
CPU_SCS |
Description |
Deubg Core Register Selector Register |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:17 |
RESERVED17 |
Software should not rely on the value of a reserved. Write 0. |
WO |
0x0000 |
||
16 |
REGWNR |
1: Write |
WO |
0 |
||
15:5 |
RESERVED5 |
Software should not rely on the value of a reserved. Write 0. |
WO |
0x000 |
||
4:0 |
REGSEL |
Register select |
WO |
0x00 |
Address offset |
0x0000 0DF8 |
||
Physical address |
0xE000 EDF8 |
Instance |
CPU_SCS |
Description |
Debug Core Register Data Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DCRDR |
This register holds data for reading and writing registers to and from the processor. This is the data value written to the register selected by DCRSR. When the processor receives a request from DCRSR, this register is read or written by the processor using a normal load-store unit operation. If core register transfers are not being performed, software-based debug monitors can use this register for communication in non-halting debug. This enables flags and bits to acknowledge state and indicate if commands have been accepted to, replied to, or accepted and replied to. |
RW |
0x0000 0000 |
Address offset |
0x0000 0DFC |
||
Physical address |
0xE000 EDFC |
Instance |
CPU_SCS |
Description |
Debug Exception and Monitor Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:25 |
RESERVED25 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
||
24 |
TRCENA |
This bit must be set to 1 to enable use of the trace and debug blocks: DWT, ITM, ETM and TPIU. This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger. |
RW |
0 |
||
23:20 |
RESERVED20 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
19 |
MON_REQ |
This enables the monitor to identify how it wakes up. This bit clears on a Core Reset. |
RW |
0 |
||
18 |
MON_STEP |
When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. |
RW |
0 |
||
17 |
MON_PEND |
Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a power-on reset. Software in the reset handler or later, or by the DAP must enable the debug monitor. |
RW |
0 |
||
16 |
MON_EN |
Enable the debug monitor. |
RW |
0 |
||
15:11 |
RESERVED11 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
||
10 |
VC_HARDERR |
Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. |
RW |
0 |
||
9 |
VC_INTERR |
Debug trap on a fault occurring during an exception entry or return sequence. Ignored when DHCSR.C_DEBUGEN is cleared. |
RW |
0 |
||
8 |
VC_BUSERR |
Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. |
RW |
0 |
||
7 |
VC_STATERR |
Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is cleared. |
RW |
0 |
||
6 |
VC_CHKERR |
Debug trap on Usage Fault enabled checking errors. Ignored when DHCSR.C_DEBUGEN is cleared. |
RW |
0 |
||
5 |
VC_NOCPERR |
Debug trap on a UsageFault access to a Coprocessor. Ignored when DHCSR.C_DEBUGEN is cleared. |
RW |
0 |
||
4 |
VC_MMERR |
Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is cleared. |
RW |
0 |
||
3:1 |
RESERVED1 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
0 |
VC_CORERESET |
Reset Vector Catch. Halt running system if Core reset occurs. Ignored when DHCSR.C_DEBUGEN is cleared. |
RW |
0 |
Address offset |
0x0000 0F00 |
||
Physical address |
0xE000 EF00 |
Instance |
CPU_SCS |
Description |
Software Trigger Interrupt Register |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:9 |
RESERVED9 |
Software should not rely on the value of a reserved. Write 0. |
WO |
0x00 0000 |
||
8:0 |
INTID |
Interrupt ID field. Writing a value to this bit-field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. |
WO |
0x000 |
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