Instance: EVENT
Component: EVENT
Base address: 0x40083000
Event Fabric Component Definition
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x0000 0004 |
0x0000 0000 |
0x4008 3000 |
|
RO |
32 |
0x0000 0009 |
0x0000 0004 |
0x4008 3004 |
|
RO |
32 |
0x0000 001E |
0x0000 0008 |
0x4008 3008 |
|
RO |
32 |
0x0000 0038 |
0x0000 000C |
0x4008 300C |
|
RO |
32 |
0x0000 0007 |
0x0000 0010 |
0x4008 3010 |
|
RO |
32 |
0x0000 0024 |
0x0000 0014 |
0x4008 3014 |
|
RO |
32 |
0x0000 001C |
0x0000 0018 |
0x4008 3018 |
|
RO |
32 |
0x0000 0022 |
0x0000 001C |
0x4008 301C |
|
RO |
32 |
0x0000 0023 |
0x0000 0020 |
0x4008 3020 |
|
RO |
32 |
0x0000 001B |
0x0000 0024 |
0x4008 3024 |
|
RO |
32 |
0x0000 001A |
0x0000 0028 |
0x4008 3028 |
|
RO |
32 |
0x0000 0019 |
0x0000 002C |
0x4008 302C |
|
RO |
32 |
0x0000 0008 |
0x0000 0030 |
0x4008 3030 |
|
RO |
32 |
0x0000 001D |
0x0000 0034 |
0x4008 3034 |
|
RO |
32 |
0x0000 0018 |
0x0000 0038 |
0x4008 3038 |
|
RO |
32 |
0x0000 0010 |
0x0000 003C |
0x4008 303C |
|
RO |
32 |
0x0000 0011 |
0x0000 0040 |
0x4008 3040 |
|
RO |
32 |
0x0000 0012 |
0x0000 0044 |
0x4008 3044 |
|
RO |
32 |
0x0000 0013 |
0x0000 0048 |
0x4008 3048 |
|
RO |
32 |
0x0000 000C |
0x0000 004C |
0x4008 304C |
|
RO |
32 |
0x0000 000D |
0x0000 0050 |
0x4008 3050 |
|
RO |
32 |
0x0000 000E |
0x0000 0054 |
0x4008 3054 |
|
RO |
32 |
0x0000 000F |
0x0000 0058 |
0x4008 3058 |
|
RO |
32 |
0x0000 005D |
0x0000 005C |
0x4008 305C |
|
RO |
32 |
0x0000 0027 |
0x0000 0060 |
0x4008 3060 |
|
RO |
32 |
0x0000 0026 |
0x0000 0064 |
0x4008 3064 |
|
RO |
32 |
0x0000 0015 |
0x0000 0068 |
0x4008 3068 |
|
RO |
32 |
0x0000 0064 |
0x0000 006C |
0x4008 306C |
|
RO |
32 |
0x0000 000B |
0x0000 0070 |
0x4008 3070 |
|
RO |
32 |
0x0000 0001 |
0x0000 0074 |
0x4008 3074 |
|
RW |
32 |
0x0000 0000 |
0x0000 0078 |
0x4008 3078 |
|
RO |
32 |
0x0000 006A |
0x0000 007C |
0x4008 307C |
|
RO |
32 |
0x0000 0073 |
0x0000 0080 |
0x4008 3080 |
|
RO |
32 |
0x0000 0068 |
0x0000 0084 |
0x4008 3084 |
|
RO |
32 |
0x0000 003D |
0x0000 0100 |
0x4008 3100 |
|
RO |
32 |
0x0000 003E |
0x0000 0104 |
0x4008 3104 |
|
RO |
32 |
0x0000 003F |
0x0000 0108 |
0x4008 3108 |
|
RO |
32 |
0x0000 0040 |
0x0000 010C |
0x4008 310C |
|
RO |
32 |
0x0000 0041 |
0x0000 0110 |
0x4008 3110 |
|
RO |
32 |
0x0000 0042 |
0x0000 0114 |
0x4008 3114 |
|
RO |
32 |
0x0000 0043 |
0x0000 0118 |
0x4008 3118 |
|
RO |
32 |
0x0000 0044 |
0x0000 011C |
0x4008 311C |
|
RO |
32 |
0x0000 0077 |
0x0000 0120 |
0x4008 3120 |
|
RW |
32 |
0x0000 0002 |
0x0000 0124 |
0x4008 3124 |
|
RW |
32 |
0x0000 0055 |
0x0000 0200 |
0x4008 3200 |
|
RW |
32 |
0x0000 0056 |
0x0000 0204 |
0x4008 3204 |
|
RW |
32 |
0x0000 0057 |
0x0000 0300 |
0x4008 3300 |
|
RW |
32 |
0x0000 0058 |
0x0000 0304 |
0x4008 3304 |
|
RW |
32 |
0x0000 0059 |
0x0000 0400 |
0x4008 3400 |
|
RW |
32 |
0x0000 005A |
0x0000 0404 |
0x4008 3404 |
|
RO |
32 |
0x0000 0031 |
0x0000 0508 |
0x4008 3508 |
|
RO |
32 |
0x0000 0030 |
0x0000 050C |
0x4008 350C |
|
RO |
32 |
0x0000 0033 |
0x0000 0510 |
0x4008 3510 |
|
RO |
32 |
0x0000 0032 |
0x0000 0514 |
0x4008 3514 |
|
RO |
32 |
0x0000 0029 |
0x0000 0518 |
0x4008 3518 |
|
RO |
32 |
0x0000 0028 |
0x0000 051C |
0x4008 351C |
|
RO |
32 |
0x0000 002B |
0x0000 0520 |
0x4008 3520 |
|
RO |
32 |
0x0000 002A |
0x0000 0524 |
0x4008 3524 |
|
RO |
32 |
0x0000 003A |
0x0000 0528 |
0x4008 3528 |
|
RO |
32 |
0x0000 0039 |
0x0000 052C |
0x4008 352C |
|
RO |
32 |
0x0000 003C |
0x0000 0530 |
0x4008 3530 |
|
RO |
32 |
0x0000 003B |
0x0000 0534 |
0x4008 3534 |
|
RO |
32 |
0x0000 0075 |
0x0000 0538 |
0x4008 3538 |
|
RO |
32 |
0x0000 0076 |
0x0000 053C |
0x4008 353C |
|
RO |
32 |
0x0000 0074 |
0x0000 0540 |
0x4008 3540 |
|
RO |
32 |
0x0000 0074 |
0x0000 0544 |
0x4008 3544 |
|
RW |
32 |
0x0000 0045 |
0x0000 0548 |
0x4008 3548 |
|
RW |
32 |
0x0000 004D |
0x0000 054C |
0x4008 354C |
|
RW |
32 |
0x0000 0046 |
0x0000 0550 |
0x4008 3550 |
|
RW |
32 |
0x0000 004E |
0x0000 0554 |
0x4008 3554 |
|
RW |
32 |
0x0000 0047 |
0x0000 0558 |
0x4008 3558 |
|
RW |
32 |
0x0000 004F |
0x0000 055C |
0x4008 355C |
|
RW |
32 |
0x0000 0048 |
0x0000 0560 |
0x4008 3560 |
|
RW |
32 |
0x0000 0050 |
0x0000 0564 |
0x4008 3564 |
|
RO |
32 |
0x0000 0003 |
0x0000 056C |
0x4008 356C |
|
RW |
32 |
0x0000 0001 |
0x0000 0574 |
0x4008 3574 |
|
RO |
32 |
0x0000 0007 |
0x0000 057C |
0x4008 357C |
|
RO |
32 |
0x0000 002D |
0x0000 0580 |
0x4008 3580 |
|
RO |
32 |
0x0000 002C |
0x0000 0584 |
0x4008 3584 |
|
RO |
32 |
0x0000 002F |
0x0000 0588 |
0x4008 3588 |
|
RO |
32 |
0x0000 002E |
0x0000 058C |
0x4008 358C |
|
RO |
32 |
0x0000 0064 |
0x0000 05A8 |
0x4008 35A8 |
|
RO |
32 |
0x0000 0064 |
0x0000 05AC |
0x4008 35AC |
|
RO |
32 |
0x0000 0065 |
0x0000 05B0 |
0x4008 35B0 |
|
RO |
32 |
0x0000 0065 |
0x0000 05B4 |
0x4008 35B4 |
|
RO |
32 |
0x0000 0066 |
0x0000 05B8 |
0x4008 35B8 |
|
RO |
32 |
0x0000 0066 |
0x0000 05BC |
0x4008 35BC |
|
RO |
32 |
0x0000 0067 |
0x0000 05C0 |
0x4008 35C0 |
|
RO |
32 |
0x0000 0067 |
0x0000 05C4 |
0x4008 35C4 |
|
RW |
32 |
0x0000 005B |
0x0000 0600 |
0x4008 3600 |
|
RW |
32 |
0x0000 005C |
0x0000 0604 |
0x4008 3604 |
|
RW |
32 |
0x0000 0010 |
0x0000 0700 |
0x4008 3700 |
|
RO |
32 |
0x0000 0063 |
0x0000 0800 |
0x4008 3800 |
|
RW |
32 |
0x0000 005F |
0x0000 0900 |
0x4008 3900 |
|
RW |
32 |
0x0000 0078 |
0x0000 0A00 |
0x4008 3A00 |
|
RW |
32 |
0x0000 0000 |
0x0000 0F00 |
0x4008 3F00 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4008 3000 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x04 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4008 3004 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 1 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x09 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4008 3008 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 2 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x1E |
Address offset |
0x0000 000C |
||
Physical address |
0x4008 300C |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 3 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x38 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4008 3010 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 4 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x07 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4008 3014 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 5 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x24 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4008 3018 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 6 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x1C |
Address offset |
0x0000 001C |
||
Physical address |
0x4008 301C |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 7 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x22 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4008 3020 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 8 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x23 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4008 3024 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 9 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x1B |
Address offset |
0x0000 0028 |
||
Physical address |
0x4008 3028 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 10 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x1A |
Address offset |
0x0000 002C |
||
Physical address |
0x4008 302C |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 11 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x19 |
Address offset |
0x0000 0030 |
||
Physical address |
0x4008 3030 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 12 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x08 |
Address offset |
0x0000 0034 |
||
Physical address |
0x4008 3034 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 13 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x1D |
Address offset |
0x0000 0038 |
||
Physical address |
0x4008 3038 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 14 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x18 |
Address offset |
0x0000 003C |
||
Physical address |
0x4008 303C |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 15 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x10 |
Address offset |
0x0000 0040 |
||
Physical address |
0x4008 3040 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 16 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x11 |
Address offset |
0x0000 0044 |
||
Physical address |
0x4008 3044 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 17 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x12 |
Address offset |
0x0000 0048 |
||
Physical address |
0x4008 3048 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 18 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x13 |
Address offset |
0x0000 004C |
||
Physical address |
0x4008 304C |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 19 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x0C |
Address offset |
0x0000 0050 |
||
Physical address |
0x4008 3050 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 20 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x0D |
Address offset |
0x0000 0054 |
||
Physical address |
0x4008 3054 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 21 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x0E |
Address offset |
0x0000 0058 |
||
Physical address |
0x4008 3058 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 22 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x0F |
Address offset |
0x0000 005C |
||
Physical address |
0x4008 305C |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 23 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x5D |
Address offset |
0x0000 0060 |
||
Physical address |
0x4008 3060 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 24 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x27 |
Address offset |
0x0000 0064 |
||
Physical address |
0x4008 3064 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 25 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x26 |
Address offset |
0x0000 0068 |
||
Physical address |
0x4008 3068 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 26 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x15 |
Address offset |
0x0000 006C |
||
Physical address |
0x4008 306C |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 27 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x64 |
Address offset |
0x0000 0070 |
||
Physical address |
0x4008 3070 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 28 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x0B |
Address offset |
0x0000 0074 |
||
Physical address |
0x4008 3074 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 29 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x01 |
Address offset |
0x0000 0078 |
||
Physical address |
0x4008 3078 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 30 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x00 |
Address offset |
0x0000 007C |
||
Physical address |
0x4008 307C |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 31 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x6A |
Address offset |
0x0000 0080 |
||
Physical address |
0x4008 3080 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 32 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x73 |
Address offset |
0x0000 0084 |
||
Physical address |
0x4008 3084 |
Instance |
EVENT |
Description |
Output Selection for CPU Interrupt 33 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x68 |
Address offset |
0x0000 0100 |
||
Physical address |
0x4008 3100 |
Instance |
EVENT |
Description |
Output Selection for RFC Event 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x3D |
Address offset |
0x0000 0104 |
||
Physical address |
0x4008 3104 |
Instance |
EVENT |
Description |
Output Selection for RFC Event 1 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x3E |
Address offset |
0x0000 0108 |
||
Physical address |
0x4008 3108 |
Instance |
EVENT |
Description |
Output Selection for RFC Event 2 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x3F |
Address offset |
0x0000 010C |
||
Physical address |
0x4008 310C |
Instance |
EVENT |
Description |
Output Selection for RFC Event 3 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x40 |
Address offset |
0x0000 0110 |
||
Physical address |
0x4008 3110 |
Instance |
EVENT |
Description |
Output Selection for RFC Event 4 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x41 |
Address offset |
0x0000 0114 |
||
Physical address |
0x4008 3114 |
Instance |
EVENT |
Description |
Output Selection for RFC Event 5 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x42 |
Address offset |
0x0000 0118 |
||
Physical address |
0x4008 3118 |
Instance |
EVENT |
Description |
Output Selection for RFC Event 6 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x43 |
Address offset |
0x0000 011C |
||
Physical address |
0x4008 311C |
Instance |
EVENT |
Description |
Output Selection for RFC Event 7 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x44 |
Address offset |
0x0000 0120 |
||
Physical address |
0x4008 3120 |
Instance |
EVENT |
Description |
Output Selection for RFC Event 8 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x77 |
Address offset |
0x0000 0124 |
||
Physical address |
0x4008 3124 |
Instance |
EVENT |
Description |
Output Selection for RFC Event 9 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x02 |
Address offset |
0x0000 0200 |
||
Physical address |
0x4008 3200 |
Instance |
EVENT |
Description |
Output Selection for GPT0 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x55 |
Address offset |
0x0000 0204 |
||
Physical address |
0x4008 3204 |
Instance |
EVENT |
Description |
Output Selection for GPT0 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x56 |
Address offset |
0x0000 0300 |
||
Physical address |
0x4008 3300 |
Instance |
EVENT |
Description |
Output Selection for GPT1 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x57 |
Address offset |
0x0000 0304 |
||
Physical address |
0x4008 3304 |
Instance |
EVENT |
Description |
Output Selection for GPT1 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x58 |
Address offset |
0x0000 0400 |
||
Physical address |
0x4008 3400 |
Instance |
EVENT |
Description |
Output Selection for GPT2 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x59 |
Address offset |
0x0000 0404 |
||
Physical address |
0x4008 3404 |
Instance |
EVENT |
Description |
Output Selection for GPT2 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x5A |
Address offset |
0x0000 0508 |
||
Physical address |
0x4008 3508 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x31 |
Address offset |
0x0000 050C |
||
Physical address |
0x4008 350C |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x30 |
Address offset |
0x0000 0510 |
||
Physical address |
0x4008 3510 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x33 |
Address offset |
0x0000 0514 |
||
Physical address |
0x4008 3514 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x32 |
Address offset |
0x0000 0518 |
||
Physical address |
0x4008 3518 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x29 |
Address offset |
0x0000 051C |
||
Physical address |
0x4008 351C |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x28 |
Address offset |
0x0000 0520 |
||
Physical address |
0x4008 3520 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x2B |
Address offset |
0x0000 0524 |
||
Physical address |
0x4008 3524 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x2A |
Address offset |
0x0000 0528 |
||
Physical address |
0x4008 3528 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x3A |
Address offset |
0x0000 052C |
||
Physical address |
0x4008 352C |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x39 |
Address offset |
0x0000 0530 |
||
Physical address |
0x4008 3530 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x3C |
Address offset |
0x0000 0534 |
||
Physical address |
0x4008 3534 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x3B |
Address offset |
0x0000 0538 |
||
Physical address |
0x4008 3538 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x75 |
Address offset |
0x0000 053C |
||
Physical address |
0x4008 353C |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x76 |
Address offset |
0x0000 0540 |
||
Physical address |
0x4008 3540 |
Instance |
EVENT |
Description |
Output Selection for DMA Channel 8 SREQ |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x74 |
Address offset |
0x0000 0544 |
||
Physical address |
0x4008 3544 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x74 |
Address offset |
0x0000 0548 |
||
Physical address |
0x4008 3548 |
Instance |
EVENT |
Description |
Output Selection for DMA Channel 9 SREQ |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x45 |
Address offset |
0x0000 054C |
||
Physical address |
0x4008 354C |
Instance |
EVENT |
Description |
Output Selection for DMA Channel 9 REQ |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x4D |
Address offset |
0x0000 0550 |
||
Physical address |
0x4008 3550 |
Instance |
EVENT |
Description |
Output Selection for DMA Channel 10 SREQ |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x46 |
Address offset |
0x0000 0554 |
||
Physical address |
0x4008 3554 |
Instance |
EVENT |
Description |
Output Selection for DMA Channel 10 REQ |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x4E |
Address offset |
0x0000 0558 |
||
Physical address |
0x4008 3558 |
Instance |
EVENT |
Description |
Output Selection for DMA Channel 11 SREQ |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x47 |
Address offset |
0x0000 055C |
||
Physical address |
0x4008 355C |
Instance |
EVENT |
Description |
Output Selection for DMA Channel 11 REQ |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x4F |
Address offset |
0x0000 0560 |
||
Physical address |
0x4008 3560 |
Instance |
EVENT |
Description |
Output Selection for DMA Channel 12 SREQ |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x48 |
Address offset |
0x0000 0564 |
||
Physical address |
0x4008 3564 |
Instance |
EVENT |
Description |
Output Selection for DMA Channel 12 REQ |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x50 |
Address offset |
0x0000 056C |
||
Physical address |
0x4008 356C |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x03 |
Address offset |
0x0000 0574 |
||
Physical address |
0x4008 3574 |
Instance |
EVENT |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x01 |
Address offset |
0x0000 057C |
||
Physical address |
0x4008 357C |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x07 |
Address offset |
0x0000 0580 |
||
Physical address |
0x4008 3580 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x2D |
Address offset |
0x0000 0584 |
||
Physical address |
0x4008 3584 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x2C |
Address offset |
0x0000 0588 |
||
Physical address |
0x4008 3588 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x2F |
Address offset |
0x0000 058C |
||
Physical address |
0x4008 358C |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x2E |
Address offset |
0x0000 05A8 |
||
Physical address |
0x4008 35A8 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x64 |
Address offset |
0x0000 05AC |
||
Physical address |
0x4008 35AC |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x64 |
Address offset |
0x0000 05B0 |
||
Physical address |
0x4008 35B0 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x65 |
Address offset |
0x0000 05B4 |
||
Physical address |
0x4008 35B4 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x65 |
Address offset |
0x0000 05B8 |
||
Physical address |
0x4008 35B8 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x66 |
Address offset |
0x0000 05BC |
||
Physical address |
0x4008 35BC |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x66 |
Address offset |
0x0000 05C0 |
||
Physical address |
0x4008 35C0 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x67 |
Address offset |
0x0000 05C4 |
||
Physical address |
0x4008 35C4 |
Instance |
EVENT |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x67 |
Address offset |
0x0000 0600 |
||
Physical address |
0x4008 3600 |
Instance |
EVENT |
Description |
Output Selection for GPT3 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x5B |
Address offset |
0x0000 0604 |
||
Physical address |
0x4008 3604 |
Instance |
EVENT |
Description |
Output Selection for GPT3 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x5C |
Address offset |
0x0000 0700 |
||
Physical address |
0x4008 3700 |
Instance |
EVENT |
Description |
Output Selection for AUX Subscriber 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x10 |
Address offset |
0x0000 0800 |
||
Physical address |
0x4008 3800 |
Instance |
EVENT |
Description |
Output Selection for NMI Subscriber 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||
6:0 |
EV |
Read only selection value
|
RO |
0x63 |
Address offset |
0x0000 0900 |
||
Physical address |
0x4008 3900 |
Instance |
EVENT |
Description |
Output Selection for I2S Subscriber 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x5F |
Address offset |
0x0000 0A00 |
||
Physical address |
0x4008 3A00 |
Instance |
EVENT |
Description |
Output Selection for FRZ Subscriber 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||
6:0 |
EV |
Read/write selection value
|
RW |
0x78 |
Address offset |
0x0000 0F00 |
||
Physical address |
0x4008 3F00 |
Instance |
EVENT |
Description |
Set or Clear Software Events |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:25 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
24 |
SWEV3 |
Writing "1" to this bit when the value is "0" triggers the Software 3 event. |
RW |
0 |
||
23:17 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
16 |
SWEV2 |
Writing "1" to this bit when the value is "0" triggers the Software 2 event. |
RW |
0 |
||
15:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
8 |
SWEV1 |
Writing "1" to this bit when the value is "0" triggers the Software 1 event. |
RW |
0 |
||
7:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
0 |
SWEV0 |
Writing "1" to this bit when the value is "0" triggers the Software 0 event. |
RW |
0 |
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