Instance: ADI_3_REFSYS
Component: ADI_3_REFSYS
Base address: 0x40086200
ADI for REFSYS modules.
Registers Fields should be considered static unless otherwise noted (as dynamic)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
8 |
0x0000 0000 |
0x0000 0000 |
0x4008 6200 |
|
RW |
8 |
0x0000 0000 |
0x0000 0001 |
0x4008 6201 |
|
RW |
8 |
0x0000 0000 |
0x0000 0002 |
0x4008 6202 |
|
RW |
8 |
0x0000 0000 |
0x0000 0003 |
0x4008 6203 |
|
RW |
8 |
0x0000 0000 |
0x0000 0004 |
0x4008 6204 |
|
RW |
8 |
0x0000 0000 |
0x0000 0005 |
0x4008 6205 |
|
RW |
8 |
0x0000 0000 |
0x0000 0006 |
0x4008 6206 |
|
RW |
8 |
0x0000 0000 |
0x0000 0007 |
0x4008 6207 |
|
RW |
8 |
0x0000 0000 |
0x0000 0008 |
0x4008 6208 |
|
RW |
8 |
0x0000 0000 |
0x0000 0009 |
0x4008 6209 |
|
RW |
8 |
0x0000 0000 |
0x0000 000A |
0x4008 620A |
|
RW |
8 |
0x0000 0000 |
0x0000 000B |
0x4008 620B |
Address offset |
0x0000 0000 |
||
Physical address |
0x4008 6200 |
Instance |
ADI_3_REFSYS |
Description |
Analog Test Control 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||
7:4 |
SPARE4 |
RSVD, not used at this time. |
RW |
0x0 |
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3:0 |
TEST_CTL |
ATEST muxing:
|
RW |
0x0 |
Address offset |
0x0000 0001 |
||
Physical address |
0x4008 6201 |
Instance |
ADI_3_REFSYS |
Description |
Analog Test Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:0 |
SPARE0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
Address offset |
0x0000 0002 |
||
Physical address |
0x4008 6202 |
Instance |
ADI_3_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
7:0 |
TESTCTL |
Internal
|
RW |
0x00 |
Address offset |
0x0000 0003 |
||
Physical address |
0x4008 6203 |
Instance |
ADI_3_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:3 |
TRIM_VDDS_BOD |
Internal
|
RW |
0x00 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 |
BATMON_COMP_TEST_EN |
Internal
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1:0 |
TESTCTL |
Internal
|
RW |
0x0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4008 6204 |
Instance |
ADI_3_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:4 |
TRIM_VREF |
Internal |
RW |
0x0 |
||
3:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
1:0 |
TRIM_TSENSE |
Internal |
RW |
0x0 |
Address offset |
0x0000 0005 |
||
Physical address |
0x4008 6205 |
Instance |
ADI_3_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7 |
BOD_BG_TRIM_EN |
Internal |
RW |
0 |
|||||||||||||
6 |
VTEMP_EN |
Internal
|
RW |
0 |
|||||||||||||
5:0 |
TRIM_VBG |
Internal |
RW |
0x00 |
Address offset |
0x0000 0006 |
||
Physical address |
0x4008 6206 |
Instance |
ADI_3_REFSYS |
Description |
DCDC Control Register 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:5 |
GLDO_ISRC |
Set charge and re-charge current level. |
RW |
0x0 |
||
4:0 |
VDDR_TRIM |
Set the VDDR voltage. |
RW |
0x00 |
Address offset |
0x0000 0007 |
||
Physical address |
0x4008 6207 |
Instance |
ADI_3_REFSYS |
Description |
DCDC Control Register 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:6 |
IPTAT_TRIM |
Trim GLDO bias current. |
RW |
0x0 |
||
5 |
VDDR_OK_HYST |
Increase the hysteresis for when VDDR is considered ok. |
RW |
0 |
||
4:0 |
VDDR_TRIM_SLEEP |
Set the min VDDR voltage threshold during sleep mode. |
RW |
0x00 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4008 6208 |
Instance |
ADI_3_REFSYS |
Description |
DCDC Control Register 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||
7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
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6 |
TURNON_EA_SW |
Turn on erroramp switch |
RW |
0 |
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5 |
TEST_VDDR |
Connect VDDR to ATEST bus |
RW |
0 |
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4 |
BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
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3:0 |
TESTSEL |
Select signal for test bus, one hot.
|
RW |
0x0 |
Address offset |
0x0000 0009 |
||
Physical address |
0x4008 6209 |
Instance |
ADI_3_REFSYS |
Description |
DCDC Control Register 3 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 |
Address offset |
0x0000 000A |
||
Physical address |
0x4008 620A |
Instance |
ADI_3_REFSYS |
Description |
DCDC Control Register 5 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:6 |
DEADTIME_TRIM |
Adjust the supply voltage threshold below which the non overlap delay of the switch driver block decreases. |
RW |
0x0 |
||
5:3 |
LOW_EN_SEL |
Control NMOS switch strength in linear steps. |
RW |
0x0 |
||
2:0 |
HIGH_EN_SEL |
Control PMOS switch strength in linear steps. |
RW |
0x0 |
Address offset |
0x0000 000B |
||
Physical address |
0x4008 620B |
Instance |
ADI_3_REFSYS |
Description |
DCDC Control Register 6 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
|||||||||||||
5 |
TESTN |
Buck converter NMOS switch is turned on. |
RW |
0 |
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4 |
TESTP |
Buck converter PMOS switch is turned on. |
RW |
0 |
|||||||||||||
3 |
DITHER_EN |
Enable switching frequency randomizer
|
RW |
0 |
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2:0 |
IPEAK |
Set inductor peak current. |
RW |
0x0 |
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