Instance: CPU_TPIU
Component: CPU_TPIU
Base address: 0xe0040000
Cortex-M3's Trace Port Interface Unit (TPIU)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x0000 000B |
0x0000 0000 |
0xE004 0000 |
|
RW |
32 |
0x0000 0001 |
0x0000 0004 |
0xE004 0004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0xE004 0010 |
|
RW |
32 |
0x0000 0001 |
0x0000 00F0 |
0xE004 00F0 |
|
RO |
32 |
0x0000 0008 |
0x0000 0300 |
0xE004 0300 |
|
RW |
32 |
0x0000 0102 |
0x0000 0304 |
0xE004 0304 |
|
RO |
32 |
0x0000 0000 |
0x0000 0308 |
0xE004 0308 |
|
RO |
32 |
0x0000 000F |
0x0000 0FA0 |
0xE004 0FA0 |
|
WO |
32 |
0x0000 000F |
0x0000 0FA0 |
0xE004 0FA0 |
|
RO |
32 |
0x0000 0000 |
0x0000 0FA4 |
0xE004 0FA4 |
|
WO |
32 |
0x0000 0000 |
0x0000 0FA4 |
0xE004 0FA4 |
|
RO |
32 |
0x0000 0CA0 |
0x0000 0FC8 |
0xE004 0FC8 |
Address offset |
0x0000 0000 |
||
Physical address |
0xE004 0000 |
Instance |
CPU_TPIU |
Description |
Supported Sync Port Sizes Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x000 0000 |
||
3 |
FOUR |
4-bit port size support |
RO |
1 |
||
2 |
THREE |
3-bit port size support |
RO |
0 |
||
1 |
TWO |
2-bit port size support |
RO |
1 |
||
0 |
ONE |
1-bit port size support |
RO |
1 |
Address offset |
0x0000 0004 |
||
Physical address |
0xE004 0004 |
Instance |
CPU_TPIU |
Description |
Current Sync Port Size Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x000 0000 |
||
3 |
FOUR |
4-bit port enable |
RW |
0 |
||
2 |
THREE |
3-bit port enable |
RW |
0 |
||
1 |
TWO |
2-bit port enable |
RW |
0 |
||
0 |
ONE |
1-bit port enable |
RW |
1 |
Address offset |
0x0000 0010 |
||
Physical address |
0xE004 0010 |
Instance |
CPU_TPIU |
Description |
Async Clock Prescaler Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:13 |
RESERVED13 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 0000 |
||
12:0 |
PRESCALER |
Divisor for input trace clock is (PRESCALER + 1). |
RW |
0x0000 |
Address offset |
0x0000 00F0 |
||
Physical address |
0xE004 00F0 |
Instance |
CPU_TPIU |
Description |
Selected Pin Protocol Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||
31:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0000 0000 |
|||||||||||||||||
1:0 |
PROTOCOL |
Trace output protocol
|
RW |
0x1 |
Address offset |
0x0000 0300 |
||
Physical address |
0xE004 0300 |
Instance |
CPU_TPIU |
Description |
Formatter and Flush Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x000 0000 |
||
3 |
FTNONSTOP |
0: Formatter can be stopped |
RO |
1 |
||
2:0 |
RESERVED0 |
This field always reads as zero |
RO |
0x0 |
Address offset |
0x0000 0304 |
||
Physical address |
0xE004 0304 |
Instance |
CPU_TPIU |
Description |
Formatter and Flush Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:9 |
RESERVED9 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 0000 |
||
8 |
TRIGIN |
Indicates that triggers are inserted when a trigger pin is asserted. |
RW |
1 |
||
7:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
||
1 |
ENFCONT |
Enable continuous formatting: |
RW |
1 |
||
0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
Address offset |
0x0000 0308 |
||
Physical address |
0xE004 0308 |
Instance |
CPU_TPIU |
Description |
Formatter Synchronization Counter Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
FSCR |
The global synchronization trigger is generated by the Program Counter (PC) Sampler block. This means that there is no synchronization counter in the TPIU. |
RO |
0x0000 0000 |
Address offset |
0x0000 0FA0 |
||
Physical address |
0xE004 0FA0 |
Instance |
CPU_TPIU |
Description |
Claim Tag Mask Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CLAIMMASK |
This register forms one half of the Claim Tag value. When reading this register returns the number of bits that can be set (each bit is considered separately): |
RO |
0x0000 000F |
Address offset |
0x0000 0FA0 |
||
Physical address |
0xE004 0FA0 |
Instance |
CPU_TPIU |
Description |
Claim Tag Set Register |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CLAIMSET |
This register forms one half of the Claim Tag value. Writing to this location allows individual bits to be set (each bit is considered separately): |
WO |
0x0000 000F |
Address offset |
0x0000 0FA4 |
||
Physical address |
0xE004 0FA4 |
Instance |
CPU_TPIU |
Description |
Current Claim Tag Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CLAIMTAG |
This register forms one half of the Claim Tag value. Reading this register returns the current Claim Tag value. |
RO |
0x0000 0000 |
Address offset |
0x0000 0FA4 |
||
Physical address |
0xE004 0FA4 |
Instance |
CPU_TPIU |
Description |
Claim Tag Clear Register |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CLAIMCLR |
This register forms one half of the Claim Tag value. Writing to this location enables individual bits to be cleared (each bit is considered separately): |
WO |
0x0000 0000 |
Address offset |
0x0000 0FC8 |
||
Physical address |
0xE004 0FC8 |
Instance |
CPU_TPIU |
Description |
Device ID Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DEVID |
This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no ETM present. |
RO |
0x0000 0CA0 |
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