AUX_ANAIF

Instance: AUX_ANAIF
Component: AUX_ANAIF
Base address: 0x400c9000

 

AUX Analog Peripheral Control Module

 

TOP:AUX_ANAIF Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

ADCCTL

RW

32

0x0000 0000

0x0000 0010

0x400C 9010

ADCFIFOSTAT

RO

32

0x0000 0001

0x0000 0014

0x400C 9014

ADCFIFO

RW

32

0x0000 0000

0x0000 0018

0x400C 9018

ADCTRIG

RW

32

0x0000 0000

0x0000 001C

0x400C 901C

ISRCCTL

RW

32

0x0000 0001

0x0000 0020

0x400C 9020

TOP:AUX_ANAIF Register Descriptions

TOP:AUX_ANAIF:ADCCTL

Address offset

0x0000 0010

Physical address

0x400C 9010

Instance

AUX_ANAIF

Description

ADC Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

13

START_POL

Selected active edge for start event / Selected polarity for start event

Value

ENUM name

Description

0

RISE

Start on rising edge of event

1

FALL

Start on falling edge of event

RW

0

12:8

START_SRC

Selected source for ADC conversion start event. The start source selected by this field is OR'ed with any trigger coming from writes to ADCTRIG.START. If it is desired to only trigger ADC conversions by writes to ADCTRIG.START one should select NO_EVENT here

Value

ENUM name

Description

0x00

RTC_CH2_EV

Selects RTC_CH2_EV as start signal

0x01

AUX_COMPA

Selects AUX_COMPA as start signal

0x02

AUX_COMPB

Selects AUX_COMPB as start signal

0x03

TDC_DONE

Selects TDC_DONE as start signal

0x04

TIMER0_EV

Selects TIMER0_EV as start signal

0x05

TIMER1_EV

Selects TIMER1_EV as start signal

0x06

SMPH_AUTOTAKE_DONE

Selects SMPH_AUTOTAKE_DONE as start signal

0x07

RESERVED0

Reserved do not use

0x08

RESERVED1

Reserved do not use

0x09

NO_EVENT0

No event selected

0x0A

NO_EVENT1

No event selected

0x0B

AON_SW

Selects AON_SW as start signal

0x0C

AON_PROG_WU

Selects AON_PROG_WU as start signal

0x0D

AUXIO0

Selects AUXIO0 as start signal

0x0E

AUXIO1

Selects AUXIO1 as start signal

0x0F

AUXIO2

Selects AUXIO2 as start signal

0x10

AUXIO3

Selects AUXIO3 as start signal

0x11

AUXIO4

Selects AUXIO4 as start signal

0x12

AUXIO5

Selects AUXIO5 as start signal

0x13

AUXIO6

Selects AUXIO6 as start signal

0x14

AUXIO7

Selects AUXIO7 as start signal

0x15

AUXIO8

Selects AUXIO8 as start signal

0x16

AUXIO9

Selects AUXIO9 as start signal

0x17

AUXIO10

Selects AUXIO10 as start signal

0x18

AUXIO11

Selects AUXIO11 as start signal

0x19

AUXIO12

Selects AUXIO12 as start signal

0x1A

AUXIO13

Selects AUXIO13 as start signal

0x1B

AUXIO14

Selects AUXIO14 as start signal

0x1C

AUXIO15

Selects AUXIO15 as start signal

0x1D

ACLK_REF

Selects ACLK_REF as start signal

0x1E

MCU_EV

Selects MCU_EV as start signal

0x1F

ADC_IRQ

Selects ADC_IRQ as start signal

RW

0x00

7:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

1:0

CMD

ADC interface control command

Value

ENUM name

Description

0x0

DIS

ADC interface disabled

0x1

EN

ADC interface enabled

0x3

FLUSH

ADC FIFO flush. Note that CMD needs to be set to 'EN' again for FIFO to be functional after a flush. A flush takes two clock periods on the AUX clock to finish.

RW

0x0



TOP:AUX_ANAIF:ADCFIFOSTAT

Address offset

0x0000 0014

Physical address

0x400C 9014

Instance

AUX_ANAIF

Description

ADC FIFO Status

FIFO can hold up to four ADC samples

Type

RO

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4

OVERFLOW

FIFO overflow flag.

0: FIFO has not overflowed.
1: FIFO has overflowed, this flag is sticky until FIFO is flushed.

RO

0

3

UNDERFLOW

FIFO underflow flag.

0: FIFO has not underflowed
1: FIFO has underflowed, this flag is sticky until the FIFO is flushed

RO

0

2

FULL

FIFO full flag.

0: FIFO is not full, i.e. there is less than 4 samples in the FIFO.
1: FIFO is full, i.e. there are 4 samples in the FIFO

RO

0

1

ALMOST_FULL

FIFO almost full flag.

0: There is less than 3 samples in the FIFO, or the FIFO is full in which case the FULL flag is asserted
1: There are 3 samples in the FIFO, i.e. there is room for one more sample

RO

0

0

EMPTY

FIFO empty flag.

0: FIFO contains one or more samples
1: FIFO is empty

RO

1



TOP:AUX_ANAIF:ADCFIFO

Address offset

0x0000 0018

Physical address

0x400C 9018

Instance

AUX_ANAIF

Description

ADC FIFO

Type

RW

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

11:0

DATA

FIFO is popped when read. Data is pushed into FIFO when written. Writing is intended for debugging/code development purposes

RW

0x000



TOP:AUX_ANAIF:ADCTRIG

Address offset

0x0000 001C

Physical address

0x400C 901C

Instance

AUX_ANAIF

Description

ADC Trigger

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

START

Writing to this register will trigger an ADC conversion given that ADCCTL.START_SRC is set to NO_EVENT0 or NO_EVENT1. If other setting is used in ADCCTL.START_SRC behavior can be unpredictable

WO

0



TOP:AUX_ANAIF:ISRCCTL

Address offset

0x0000 0020

Physical address

0x400C 9020

Instance

AUX_ANAIF

Description

Current Source Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

RESET_N

Current source control

0: Current source is clamped
1: Current source is active/charging

RW

1