Instance: AON_SYSCTL
Component: AON_SYSCTL
Base address: 0x40090000
This component controls AON_SYSCTL, which is the device's system controller.
Note: This module is only supporting 32 bit ReadWrite access from MCU
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4009 0000 |
|
RW |
32 |
0x0000 00E0 |
0x0000 0004 |
0x4009 0004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4009 0008 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4009 0000 |
Instance |
AON_SYSCTL |
Description |
Power Management |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
||
11 |
VDDS3_IOSEG_EN_SET |
VDDS3 I/O segment enable |
WO |
0 |
||
10 |
VDDS2_IOSEG_EN_SET |
VDDS2 I/O segment enable |
WO |
0 |
||
9 |
VDDS3_IOSEG_EN_CLR |
VDDS3 I/O segment disable |
WO |
0 |
||
8 |
VDDS2_IOSEG_EN_CLR |
VDDS2 I/O segment disable |
WO |
0 |
||
7:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
2 |
DCDC_ACTIVE |
Select to use DCDC regulator for VDDR in active mode |
RW |
0 |
||
1 |
EXT_REG_MODE |
Status of source for VDDRsupply: |
RO |
0 |
||
0 |
DCDC_EN |
Select to use DCDC regulator during recharge of VDDR |
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4009 0004 |
Instance |
AON_SYSCTL |
Description |
Reset Management |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||
31 |
SYSRESET |
Cold reset register. Writing 1 to this bitfield will reset the entire chip and cause boot code to run again. |
WO |
0 |
|||||||||||||||||||||||||||||||||||||
30:26 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
|||||||||||||||||||||||||||||||||||||
25 |
BOOT_DET_1_CLR |
Clear of debug flag 1 BOOT_DET_1 . Takes immediate effect as signal is not synchronized to SCLK_LF Clock |
RW |
0 |
|||||||||||||||||||||||||||||||||||||
24 |
BOOT_DET_0_CLR |
Clear of debug flag 0 BOOT_DET_0. Takes immediate effect as signal is not synchronized to SCLK_LF Clock |
RW |
0 |
|||||||||||||||||||||||||||||||||||||
23:18 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
|||||||||||||||||||||||||||||||||||||
17 |
BOOT_DET_1_SET |
Set of debug flag 1 BOOT_DET_1 . Takes immediate effect as signal is not synchronized to SCLK_LF Clock |
RW |
0 |
|||||||||||||||||||||||||||||||||||||
16 |
BOOT_DET_0_SET |
Set of debug flag 0 BOOT_DET_0. Takes immediate effect as signal is not synchronized to SCLK_LF Clock |
RW |
0 |
|||||||||||||||||||||||||||||||||||||
15 |
WU_FROM_SD |
A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin being forced low) |
RO |
0 |
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14 |
GPIO_WU_FROM_SD |
A wakeup from SHUTDOWN on an IO event has occurred |
RO |
0 |
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13 |
BOOT_DET_1 |
Boot Debug flag which has retention throughout a system reset. This flag may be used by software to trace an undesired system reset. |
RO |
0 |
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12 |
BOOT_DET_0 |
Boot Debug flag which has retention throughout a system reset. This flag may be used by software to trace an undesired system reset. |
RO |
0 |
|||||||||||||||||||||||||||||||||||||
11 |
VDDS_LOSS_EN_OVR |
Internal field controlled by TI provided startup code |
RW |
0 |
|||||||||||||||||||||||||||||||||||||
10 |
VDDR_LOSS_EN_OVR |
Internal field controlled by TI provided startup code |
RW |
0 |
|||||||||||||||||||||||||||||||||||||
9 |
VDD_LOSS_EN_OVR |
Internal field controlled by TI provided startup code |
RW |
0 |
|||||||||||||||||||||||||||||||||||||
8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
|||||||||||||||||||||||||||||||||||||
7 |
VDDS_LOSS_EN |
Controls reset generation in case VDDS is lost |
RW |
1 |
|||||||||||||||||||||||||||||||||||||
6 |
VDDR_LOSS_EN |
Controls reset generation in case VDDR is lost |
RW |
1 |
|||||||||||||||||||||||||||||||||||||
5 |
VDD_LOSS_EN |
Controls reset generation in case VDD is lost |
RW |
1 |
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4 |
CLK_LOSS_EN |
Controls reset generation in case SCLK_LF is lost. (provided that clock loss detection is enabled by DDI_0_OSC:CTL0.CLK_LOSS_EN) |
RW |
0 |
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3:1 |
RESET_SRC |
Shows the source of the last system reset:
|
RO |
0x0 |
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0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4009 0008 |
Instance |
AON_SYSCTL |
Description |
Sleep Mode Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
IO_PAD_SLEEP_DIS |
Controls the I/O pad sleep mode. The boot code will set this bitfield automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set ). |
RW |
0 |
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