RFC_FSCA

Instance: RFC_FSCA
Component: RFC_FSCA
Base address: 0x40044000

 

Component for fsca register bank

 

TOP:RFC_FSCA Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SYNTHREG00

RW

32

0x0000 0000

0x0000 0000

0x4004 4000

PREDIV

RW

32

0x0000 0000

0x0000 0004

0x4004 4004

PLLM

RW

32

0x0000 0000

0x0000 0008

0x4004 4008

OTHERM

RW

32

0x0000 0000

0x0000 000C

0x4004 400C

FINECALM

RW

32

0x0000 0000

0x0000 0010

0x4004 4010

FRCDCO

RW

32

0x0000 0000

0x0000 0014

0x4004 4014

SDCTL

RW

32

0x0000 0000

0x0000 0018

0x4004 4018

DTSTCTL

RW

32

0x0000 0000

0x0000 001C

0x4004 401C

DIGCFG2

RW

32

0x0000 0000

0x0000 0020

0x4004 4020

TDCTH

RW

32

0x0000 0000

0x0000 0024

0x4004 4024

LOOPCOEFF

RW

32

0x0000 0000

0x0000 0028

0x4004 4028

PLLCTL0

RW

32

0x0000 0000

0x0000 002C

0x4004 402C

FSMCTL0

RW

32

0x0000 0000

0x0000 0030

0x4004 4030

PETH

RW

32

0x0000 0000

0x0000 0034

0x4004 4034

PLLCTL1

RW

32

0x0000 0000

0x0000 0038

0x4004 4038

DTX

RW

32

0x0000 0000

0x0000 003C

0x4004 403C

DTX00

RW

32

0x0000 0000

0x0000 0040

0x4004 4040

DTX01

RW

32

0x0000 0000

0x0000 0044

0x4004 4044

DTX02

RW

32

0x0000 0000

0x0000 0048

0x4004 4048

DTX03

RW

32

0x0000 0000

0x0000 004C

0x4004 404C

DTX04

RW

32

0x0000 0000

0x0000 0050

0x4004 4050

DTX05

RW

32

0x0000 0000

0x0000 0054

0x4004 4054

DTXGAIN

RW

32

0x0000 0000

0x0000 0058

0x4004 4058

ANADIV

RW

32

0x0000 0000

0x0000 005C

0x4004 405C

PLLCTL2

RO

32

0x0000 0000

0x0000 0060

0x4004 4060

FSMCTL1

RW

32

0x0000 0000

0x0000 0064

0x4004 4064

FSMCTL2

RO

32

0x0000 0000

0x0000 0068

0x4004 4068

SPARE0

RW

32

0x0000 0000

0x0000 006C

0x4004 406C

STAT0

RO

32

0x0000 0000

0x0000 0070

0x4004 4070

STAT1

RO

32

0x0000 0000

0x0000 0074

0x4004 4074

STAT2

RO

32

0x0000 0000

0x0000 0078

0x4004 4078

STAT3

RO

32

0x0000 0000

0x0000 007C

0x4004 407C

DDICTL

RW

32

0x0000 0000

0x0000 0100

0x4004 4100

DDISTATUS

RO

32

0x0000 0000

0x0000 0104

0x4004 4104

ADI1CTL

RW

32

0x0000 0000

0x0000 0108

0x4004 4108

ADI1CLK

RW

32

0x0000 0000

0x0000 010C

0x4004 410C

ADI1CLRREQ

RW

32

0x0000 0000

0x0000 0110

0x4004 4110

ADI1ADDRWRDATA

RW

32

0x0000 0000

0x0000 0114

0x4004 4114

ADI1RD

RO

32

0x0000 0000

0x0000 0118

0x4004 4118

DIVCTRL

RO

32

0x0000 0000

0x0000 011C

0x4004 411C

DIVIDEND

RW

32

0x0000 0000

0x0000 0120

0x4004 4120

DIVISOR

RW

32

0x0000 0000

0x0000 0124

0x4004 4124

QUOTIENT

RO

32

0x0000 0000

0x0000 0128

0x4004 4128

TOP:RFC_FSCA Register Descriptions

TOP:RFC_FSCA:SYNTHREG00

Address offset

0x0000 0000

Physical address

0x4004 4000

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:SYNTHREG00.

Type

RW

Bits

Field Name

Description

Type

Reset

31

SYNTH_TX_RX_Z

See DLO_DTX:SYNTHREG00.SYNTH_TX_RX_Z.

Value

ENUM name

Description

0

RX

See DLO_DTX:SYNTHREG00.SYNTH_TX_RX_Z.

1

TX

See DLO_DTX:SYNTHREG00.SYNTH_TX_RX_Z.

RW

0

30

HSD_CLOCK_MASTER_ENABLE

See DLO_DTX:SYNTHREG00.HSD_CLOCK_MASTER_ENABLE.

Value

ENUM name

Description

0

DIS

See DLO_DTX:SYNTHREG00.HSD_CLOCK_MASTER_ENABLE.

1

EN

See DLO_DTX:SYNTHREG00.HSD_CLOCK_MASTER_ENABLE.

RW

0

29

RETIMER_CLRZ_MASTER

See DLO_DTX:SYNTHREG00.RETIMER_CLRZ_MASTER.

RW

0

28:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

11:6

TDC_SUBTRACT

See DLO_DTX:SYNTHREG00.TDC_SUBTRACT.

RW

0x00

5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

4:0

SYNTH_TUNE_PHASE

See DLO_DTX:SYNTHREG00.SYNTH_TUNE_PHASE.

RW

0x00



TOP:RFC_FSCA:PREDIV

Address offset

0x0000 0004

Physical address

0x4004 4004

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:PREDIV.

Type

RW

Bits

Field Name

Description

Type

Reset

31:26

PLL_PREDIV_RATIO

See DLO_DTX:PREDIV.PLL_PREDIV_RATIO.

RW

0x00

25:15

FINECALIB_PREDIV_RATIO

See DLO_DTX:PREDIV.FINECALIB_PREDIV_RATIO.

RW

0x000

14:6

MIDCALIB_PREDIV_RATIO

See DLO_DTX:PREDIV.MIDCALIB_PREDIV_RATIO.

RW

0x000

5:0

DEFAULTCALIB_PREDIV_RATIO

See DLO_DTX:PREDIV.DEFAULTCALIB_PREDIV_RATIO.

RW

0x00



TOP:RFC_FSCA:PLLM

Address offset

0x0000 0008

Physical address

0x4004 4008

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:PLLM.

Type

RW

Bits

Field Name

Description

Type

Reset

31

FREF_DITHER_EN

See DLO_DTX:PLLM.FREF_DITHER_EN.

RW

0

30:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

27:0

VAL

See DLO_DTX:PLLM.VAL.

RW

0x000 0000



TOP:RFC_FSCA:OTHERM

Address offset

0x0000 000C

Physical address

0x4004 400C

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:OTHERM.

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

MID_M_VAL

See DLO_DTX:OTHERM.MID_M_VAL.

RW

0x0000

15:0

DEF_M_VAL

See DLO_DTX:OTHERM.DEF_M_VAL.

RW

0x0000



TOP:RFC_FSCA:FINECALM

Address offset

0x0000 0010

Physical address

0x4004 4010

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:FINECALM.

Type

RW

Bits

Field Name

Description

Type

Reset

31:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

17:0

VAL

See DLO_DTX:FINECALM.VAL.

RW

0x0 0000



TOP:RFC_FSCA:FRCDCO

Address offset

0x0000 0014

Physical address

0x4004 4014

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:FRCDCO.

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

29:22

TST_DCO_FINE_REG

See DLO_DTX:FRCDCO.TST_DCO_FINE_REG.

RW

0x00

21:14

TST_DCO_SD_REG

See DLO_DTX:FRCDCO.TST_DCO_SD_REG.

RW

0x00

13:8

TST_DCO_MID_REG

See DLO_DTX:FRCDCO.TST_DCO_MID_REG.

RW

0x00

7:4

TST_DCO_COARSE_REG

See DLO_DTX:FRCDCO.TST_DCO_COARSE_REG.

RW

0x0

3:1

TST_FORCE_C_M_F_CODES

See DLO_DTX:FRCDCO.TST_FORCE_C_M_F_CODES.

RW

0x0

0

TST_FORCE_SD

See DLO_DTX:FRCDCO.TST_FORCE_SD.

RW

0



TOP:RFC_FSCA:SDCTL

Address offset

0x0000 0018

Physical address

0x4004 4018

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:SDCTL.

Type

RW

Bits

Field Name

Description

Type

Reset

31

SDM_DLY_DOUBLE_EN

See DLO_DTX:SDCTL.SDM_DLY_DOUBLE_EN.

RW

0

30

SDM_DLY_MAT_DIS

See DLO_DTX:SDCTL.SDM.

RW

0

29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

28:27

SDM_DITHER_MODE

See DLO_DTX:SDCTL.SDM_DITHER_MODE.

RW

0x0

26

SDM_ORDER_1OR2Z

See DLO_DTX:SDCTL.SDM_ORDER_1OR2Z.

Value

ENUM name

Description

0

2ND

See DLO_DTX:SDCTL.SDM_ORDER_1OR2Z.

1

1ST

See DLO_DTX:SDCTL.SDM_ORDER_1OR2Z.

RW

0

25

SDM_DEM_DIS

See DLO_DTX:SDCTL.SDM_DEM_DIS.

RW

0

24

MPX_CAN_DIS

See DLO_DTX:SDCTL.MPX_CAN_DIS.

RW

0

23

SDM_DIS

See DLO_DTX:SDCTL.SDM_DIS.

RW

0

22:20

TST_DCO_SDM_OP_REG

See DLO_DTX:SDCTL.TST_DCO_SDM_OP_REG.

RW

0x0

19

TST_FORCE_SDM_OP

See DLO_DTX:SDCTL.TST_FORCE_SDM_OP.

RW

0

18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

17:16

SDM_DLY_MODE

See DLO_DTX:SDCTL.SDM_DLY_MODE.

Value

ENUM name

Description

0x0

1DELAY

See DLO_DTX:SDCTL.SDM_DLY_MODE.

0x1

2DELAY

See DLO_DTX:SDCTL.SDM_DLY_MODE.

0x2

3DELAY

See DLO_DTX:SDCTL.SDM_DLY_MODE.

0x3

4DELAY

See DLO_DTX:SDCTL.SDM_DLY_MODE.

RW

0x0

15:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000



TOP:RFC_FSCA:DTSTCTL

Address offset

0x0000 001C

Physical address

0x4004 401C

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DTSTCTL.

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

DTST_CLK_SEL

See DLO_DTX:DTSTCTL.DTST_CLK_SEL.

Value

ENUM name

Description

0x0

NC

See DLO_DTX:DTSTCTL.DTST_CLK_SEL.

0x1

FBCNTEREN

See DLO_DTX:DTSTCTL.DTST_CLK_SEL.

RW

0x0

28:25

DTST_DATA_SEL

See DLO_DTX:DTSTCTL.DTST_DATA_SEL.

Value

ENUM name

Description

0x0

NC

See DLO_DTX:DTSTCTL.DTST_DATA_SEL.

0x1

PHASE_ERROR

See DLO_DTX:DTSTCTL.DTST_DATA_SEL.

RW

0x0

24

RDCORE_DTST_EN

See DLO_DTX:DTSTCTL.RFCORE_DTST_EN.

RW

0

23

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

22

READ_DTST_BY_SW

See DLO_DTX:DTSTCTL.READ_DTST_BY_SW.

RW

0

21

DTST_MASTER_EN

See DLO_DTX:DTSTCTL.DTST_MASTER_EN.

RW

0

20:17

DTST_DATA_SEL2

See DLO_DTX:DTSTCTL.DTST_DATA_SEL2.

Value

ENUM name

Description

0x0

ZERO

See DLO_DTX:DTSTCTL.DTST_DATA_SEL2.

0x1

PLL_MSB_LSB_TDC

See DLO_DTX:DTSTCTL.DTST_DATA_SEL2.

RW

0x0

16:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000



TOP:RFC_FSCA:DIGCFG2

Address offset

0x0000 0020

Physical address

0x4004 4020

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DIGCFG2.

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

FINE_BOT_CODE_DURING_CALIB

See DLO_DTX:DIGCFG2.FINE_BOT_CODE_DURING_CALIB.

RW

0x00

23:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

15:8

FINE_TOP_CODE_DURING_CALIB

See DLO_DTX:DIGCFG2.FINE_TOP_CODE_DURING_CALIB.

RW

0x00

7:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00



TOP:RFC_FSCA:TDCTH

Address offset

0x0000 0024

Physical address

0x4004 4024

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:TDCTH.

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

MEM_KT_INV

See DLO_DTX:TDCTH.MEM_KT_INV.

RW

0x0000

15:8

EDGESEL_TDC_TH2

See DLO_DTX:TDCTH.EDGESEL_TDC_TH2.

RW

0x00

7:0

EDGESEL_TDC_TH1

See DLO_DTX:TDCTH.EDGESEL_TDC_TH1.

RW

0x00



TOP:RFC_FSCA:LOOPCOEFF

Address offset

0x0000 0028

Physical address

0x4004 4028

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:LOOPCOEFF.

Type

RW

Bits

Field Name

Description

Type

Reset

31

PLL_COEFF_DYN_CHANGE

See DLO_DTX:LOOPCOEFF.PLL_COEFF_DYN_CHANGE.

RW

0

30:29

IIR_FILT_BW

See DLO_DTX:LOOPCOEFF.IIR_FILT_BW.

RW

0x0

28

IIR_FILTER_ORDER

See DLO_DTX:LOOPCOEFF.IIR_FILTER_ORDER.

RW

0

27

IIR_FILT_EN

See DLO_DTX:LOOPCOEFF.IIR_FILT_EN.

RW

0

26

ALPHA_HIGH_PREC

See DLO_DTX:LOOPCOEFF.ALPHA_HIGH_PREC.

RW

0

25:12

PLL_BETA

See DLO_DTX:LOOPCOEFF.PLL_BETA.

RW

0x0000

11:0

PLL_ALPHA

See DLO_DTX:LOOPCOEFF.PLL_ALPHA.

RW

0x000



TOP:RFC_FSCA:PLLCTL0

Address offset

0x0000 002C

Physical address

0x4004 402C

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:PLLCTL0.

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:21

DLY_RETIMER_INP

See DLO_DTX:PLLCTL0.DLY_RETIMER_INP.

Value

ENUM name

Description

0x0

3CLK

See DLO_DTX:PLLCTL0.DLY_RETIMER_INP.

0x1

4CLK

See DLO_DTX:PLLCTL0.DLY_RETIMER_INP.

RW

0x0

20

RECENTER_DISABLE

See DLO_DTX:PLLCTL0.RECENTER_DISABLE.

RW

0

19:14

RECENTER_THRESHOLD

See DLO_DTX:PLLCTL0.RECENTER_THRESHOLD.

RW

0x00

13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

12:10

CKVD64_LATENCY_FOR_MPX_CAN

See DLO_DTX:PLLCTL0.CKVD64_LATENCY_FOR_MPX_CAN.

RW

0x0

9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

8:7

CKVD16_LATENCY_FOR_MPX_CAN

See DLO_DTX:PLLCTL0.CKVD16_LATENCY_FOR_MPX_CAN.

RW

0x0

6

REFCLK_LATCH_EDGE_SEL

See DLO_DTX:PLLCTL0.REFCLK_LATCH_EDGE_SEL.

Value

ENUM name

Description

0

POSEDGE

See DLO_DTX:PLLCTL0.REFCLK_LATCH_EDGE_SEL.

1

NEGEDGE

See DLO_DTX:PLLCTL0.REFCLK_LATCH_EDGE_SEL.

RW

0

5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

4

TDC_SAT_ENABLE

See DLO_DTX:PLLCTL0.TDC_SAT_ENABLE.

RW

0

3:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

1:0

TDC_CALIB_AVERAGE

See DLO_DTX:PLLCTL0.TDC_CALIB_AVERAGE.

Value

ENUM name

Description

0x0

1CYCLE

See DLO_DTX:PLLCTL0.TDC_CALIB_AVERAGE.

0x1

2CYCLE

See DLO_DTX:PLLCTL0.TDC_CALIB_AVERAGE.

RW

0x0



TOP:RFC_FSCA:FSMCTL0

Address offset

0x0000 0030

Physical address

0x4004 4030

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:FSMCTL0.

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

28

PLL_FREEZE

See DLO_DTX:FSMCTL0.PLL_FREEZE.

RW

0

27

RETIMERFREEZE

See DLO_DTX:FSMCTL0.RETIMERFREEZE.

RW

0

26

FINECODEFREEZE

See DLO_DTX:FSMCTL0.FINECODEFREEZE.

RW

0

25

TDCFREEZE

See DLO_DTX:FSMCTL0.TDCFREEZE.

RW

0

24:19

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

18:13

MID_SAR_INIT_VAL

See DLO_DTX:FSMCTL0.MID_SAR_INIT_VAL.

RW

0x00

12:9

COARSE_PRECAL_VAL

See DLO_DTX:FSMCTL0.COARSE_PRECAL_VAL.

RW

0x0

8:3

MID_PRECAL_VAL

See DLO_DTX:FSMCTL0.MID_PRECAL_VAL.

RW

0x00

2

COARSE_CAL_SKIP_EN

See DLO_DTX:FSMCTL0.COARSE_CAL_SKIP_EN.

RW

0

1

MID_CAL_SKIP_EN

See DLO_DTX:FSMCTL0.MID_CAL_SKIP_EN.

RW

0

0

TDC_CAL_SKIP_EN

See DLO_DTX:FSMCTL0.TDC_CAL_SKIP_EN.

RW

0



TOP:RFC_FSCA:PETH

Address offset

0x0000 0034

Physical address

0x4004 4034

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:PETH.

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

28:24

PHASE_ERROR_LOCK_THRESH_CNT

See DLO_DTX:PETH.PHASE_ERROR_LOCK_THRESH_CNT.

RW

0x00

23:16

PHASE_ERROR_LOCK_THRESH

See DLO_DTX:PETH.PHASE_ERROR_LOCK_THRESH.

RW

0x00

15

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

14

PHASE_ERROR_DISCARD_ENABLE

See DLO_DTX:PETH.PHASE_ERROR_DISCARD_ENABLE.

RW

0

13:10

PHASE_ERROR_DISCARD_CNT

See DLO_DTX:PETH.PHASE_ERROR_DISCARD_CNT.

RW

0x0

9:0

PHASE_ERROR_DISCARD_TH

See DLO_DTX:PETH.PHASE_ERROR_DISCARD_TH.

RW

0x000



TOP:RFC_FSCA:PLLCTL1

Address offset

0x0000 0038

Physical address

0x4004 4038

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:PLLCTL1.

Type

RW

Bits

Field Name

Description

Type

Reset

31

PLL_OPEN_LOOP_MODE_WITH_1PT_MOD

See DLO_DTX:PLLCTL1.PLL_OPEN_LOOP_MODE_WITH_1PT_MOD.

RW

0

30:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:8

XTALID_FRAC

See DLO_DTX:PLLCTL1.XTALID_FRAC.

RW

0x00

7:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

5

PO_MID_SEL

See DLO_DTX:PLLCTL1.PO_MID_SEL.

RW

0

4

PO_FINE_SEL

See DLO_DTX:PLLCTL1.PO_FINE_SEL.

RW

0

3:0

PO_TAIL_RES_TRIM

See DLO_DTX:PLLCTL1.PO_TAIL_RES_TRIM.

RW

0x0



TOP:RFC_FSCA:DTX

Address offset

0x0000 003C

Physical address

0x4004 403C

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DTX.

Type

RW

Bits

Field Name

Description

Type

Reset

31:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

19:8

TXOFF

See DLO_DTX:DTX.TXOFF.

RW

0x000

7

SHAPEDZIGBEE

See DLO_DTX:DTX.SHAPEDZIGBEE.

RW

0

6

ZIGBEEMODE

See DLO_DTX:DTX.ZIGBEEMODE.

RW

0

5:4

SHAPEGAIN

See DLO_DTX:DTX.SHAPEGAIN.

RW

0x0

3:2

INPTFACTOR

See DLO_DTX:DTX.INPTFACTOR.

RW

0x0

1

INIT

See DLO_DTX:DTX.INIT.

RW

0

0

MODULEEN

See DLO_DTX:DTX.MODULEEN.

RW

0



TOP:RFC_FSCA:DTX00

Address offset

0x0000 0040

Physical address

0x4004 4040

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DTX00.

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

SHAPE3

See DLO_DTX:DTX00.SHAPE3.

RW

0x00

23:16

SHAPE2

See DLO_DTX:DTX00.SHAPE2.

RW

0x00

15:8

SHAPE1

See DLO_DTX:DTX00.SHAPE1.

RW

0x00

7:0

SHAPE0

See DLO_DTX:DTX00.SHAPE0.

RW

0x00



TOP:RFC_FSCA:DTX01

Address offset

0x0000 0044

Physical address

0x4004 4044

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DTX01.

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

SHAPE7

See DLO_DTX:DTX01.SHAPE7.

RW

0x00

23:16

SHAPE6

See DLO_DTX:DTX01.SHAPE6.

RW

0x00

15:8

SHAPE5

See DLO_DTX:DTX01.SHAPE5.

RW

0x00

7:0

SHAPE4

See DLO_DTX:DTX01.SHAPE4.

RW

0x00



TOP:RFC_FSCA:DTX02

Address offset

0x0000 0048

Physical address

0x4004 4048

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DTX02.

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

SHAPE11

See DLO_DTX:DTX02.SHAPE11.

RW

0x00

23:16

SHAPE10

See DLO_DTX:DTX02.SHAPE10.

RW

0x00

15:8

SHAPE9

See DLO_DTX:DTX02.SHAPE9.

RW

0x00

7:0

SHAPE8

See DLO_DTX:DTX02.SHAPE8.

RW

0x00



TOP:RFC_FSCA:DTX03

Address offset

0x0000 004C

Physical address

0x4004 404C

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DTX03.

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

SHAPE15

See DLO_DTX:DTX03.SHAPE15.

RW

0x00

23:16

SHAPE14

See DLO_DTX:DTX03.SHAPE14.

RW

0x00

15:8

SHAPE13

See DLO_DTX:DTX03.SHAPE13.

RW

0x00

7:0

SHAPE12

See DLO_DTX:DTX03.SHAPE12.

RW

0x00



TOP:RFC_FSCA:DTX04

Address offset

0x0000 0050

Physical address

0x4004 4050

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DTX04.

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

SHAPE19

See DLO_DTX:DTX04.SHAPE19.

RW

0x00

23:16

SHAPE18

See DLO_DTX:DTX04.SHAPE18.

RW

0x00

15:8

SHAPE17

See DLO_DTX:DTX04.SHAPE17.

RW

0x00

7:0

SHAPE16

See DLO_DTX:DTX04.SHAPE16.

RW

0x00



TOP:RFC_FSCA:DTX05

Address offset

0x0000 0054

Physical address

0x4004 4054

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DTX05.

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

SHAPE23

See DLO_DTX:DTX05.SHAPE23.

RW

0x00

23:16

SHAPE22

See DLO_DTX:DTX05.SHAPE22.

RW

0x00

15:8

SHAPE21

See DLO_DTX:DTX05.SHAPE21.

RW

0x00

7:0

SHAPE20

See DLO_DTX:DTX05.SHAPE20.

RW

0x00



TOP:RFC_FSCA:DTXGAIN

Address offset

0x0000 0058

Physical address

0x4004 4058

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:DTXGAIN.

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

CKVD64_LATENCY_FOR_MPX_ADD

See DLO_DTX:DTXGAIN.CKVD64_LATENCY_FOR_MPX_ADD.

RW

0x0

29:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

ADD_PATH_GAIN

See DLO_DTX:DTXGAIN.ADD_PATH_GAIN.

RW

0x0000



TOP:RFC_FSCA:ANADIV

Address offset

0x0000 005C

Physical address

0x4004 405C

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:ANADIV.

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

CORNER_CAP

See DLO_DTX:ANADIV.CORNER_CAP.

RW

0x0

29

EN_KICK_START

See DLO_DTX:ANADIV.EN_KICK_START.

RW

0

28

DIV_BIAS_MODE

See DLO_DTX:ANADIV.DIV_BIAS_MODE.

RW

0

27:26

TDC_CALIB_PERIOD

See DLO_DTX:ANADIV.TDC_CALIB_PERIOD.

RW

0x0

25:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

23

RETIMER_ISO

See DLO_DTX:ANADIV.RETIMER_ISO.

RW

0

22:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

16:14

CTL_NM_IREF

See DLO_DTX:ANADIV.CTL_NM_IREF.

RW

0x0

13:11

CTL_PM_IREF

See DLO_DTX:ANADIV.CTL_PM_IREF.

RW

0x0

10:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

6

EN_ADC

See DLO_DTX:ANADIV.EN_ADC.

RW

0

5

EN_SYNTH

See DLO_DTX:ANADIV.EN_SYNTH.

RW

0

4

EN_TX_PH180

See DLO_DTX:ANADIV.EN_TX_PH180.

RW

0

3

EN_TX_PH0

See DLO_DTX:ANADIV.EN_TX_PH0.

RW

0

2

EN_RX_Q

See DLO_DTX:ANADIV.EN_RX_Q.

RW

0

1

EN_RX_I

See DLO_DTX:ANADIV.EN_RX_I.

RW

0

0

DIV_BUF_ENABLE

See DLO_DTX:ANADIV.DIV_BUF_ENABLE.

RW

0



TOP:RFC_FSCA:PLLCTL2

Address offset

0x0000 0060

Physical address

0x4004 4060

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:PLLCTL2.

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000



TOP:RFC_FSCA:FSMCTL1

Address offset

0x0000 0064

Physical address

0x4004 4064

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:FSMCTL1.

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

FINE_START_CODE

See DLO_DTX:FSMCTL1.FINE_START_CODE.

RW

0x00



TOP:RFC_FSCA:FSMCTL2

Address offset

0x0000 0068

Physical address

0x4004 4068

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:FSMCTL2.

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000



TOP:RFC_FSCA:SPARE0

Address offset

0x0000 006C

Physical address

0x4004 406C

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:SPARE0.

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0000 0000



TOP:RFC_FSCA:STAT0

Address offset

0x0000 0070

Physical address

0x4004 4070

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:STAT0.

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

FB_CNT

See DLO_DTX:STAT0.FB_CNT.

RO

0x0000



TOP:RFC_FSCA:STAT1

Address offset

0x0000 0074

Physical address

0x4004 4074

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:STAT1.

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

SYNTH_TUNE_STAT

See DLO_DTX:STAT0.SYNTH_TUNE_STAT.

RO

0x0000



TOP:RFC_FSCA:STAT2

Address offset

0x0000 0078

Physical address

0x4004 4078

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:STAT2.

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

FDCO_SPAN

See DLO_DTX:STAT0.FDCO_SPAN.

RO

0x0000 0000



TOP:RFC_FSCA:STAT3

Address offset

0x0000 007C

Physical address

0x4004 407C

Instance

RFC_FSCA

Description

Alias register for DLO_DTX:STAT3.

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

DTST_READ

See DLO_DTX:STAT3.DTST_READ.

RO

0x0000

15:0

TDC_CALIB_AVG

See DLO_DTX:STAT3.TDC_CALIB_AVG.

RO

0x0000



TOP:RFC_FSCA:DDICTL

Address offset

0x0000 0100

Physical address

0x4004 4100

Instance

RFC_FSCA

Description

DDI Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

RESTART

Resets the DDI master, which is connected to the [ANATOP_MMAP::DLO_DTX.*] register bank, back to idle state.

RW

0

0

SAFEPARK

Parks the DDI bus to a safe state. To be used before e.g. entering power-down of the RF Core power domain.

RW

0



TOP:RFC_FSCA:DDISTATUS

Address offset

0x0000 0104

Physical address

0x4004 4104

Instance

RFC_FSCA

Description

DDI Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

BUSY

DDI interface busy indicator. Reads as 1 when a transaction is active and interface is busy.

RO

0



TOP:RFC_FSCA:ADI1CTL

Address offset

0x0000 0108

Physical address

0x4004 4108

Instance

RFC_FSCA

Description

ADI Interface 1 Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

WRSIZE

Transaction write size. (The read size is always half register, i.e. 4 bits).

Value

ENUM name

Description

0

FULL

Full register, direct write (8 bits data)

1

HALF

Half register, masked write (4 bits write mask + 4 bits data)

RW

0

0

WREN

Write enable configuration.

Value

ENUM name

Description

0

READ

Enable register read mode

1

WRITE

Enable register write mode

RW

0



TOP:RFC_FSCA:ADI1CLK

Address offset

0x0000 010C

Physical address

0x4004 410C

Instance

RFC_FSCA

Description

ADI Interface 1 Clock

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

CLK

Generates one clock transaction on the ADI when written to 1. To be used after configuring the desired transaction type in ADI1CTL and address in ADI1ADDRWRDATA registers to perform either one read or write transaction.

RW

0



TOP:RFC_FSCA:ADI1CLRREQ

Address offset

0x0000 0110

Physical address

0x4004 4110

Instance

RFC_FSCA

Description

ADI Interface 1 Clear Request

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

REQ0

Clears the REQ toggler signal to zero.

RW

0



TOP:RFC_FSCA:ADI1ADDRWRDATA

Address offset

0x0000 0114

Physical address

0x4004 4114

Instance

RFC_FSCA

Description

ADI Interface 1 Address and Write Data

Type

RW

Bits

Field Name

Description

Type

Reset

31:13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

12:8

ADDR

The ADI1 is connected to the [ANATOP_MMAP::ADI_1_SYNTH.*] analog register bank, and uses addresses in range 0..31. The register bank contains 16 registers, each of 8 bits. The address number refers to the register bank in half register (half byte) increments. E.g. address 0 means bits [3:0] of analog register 0, address 1 means bits [7:4] of analog register 0, address 2 means bits [3:0] of analog register 1, (...), and finally, the address 31 means bits [7:4] of analog register 15.

RW

0x00

7:0

WRDATA

ADI1 write data when write mode is enabled. For full register write accesses (ADI1CTL.WRSIZE = 0), this should be the 8 bits data to be written to the two half registers at address ADDR and ADDR + 1. For half register masked write (ADI1CTL.WRSIZE = 1), this should be concatenation of a 4 bit write mask and 4 bits data. The order of the write mask and the data depends on the value of the address. When ADDR is an even value (i.e. referring lower half of a register), the WRDATA should contain the write mask in bits [7:4] and data in [3:0]. When ADDR is an odd value (i.e. referring to upper half of a register), the WRDATA should contain the data in bits [7:4] and write mask in [3:0]. For half register write accesses, only the bits where the write mask bits are set to 1 will be written using the data value, and other register bits will remain unchanged.

RW

0x00



TOP:RFC_FSCA:ADI1RD

Address offset

0x0000 0118

Physical address

0x4004 4118

Instance

RFC_FSCA

Description

ADI Interface 1 Read Data

Type

RO

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4

ACK

Self-timed read transaction is done. Read data in RDDATA is not valid until this reads as 1.

RO

0

3:0

RDDATA

ADI half register read data.

RO

0x0



TOP:RFC_FSCA:DIVCTRL

Address offset

0x0000 011C

Physical address

0x4004 411C

Instance

RFC_FSCA

Description

Serial Divider Control Register

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

BUSY

Divider hardware is busy and output result in QUOTIENT is not yet ready.

RO

0



TOP:RFC_FSCA:DIVIDEND

Address offset

0x0000 0120

Physical address

0x4004 4120

Instance

RFC_FSCA

Description

Serial Divider Dividend Register

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

DIVIDEND

Dividend input (write only, reads as 0x0)

RW

0x0000 0000



TOP:RFC_FSCA:DIVISOR

Address offset

0x0000 0124

Physical address

0x4004 4124

Instance

RFC_FSCA

Description

Serial Divider Divisor Register

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

DIVISOR

Divisor input

RW

0x0000 0000



TOP:RFC_FSCA:QUOTIENT

Address offset

0x0000 0128

Physical address

0x4004 4128

Instance

RFC_FSCA

Description

Serial Divider Quotient Register

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

QUOTIENT

Quotient output. Gives the result from the following calculation: QUOTIENT = DIVIDEND / DIVISOR.

RO

0x0000 0000