DLO_DTX

Instance: DLO_DTX
Component: DLO_DTX
Base address: 0x40044000

 

DLO_DTX Component

 

TOP:DLO_DTX Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DTX05

RW

32

0x0000 0000

0x0000 0054

0x4004 4054

FSMCTL1

RW

32

0x0000 0000

0x0000 0064

0x4004 4064

SPARE0

RW

32

0x0000 0000

0x0000 006C

0x4004 406C

TOP:DLO_DTX Register Descriptions

TOP:DLO_DTX:DTX05

Address offset

0x0000 0054

Physical address

0x4004 4054

Instance

DLO_DTX

Description

Digital TX 5

MODSHAPE5

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

SHAPE23

Shape element 23

RW

0x00

23:16

SHAPE22

Shape element 22

RW

0x00

15:8

SHAPE21

Shape element 21

RW

0x00

7:0

SHAPE20

Shape element 20

RW

0x00



TOP:DLO_DTX:FSMCTL1

Address offset

0x0000 0064

Physical address

0x4004 4064

Instance

DLO_DTX

Description

FSM Control 1

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x00 0000

7:0

FINE_START_CODE

Starting code of fine bank. Used as a starting point for all calibration and at the start of PLL state. Remember to set FINE_START_CODE in the middle of DIGCFG2.FINE_BOT_CODE_DURING_CALIB and DIGCFG2.FINE_TOP_CODE_DURING_CALIB.

Encoding: Binary

RW

0x00



TOP:DLO_DTX:SPARE0

Address offset

0x0000 006C

Physical address

0x4004 406C

Instance

DLO_DTX

Description

Spare 0

Spare bits routed to analog. Can be used for analog configuration

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0000 0000