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prcm.c
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1 /******************************************************************************
2 * Filename: prcm.c
3 * Revised: 2015-01-13 16:59:55 +0100 (ti, 13 jan 2015)
4 * Revision: 42365
5 *
6 * Description: Driver for the PRCM.
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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37 ******************************************************************************/
38 
39 #include <driverlib/prcm.h>
40 
41 //*****************************************************************************
42 //
43 // Handle support for DriverLib in ROM:
44 // This section will undo prototype renaming made in the header file
45 //
46 //*****************************************************************************
47 #ifndef DRIVERLIB_GENERATE_ROM
48  #undef PRCMInfClockConfigureSet
49  #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet
50  #undef PRCMInfClockConfigureGet
51  #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet
52  #undef PRCMClockConfigureSet
53  #define PRCMClockConfigureSet NOROM_PRCMClockConfigureSet
54  #undef PRCMClockConfigureGet
55  #define PRCMClockConfigureGet NOROM_PRCMClockConfigureGet
56  #undef PRCMAudioClockConfigSet
57  #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet
58  #undef PRCMAudioClockConfigSetOverride
59  #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride
60  #undef PRCMPowerDomainOn
61  #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn
62  #undef PRCMPowerDomainOff
63  #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff
64  #undef PRCMPeripheralRunEnable
65  #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable
66  #undef PRCMPeripheralRunDisable
67  #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable
68  #undef PRCMPeripheralSleepEnable
69  #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable
70  #undef PRCMPeripheralSleepDisable
71  #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable
72  #undef PRCMPeripheralDeepSleepEnable
73  #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable
74  #undef PRCMPeripheralDeepSleepDisable
75  #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable
76  #undef PRCMPowerDomainStatus
77  #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus
78  #undef PRCMDeepSleep
79  #define PRCMDeepSleep NOROM_PRCMDeepSleep
80  #undef PRCMRetentionEnable
81  #define PRCMRetentionEnable NOROM_PRCMRetentionEnable
82  #undef PRCMRetentionDisable
83  #define PRCMRetentionDisable NOROM_PRCMRetentionDisable
84 #endif
85 
86 
87 //*****************************************************************************
88 //
89 // Arrays that maps the "peripheral set" number (which is stored in the
90 // third nibble of the PRCM_PERIPH_* defines) to the PRCM register that
91 // contains the relevant bit for that peripheral.
92 //
93 //*****************************************************************************
94 
95 // Run mode registers
96 static const uint32_t g_pui32RCGCRegs[] =
97 {
105 };
106 
107 // Sleep mode registers
108 static const uint32_t g_pui32SCGCRegs[] =
109 {
117 };
118 
119 // Deep sleep mode registers
120 static const uint32_t g_pui32DCGCRegs[] =
121 {
129 };
130 
131 //*****************************************************************************
132 //
133 // This macro extracts the array index out of the peripheral number
134 //
135 //*****************************************************************************
136 #define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf)
137 
138 //*****************************************************************************
139 //
140 // This macro extracts the peripheral instance number and generates bit mask
141 //
142 //*****************************************************************************
143 #define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0xf))
144 
145 
146 //*****************************************************************************
147 //
149 //
150 //*****************************************************************************
151 void
152 PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)
153 {
154  uint32_t ui32Divisor;
155 
156  //
157  // Check the arguments.
158  //
159  ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) ||
160  (ui32ClkDiv == PRCM_CLOCK_DIV_2) ||
161  (ui32ClkDiv == PRCM_CLOCK_DIV_8) ||
162  (ui32ClkDiv == PRCM_CLOCK_DIV_32));
163  ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
164  (ui32PowerMode == PRCM_SLEEP_MODE) ||
165  (ui32PowerMode == PRCM_DEEP_SLEEP_MODE));
166 
167  ui32Divisor = 0;
168 
169  //
170  // Find the correct division factor.
171  //
172  if(ui32ClkDiv == PRCM_CLOCK_DIV_1)
173  {
174  ui32Divisor = 0x0;
175  }
176  else if(ui32ClkDiv == PRCM_CLOCK_DIV_2)
177  {
178  ui32Divisor = 0x1;
179  }
180  else if(ui32ClkDiv == PRCM_CLOCK_DIV_8)
181  {
182  ui32Divisor = 0x2;
183  }
184  else if(ui32ClkDiv == PRCM_CLOCK_DIV_32)
185  {
186  ui32Divisor = 0x3;
187  }
188 
189  //
190  // Determine the correct power mode set the division factor accordingly.
191  //
192  if(ui32PowerMode == PRCM_RUN_MODE)
193  {
194  HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor;
195  }
196  else if(ui32PowerMode == PRCM_SLEEP_MODE)
197  {
198  HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor;
199  }
200  else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
201  {
202  HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor;
203  }
204 }
205 
206 //*****************************************************************************
207 //
209 //
210 //*****************************************************************************
211 uint32_t
212 PRCMInfClockConfigureGet(uint32_t ui32PowerMode)
213 {
214  uint32_t ui32ClkDiv;
215  uint32_t ui32Divisor;
216 
217  //
218  // Check the arguments.
219  //
220  ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
221  (ui32PowerMode == PRCM_SLEEP_MODE) ||
222  (ui32PowerMode == PRCM_DEEP_SLEEP_MODE));
223 
224  ui32ClkDiv = 0;
225  ui32Divisor = 0;
226 
227  //
228  // Determine the correct power mode.
229  //
230  if(ui32PowerMode == PRCM_RUN_MODE)
231  {
232  ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR);
233  }
234  else if(ui32PowerMode == PRCM_SLEEP_MODE)
235  {
236  ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS);
237  }
238  else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
239  {
240  ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS);
241  }
242 
243  //
244  // Find the correct division factor.
245  //
246  if(ui32ClkDiv == 0x0)
247  {
248  ui32Divisor = PRCM_CLOCK_DIV_1;
249  }
250  else if(ui32ClkDiv == 0x1)
251  {
252  ui32Divisor = PRCM_CLOCK_DIV_2;
253  }
254  else if(ui32ClkDiv == 0x2)
255  {
256  ui32Divisor = PRCM_CLOCK_DIV_8;
257  }
258  else if(ui32ClkDiv == 0x3)
259  {
260  ui32Divisor = PRCM_CLOCK_DIV_32;
261  }
262 
263  //
264  // Return the clock divison factor.
265  //
266  return ui32Divisor;
267 }
268 
269 //*****************************************************************************
270 //
273 //
274 //*****************************************************************************
275 void
276 PRCMClockConfigureSet(uint32_t ui32Domains, uint32_t ui32ClkDiv)
277 {
278  uint32_t ui32Reg;
279 
280  //
281  // Check the arguments.
282  //
283  ASSERT((ui32Domains & PRCM_DOMAIN_SYSBUS) ||
284  (ui32Domains & PRCM_DOMAIN_CPU) ||
285  (ui32Domains & PRCM_DOMAIN_PERIPH) ||
286  (ui32Domains & PRCM_DOMAIN_TIMER) ||
287  (ui32Domains & PRCM_DOMAIN_SERIAL));
288  ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) ||
289  (ui32ClkDiv == PRCM_CLOCK_DIV_2) ||
290  (ui32ClkDiv == PRCM_CLOCK_DIV_4) ||
291  (ui32ClkDiv == PRCM_CLOCK_DIV_8) ||
292  (ui32ClkDiv == PRCM_CLOCK_DIV_16) ||
293  (ui32ClkDiv == PRCM_CLOCK_DIV_32) ||
294  (ui32ClkDiv == PRCM_CLOCK_DIV_64) ||
295  (ui32ClkDiv == PRCM_CLOCK_DIV_128) ||
296  (ui32ClkDiv == PRCM_CLOCK_DIV_256));
297 
298  //
299  // Configure the selected clock dividers.
300  //
301  if(ui32Domains & PRCM_DOMAIN_SYSBUS)
302  {
303  ui32Reg = PRCM_O_SYSBUSCLKDIV;
304  HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv;
305  }
306  if(ui32Domains & PRCM_DOMAIN_CPU)
307  {
308  ui32Reg = PRCM_O_CPUCLKDIV;
309  HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv;
310  }
311  if(ui32Domains & PRCM_DOMAIN_PERIPH)
312  {
313  ui32Reg = PRCM_O_PERBUSCPUCLKDIV;
314  HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv;
315  }
316  if(ui32Domains & PRCM_DOMAIN_SERIAL)
317  {
318  ui32Reg = PRCM_O_PERDMACLKDIV;
319  HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv;
320  }
321  if(ui32Domains & PRCM_DOMAIN_TIMER)
322  {
323  ui32Reg = PRCM_O_GPTCLKDIV;
324  HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv;
325  }
326 }
327 
328 //*****************************************************************************
329 //
332 //
333 //*****************************************************************************
334 uint32_t
335 PRCMClockConfigureGet(uint32_t ui32Domain)
336 {
337  uint32_t ui32ClkDiv;
338 
339  //
340  // Check the arguments.
341  //
342  ASSERT((ui32Domain == PRCM_DOMAIN_SYSBUS) ||
343  (ui32Domain == PRCM_DOMAIN_CPU) ||
344  (ui32Domain == PRCM_DOMAIN_PERIPH) ||
345  (ui32Domain == PRCM_DOMAIN_TIMER) ||
346  (ui32Domain == PRCM_DOMAIN_SERIAL));
347 
348  ui32ClkDiv = 0;
349 
350  //
351  // Find the correct sub system.
352  //
353  if(ui32Domain == PRCM_DOMAIN_SYSBUS)
354  {
355  ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_SYSBUSCLKDIV);
356  }
357  else if(ui32Domain == PRCM_DOMAIN_CPU)
358  {
359  ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_CPUCLKDIV);
360  }
361  else if(ui32Domain == PRCM_DOMAIN_PERIPH)
362  {
363  ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERBUSCPUCLKDIV);
364  }
365  else if(ui32Domain == PRCM_DOMAIN_SERIAL)
366  {
367  ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERDMACLKDIV);
368  }
369  else if(ui32Domain == PRCM_DOMAIN_TIMER)
370  {
371  ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV);
372  }
373 
374  //
375  // Return the clock configuration.
376  //
377  return(ui32ClkDiv);
378 }
379 
380 //*****************************************************************************
381 //
383 //
384 //*****************************************************************************
385 void
386 PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)
387 {
388  uint32_t ui32Reg;
389  uint32_t ui32MstDiv;
390  uint32_t ui32BitDiv;
391  uint32_t ui32WordDiv;
392 
393  //
394  // Check the arguments.
395  //
397  ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) ||
398  (ui32SampleRate == I2S_SAMPLE_RATE_24K) ||
399  (ui32SampleRate == I2S_SAMPLE_RATE_32K) ||
400  (ui32SampleRate == I2S_SAMPLE_RATE_48K));
401 
402  ui32MstDiv = 0;
403  ui32BitDiv = 0;
404  ui32WordDiv = 0;
405 
406  //
407  // Make sure the audio clock generation is disabled before reconfiguring.
408  //
410 
411  //
412  // Define the clock division factors for the audio interface.
413  //
414  switch(ui32SampleRate)
415  {
416  case I2S_SAMPLE_RATE_16K :
417  ui32MstDiv = 6;
418  ui32BitDiv = 60;
419  ui32WordDiv = 25;
420  break;
421  case I2S_SAMPLE_RATE_24K :
422  ui32MstDiv = 4;
423  ui32BitDiv = 40;
424  ui32WordDiv = 25;
425  break;
426  case I2S_SAMPLE_RATE_32K :
427  ui32MstDiv = 3;
428  ui32BitDiv = 30;
429  ui32WordDiv = 25;
430  break;
431  case I2S_SAMPLE_RATE_48K :
432  ui32MstDiv = 2;
433  ui32BitDiv = 20;
434  ui32WordDiv = 25;
435  break;
436  }
437 
438  //
439  // Make sure to compensate the Frame clock division factor if using single
440  // phase format.
441  //
442  if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
443  {
444  ui32WordDiv -= 1;
445  }
446 
447  //
448  // Write the clock divison factors.
449  //
450  HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
451  HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
452  HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
453 
454  //
455  // Configure the Word clock format and polarity.
456  //
459  HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
460 }
461 
462 //*****************************************************************************
463 //
465 //
466 //*****************************************************************************
467 
468 void
469 PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv,
470  uint32_t ui32BitDiv, uint32_t ui32WordDiv)
471 {
472  uint32_t ui32Reg;
473 
474  //
475  // Check the arguments.
476  //
478 
479  //
480  // Make sure the audio clock generation is disabled before reconfiguring.
481  //
483 
484  //
485  // Make sure to compensate the Frame clock division factor if using single
486  // phase format.
487  //
488  if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
489  {
490  ui32WordDiv -= 1;
491  }
492 
493  //
494  // Write the clock divison factors.
495  //
496  HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
497  HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
498  HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
499 
500  //
501  // Configure the Word clock format and polarity.
502  //
505  HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
506 }
507 
508 //*****************************************************************************
509 //
511 //
512 //*****************************************************************************
513 void
514 PRCMPowerDomainOn(uint32_t ui32Domains)
515 {
516  //
517  // Check the arguments.
518  //
519  ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
520  (ui32Domains & PRCM_DOMAIN_SERIAL) ||
521  (ui32Domains & PRCM_DOMAIN_PERIPH) ||
522  (ui32Domains & PRCM_DOMAIN_CPU) ||
523  (ui32Domains & PRCM_DOMAIN_VIMS));
524 
525  //
526  // Assert the request to power on the right domains.
527  //
528  if(ui32Domains & PRCM_DOMAIN_RFCORE)
529  {
530  HWREG(PRCM_BASE +
533  }
534  if(ui32Domains & PRCM_DOMAIN_SERIAL)
535  {
536  HWREG(PRCM_BASE +
538  }
539  if(ui32Domains & PRCM_DOMAIN_PERIPH)
540  {
541  HWREG(PRCM_BASE +
543  }
544  if(ui32Domains & PRCM_DOMAIN_VIMS)
545  {
546  HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) |=
548  }
549  if(ui32Domains & PRCM_DOMAIN_CPU)
550  {
552  }
553 }
554 
555 //*****************************************************************************
556 //
558 //
559 //*****************************************************************************
560 void
561 PRCMPowerDomainOff(uint32_t ui32Domains)
562 {
563  //
564  // Check the arguments.
565  //
566  ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
567  (ui32Domains & PRCM_DOMAIN_SERIAL) ||
568  (ui32Domains & PRCM_DOMAIN_PERIPH) ||
569  (ui32Domains & PRCM_DOMAIN_CPU) ||
570  (ui32Domains & PRCM_DOMAIN_VIMS));
571 
572  //
573  // Assert the request to power off the right domains.
574  //
575  if(ui32Domains & PRCM_DOMAIN_RFCORE)
576  {
577  HWREG(PRCM_BASE +
580  }
581  if(ui32Domains & PRCM_DOMAIN_SERIAL)
582  {
583  HWREG(PRCM_BASE +
585  }
586  if(ui32Domains & PRCM_DOMAIN_PERIPH)
587  {
588  HWREG(PRCM_BASE +
590  }
591  if(ui32Domains & PRCM_DOMAIN_VIMS)
592  {
593  HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) &=
595  }
596  if(ui32Domains & PRCM_DOMAIN_CPU)
597  {
599  }
600 }
601 
602 //*****************************************************************************
603 //
605 //
606 //*****************************************************************************
607 void
608 PRCMPeripheralRunEnable(uint32_t ui32Peripheral)
609 {
610  //
611  // Check the arguments.
612  //
613  ASSERT(PRCMPeripheralValid(ui32Peripheral));
614 
615  //
616  // Enable module in Run Mode.
617  //
618  HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
619  PRCM_PERIPH_MASKBIT(ui32Peripheral);
620 }
621 
622 //*****************************************************************************
623 //
625 //
626 //*****************************************************************************
627 void
628 PRCMPeripheralRunDisable(uint32_t ui32Peripheral)
629 {
630  //
631  // Check the arguments.
632  //
633  ASSERT(PRCMPeripheralValid(ui32Peripheral));
634 
635  //
636  // Disable module in Run Mode.
637  //
638  HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
639  ~PRCM_PERIPH_MASKBIT(ui32Peripheral);
640 }
641 
642 //*****************************************************************************
643 //
645 //
646 //*****************************************************************************
647 void
648 PRCMPeripheralSleepEnable(uint32_t ui32Peripheral)
649 {
650  //
651  // Check the arguments.
652  //
653  ASSERT(PRCMPeripheralValid(ui32Peripheral));
654 
655  //
656  // Enable this peripheral in sleep mode.
657  //
658  HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
659  PRCM_PERIPH_MASKBIT(ui32Peripheral);
660 }
661 
662 //*****************************************************************************
663 //
665 //
666 //*****************************************************************************
667 void
668 PRCMPeripheralSleepDisable(uint32_t ui32Peripheral)
669 {
670  //
671  // Check the arguments.
672  //
673  ASSERT(PRCMPeripheralValid(ui32Peripheral));
674 
675  //
676  // Disable this peripheral in sleep mode
677  //
678  HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
679  ~PRCM_PERIPH_MASKBIT(ui32Peripheral);
680 }
681 
682 //*****************************************************************************
683 //
685 //
686 //*****************************************************************************
687 void
688 PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral)
689 {
690  //
691  // Check the arguments.
692  //
693  ASSERT(PRCMPeripheralValid(ui32Peripheral));
694 
695  //
696  // Enable this peripheral in deep-sleep mode.
697  //
698  HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
699  PRCM_PERIPH_MASKBIT(ui32Peripheral);
700 }
701 
702 //*****************************************************************************
703 //
705 //
706 //*****************************************************************************
707 void
708 PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral)
709 {
710  //
711  // Check the arguments.
712  //
713  ASSERT(PRCMPeripheralValid(ui32Peripheral));
714 
715  //
716  // Disable this peripheral in Deep Sleep mode.
717  //
718  HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
719  ~PRCM_PERIPH_MASKBIT(ui32Peripheral);
720 }
721 
722 //*****************************************************************************
723 //
725 //
726 //*****************************************************************************
727 uint32_t
728 PRCMPowerDomainStatus(uint32_t ui32Domains)
729 {
730  bool bStatus;
731  uint32_t ui32StatusRegister0;
732  uint32_t ui32StatusRegister1;
733 
734  //
735  // Check the arguments.
736  //
737  ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE |
740 
741  bStatus = true;
742  ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0);
743  ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1);
744 
745  //
746  // Return the correct power status.
747  //
748  if(ui32Domains & PRCM_DOMAIN_RFCORE)
749  {
750  bStatus = bStatus &&
751  ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) ||
752  (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON));
753  }
754  if(ui32Domains & PRCM_DOMAIN_SERIAL)
755  {
756  bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON);
757  }
758  if(ui32Domains & PRCM_DOMAIN_PERIPH)
759  {
760  bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON);
761  }
762 
763  //
764  // Return the status.
765  //
766  return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF);
767 }
768 
769 //*****************************************************************************
770 //
772 //
773 //*****************************************************************************
774 void
776 {
777  //
778  // Enable deep-sleep.
779  //
780  HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
781 
782  //
783  // Wait for an interrupt.
784  //
785  CPUwfi();
786 
787  //
788  // Disable deep-sleep so that a future sleep will work correctly.
789  //
790  HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
791 }
792 
793 //*****************************************************************************
794 //
796 //
797 //*****************************************************************************
798 void
799 PRCMRetentionEnable(uint32_t ui32PowerDomain)
800 {
801  uint32_t ui32Retention;
802 
803  //
804  // Check the arguments.
805  //
806  ASSERT((PRCM_DOMAIN_PERIPH & ui32PowerDomain) ||
807  (PRCM_DOMAIN_CPU & ui32PowerDomain));
808 
809  //
810  // Get the current register.
811  //
812  ui32Retention = HWREG(PRCM_BASE + PRCM_O_PDRETEN);
813 
814  //
815  // Set the bits.
816  //
817  if(PRCM_DOMAIN_PERIPH & ui32PowerDomain)
818  {
819  ui32Retention |= PRCM_PDRETEN_PERIPH;
820  }
821  if(PRCM_DOMAIN_CPU & ui32PowerDomain)
822  {
823  ui32Retention |= PRCM_PDRETEN_CPU;
824  }
825 
826  //
827  // Reconfigure retention.
828  //
829  HWREG(PRCM_BASE + PRCM_O_PDRETEN) = ui32Retention;
830 
831  //
832  // Get the current register values.
833  //
834  ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN);
835 
836  //
837  // Enable retention on RF core SRAM.
838  //
839  if(PRCM_DOMAIN_RFCORE & ui32PowerDomain)
840  {
841  ui32Retention |= PRCM_RAMRETEN_RFC_M;
842  }
843 
844  //
845  // Enable retention on VIMS cache.
846  //
847  if(PRCM_DOMAIN_VIMS & ui32PowerDomain)
848  {
849  ui32Retention |= PRCM_RAMRETEN_VIMS_M;
850  }
851 
852  //
853  // Reconfigure retention.
854  //
855  HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention;
856 }
857 
858 //*****************************************************************************
859 //
861 //
862 //*****************************************************************************
863 void
864 PRCMRetentionDisable(uint32_t ui32PowerDomain)
865 {
866  uint32_t ui32Retention;
867 
868  //
869  // Check the arguments.
870  //
871  ASSERT((PRCM_DOMAIN_PERIPH & ui32PowerDomain) ||
872  (PRCM_DOMAIN_CPU & ui32PowerDomain));
873 
874  //
875  // Get the current register.
876  //
877  ui32Retention = HWREG(PRCM_BASE + PRCM_O_PDRETEN);
878 
879  //
880  // Clear the bits.
881  //
882  if(PRCM_DOMAIN_PERIPH & ui32PowerDomain)
883  {
884  ui32Retention &= ~PRCM_PDRETEN_PERIPH;
885  }
886  if(PRCM_DOMAIN_CPU & ui32PowerDomain)
887  {
888  ui32Retention &= ~PRCM_PDRETEN_CPU;
889  }
890 
891  //
892  // Reconfigure retention.
893  //
894  HWREG(PRCM_BASE + PRCM_O_PDRETEN) = ui32Retention;
895 
896  //
897  // Get the current register values
898  //
899  ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN);
900 
901  //
902  // Disable retention on RF core SRAM
903  //
904  if(PRCM_DOMAIN_RFCORE & ui32PowerDomain)
905  {
906  ui32Retention &= ~PRCM_RAMRETEN_RFC_M;
907  }
908 
909  //
910  // Disable retention on VIMS cache
911  //
912  if(PRCM_DOMAIN_VIMS & ui32PowerDomain)
913  {
914  ui32Retention &= ~PRCM_RAMRETEN_VIMS_M;
915  }
916 
917  //
918  // Reconfigure retention.
919  //
920  HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention;
921 }
#define PRCM_CLOCK_DIV_64
Definition: prcm.h:128
__STATIC_INLINE void PRCMAudioClockDisable(void)
Disable the audio clock generation.
Definition: prcm.h:490
#define I2S_SAMPLE_RATE_48K
Definition: prcm.h:176
#define I2S_SAMPLE_RATE_16K
Definition: prcm.h:173
uint32_t PRCMClockConfigureGet(uint32_t ui32Domain)
Get the clock configuration for a specific sub system in the MCU Voltage Domain.
Definition: prcm.c:335
#define PRCM_CLOCK_DIV_4
Definition: prcm.h:124
uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode)
Use this function to retreive the set infrastructure clock configuration.
Definition: prcm.c:212
#define I2S_SAMPLE_RATE_24K
Definition: prcm.h:174
#define ASSERT(expr)
Definition: debug.h:65
#define PRCM_DEEP_SLEEP_MODE
Definition: prcm.h:115
uint32_t PRCMPowerDomainStatus(uint32_t ui32Domains)
Get the status for a specific power domain.
Definition: prcm.c:728
#define PRCM_CLOCK_DIV_8
Definition: prcm.h:125
#define PRCM_DOMAIN_VIMS
Definition: prcm.h:146
#define PRCM_CLOCK_DIV_256
Definition: prcm.h:130
#define PRCM_WCLK_SINGLE_PHASE
Definition: prcm.h:169
void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral)
Enables a peripheral in sleep mode.
Definition: prcm.c:648
void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral)
Disables a peripheral in sleep mode.
Definition: prcm.c:668
#define PRCM_DOMAIN_PERIPH
Definition: prcm.h:142
#define PRCM_PERIPH_MASKBIT(a)
Definition: prcm.c:143
#define I2S_SAMPLE_RATE_32K
Definition: prcm.h:175
void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)
Configure the audio clock generation with manual setting of clock divider.
Definition: prcm.c:469
#define PRCM_CLOCK_DIV_32
Definition: prcm.h:127
#define PRCM_CLOCK_DIV_128
Definition: prcm.h:129
#define PRCM_DOMAIN_TIMER
Definition: prcm.h:150
#define PRCM_PERIPH_INDEX(a)
Definition: prcm.c:136
#define PRCM_SLEEP_MODE
Definition: prcm.h:114
__STATIC_INLINE void CPUwfi(void)
Wait for interrupt.
Definition: cpu.h:154
#define PRCM_DOMAIN_SYSBUS
Definition: prcm.h:144
void PRCMRetentionEnable(uint32_t ui32PowerDomain)
Enable retention on specific power domains.
Definition: prcm.c:799
void PRCMDeepSleep(void)
Put the processor into deep-sleep mode.
Definition: prcm.c:775
#define PRCM_CLOCK_DIV_1
Definition: prcm.h:122
void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)
Configure the infrastructure clock.
Definition: prcm.c:152
#define PRCM_DOMAIN_POWER_ON
Definition: prcm.h:157
void PRCMPowerDomainOn(uint32_t ui32Domains)
Turn power on in power domains in the MCU domain.
Definition: prcm.c:514
#define PRCM_DOMAIN_SERIAL
Definition: prcm.h:140
#define PRCM_DOMAIN_RFCORE
Definition: prcm.h:138
void PRCMRetentionDisable(uint32_t ui32PowerDomain)
Disable retention on power domains.
Definition: prcm.c:864
void PRCMPeripheralRunDisable(uint32_t ui32Peripheral)
Disables a peripheral in Run mode.
Definition: prcm.c:628
#define PRCM_CLOCK_DIV_2
Definition: prcm.h:123
void PRCMClockConfigureSet(uint32_t ui32Domains, uint32_t ui32ClkDiv)
Setup the clock division factor for a subsystem in the MCU voltage domain.
Definition: prcm.c:276
#define PRCM_DOMAIN_CPU
Definition: prcm.h:148
void PRCMPeripheralRunEnable(uint32_t ui32Peripheral)
Enables a peripheral in Run mode.
Definition: prcm.c:608
void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral)
Enables a peripheral in deep-sleep mode.
Definition: prcm.c:688
void PRCMPowerDomainOff(uint32_t ui32Domains)
Turn off a specific power domain.
Definition: prcm.c:561
void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral)
Disables a peripheral in deep-sleep mode.
Definition: prcm.c:708
void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)
Configure the audio clock generation.
Definition: prcm.c:386
#define PRCM_CLOCK_DIV_16
Definition: prcm.h:126
#define PRCM_DOMAIN_POWER_OFF
Definition: prcm.h:156
#define PRCM_RUN_MODE
Definition: prcm.h:113