62 #include <inc/hw_types.h>
63 #include <inc/hw_memmap.h>
64 #include <inc/hw_event.h>
72 #define EVENT_ALWAYS_0 0 // Unused - always '0'
73 #define EVENT_AON_PROG_0 1 // AON Programmable 0
74 #define EVENT_AON_PROG_1 2 // AON Programmable 1
75 #define EVENT_AON_PROG_2 3 // AON Programmable 2
76 #define EVENT_AON_EDGE_DETECT 4 // AON Edge Detect
77 #define EVENT_AON_SPIS_RTX 5 // AON SPIS RTX
78 #define EVENT_AON_SPIS_CS 6 // AON SPIS Chip Select
79 #define EVENT_AON_RTCCOMDLY 7 // AON Real Time Clock Combined Delayed
80 #define EVENT_AUX_SM 8 // AUX State Machine
81 #define EVENT_I2C_INTERRUPT 9 // I2C Interrupt
82 #define EVENT_AON_AUX0 10 // AON event for AUX
83 #define EVENT_PTIM_RTX 11 // MCU Combined
84 #define EVENT_TIMER2_A 12 // General Purpose Timer 2A
85 #define EVENT_TIMER2_B 13 // General Purpose Timer 2B
86 #define EVENT_TIMER3_A 14 // General Purpose Timer 3A
87 #define EVENT_TIMER3_B 15 // General Purpose Timer 3B
88 #define EVENT_TIMER0_A 16 // General Purpose Timer 0A
89 #define EVENT_TIMER0_B 17 // General Purpose Timer 0B
90 #define EVENT_TIMER1_A 18 // General Purpose Timer 1A
91 #define EVENT_TIMER1_B 19 // General Purpose Timer 1B
92 #define EVENT_SW0_DONE 20 // Software Event 0 Done
93 #define EVENT_FLASH 21 // Flash event
94 #define EVENT_SW1_DMA_DONE 22 // Software event 1 DMA done
95 #define EVENT_ADC 23 // ADC event
96 #define EVENT_WATCHDOG 24 // Watchdog Timer
97 #define EVENT_RFCORE_CMD_ACK 25 // RF command acknowledge
98 #define EVENT_RFCORE_HW 26 // RF Hardware Event
99 #define EVENT_RFCORE_CPE0 27 // RF Core Packet Engine 0
100 #define EVENT_PRCM_BUSON 28 // PRCM
101 #define EVENT_AUX_CMP 29 // AUX Compare
102 #define EVENT_RFCORE_CPE1 30 // RF Core Packet Engine 1
103 #define EVENT_PRCM 31 // Power Reset Clock Management
104 #define EVENT_AUX_ERR 32 // AUX Error Event
105 #define EVENT_AUX_ADC 33 // AUX_ADC
106 #define EVENT_SSI0 34 // SSI0 combined
107 #define EVENT_SSI1 35 // SSI1 combined
108 #define EVENT_UART0 36 // UART0 combined
109 #define EVENT_UART1 37 // UART1 combined
110 #define EVENT_DMA_ERR 38 // Error event from DMA
111 #define EVENT_DMA_DONE 39 // Combined done event from DMA
112 #define EVENT_SSI0_RX_BURST 40 // SSI0 Rx burst
113 #define EVENT_SSI0_RX_SINGLE 41 // SSI0 Rx single
114 #define EVENT_SSI0_TX_BURST 42 // SSI0 Tx burst
115 #define EVENT_SSI0_TX_SINGLE 43 // SSI0 Tx single
116 #define EVENT_SSI1_RX_BURST 44 // SSI1 Rx burst
117 #define EVENT_SSI1_RX_SINGLE 45 // SSI1 Rx single
118 #define EVENT_SSI1_TX_BURST 46 // SSI1 Tx burst
119 #define EVENT_SSI1_TX_SINGLE 47 // SSI1 Tx single
120 #define EVENT_UART0_RX_BURST 48 // UART0 Rx burst
121 #define EVENT_UART0_RX_SINGLE 49 // UART0 Rx single
122 #define EVENT_UART0_TX_BURST 50 // UART0 Tx burst
123 #define EVENT_UART0_TX_SINGLE 51 // UART0 Tx single
124 #define EVENT_UART1_RX_BURST 52 // UART1 Rx burst
125 #define EVENT_UART1_RX_SINGLE 53 // UART1 Rx single
126 #define EVENT_UART1_TX_BURST 54 // UART1 Tx burst
127 #define EVENT_UART1_TX_SINGLE 55 // UART1 Tx single
128 #define EVENT_SPIS 56 // SPIS Combined event
129 #define EVENT_AON_SPIS_RX_BURST 57 // AON SPIS RX burst
130 #define EVENT_AON_SPIS_RX_SINGLE 58 // AON SPIS RX single
131 #define EVENT_AON_SPIS_TX_BURST 59 // AON SPIS TX burst
132 #define EVENT_AON_SPIS_TX_SINGLE 60 // AON SPIS TX single
133 #define EVENT_TIMER0_A_COMP 61 // GPT0 compare A
134 #define EVENT_TIMER0_B_COMP 62 // GPT0 compare B
135 #define EVENT_TIMER1_A_COMP 63 // GPT1 compare A
136 #define EVENT_TIMER1_B_COMP 64 // GPT1 compare B
137 #define EVENT_TIMER2_A_COMP 65 // GPT2 compare A
138 #define EVENT_TIMER2_B_COMP 66 // GPT2 compare B
139 #define EVENT_TIMER3_A_COMP 67 // GPT3 compare A
140 #define EVENT_TIMER3_B_COMP 68 // GPT3 compare B
141 #define EVENT_TIMER0_A_SREQ_ 69 // GPT SREQ timer 0A
142 #define EVENT_TIMER0_B_SREQ 70 // GPT SREQ timer 0B
143 #define EVENT_TIMER1_A_SREQ 71 // GPT SREQ timer 1A
144 #define EVENT_TIMER1_B_SREQ 72 // GPT SREQ timer 1B
145 #define EVENT_TIMER2_A_SREQ 73 // GPT SREQ timer 2A
146 #define EVENT_TIMER2_B_SREQ 74 // GPT SREQ timer 2B
147 #define EVENT_TIMER3_A_SREQ 75 // GPT SREQ timer 3A
148 #define EVENT_TIMER3_B_SREQ 76 // GPT SREQ timer 3B
149 #define EVENT_TIMER0_A_REQ 77 // GPT REQ timer 0A
150 #define EVENT_TIMER0_B_REQ 78 // GPT REQ timer 0B
151 #define EVENT_TIMER1_A_REQ 79 // GPT REQ timer 1A
152 #define EVENT_TIMER1_B_REQ 80 // GPT REQ timer 1B
153 #define EVENT_TIMER2_A_REQ 81 // GPT REQ timer 2A
154 #define EVENT_TIMER2_B_REQ 82 // GPT REQ timer 2B
155 #define EVENT_TIMER3_A_REQ 83 // GPT REQ timer 3A
156 #define EVENT_TIMER3_B_REQ 84 // GPT REQ timer 3B
157 #define EVENT_PAD_IN_TIMER_SUB0 85 // Pad inputs for GPT subscribers - 0
158 #define EVENT_PAD_IN_TIMER_SUB1 86 // Pad inputs for GPT subscribers - 1
159 #define EVENT_PAD_IN_TIMER_SUB2 87 // Pad inputs for GPT subscribers - 2
160 #define EVENT_PAD_IN_TIMER_SUB3 88 // Pad inputs for GPT subscribers - 3
161 #define EVENT_PAD_IN_TIMER_SUB4 89 // Pad inputs for GPT subscribers - 4
162 #define EVENT_PAD_IN_TIMER_SUB5 90 // Pad inputs for GPT subscribers - 5
163 #define EVENT_PAD_IN_TIMER_SUB6 91 // Pad inputs for GPT subscribers - 6
164 #define EVENT_PAD_IN_TIMER_SUB7 92 // Pad inputs for GPT subscribers - 7
165 #define EVENT_CRYPTO_RES_RDY 93 // Crypto core result available
166 #define EVENT_CRYPTO_DMA_DONE 94 // Crypto core dma done
167 #define EVENT_RFCORE_INPUT_1 95 // RF Core input event 1
168 #define EVENT_RFCORE_INPUT_2 96 // RF Core input event 2
169 #define EVENT_RFCORE_INPUT_3 97 // RF Core input event 3
170 #define EVENT_RFCORE_INPUT_4 98 // RF Core input event 4
171 #define EVENT_NMI 99 // Maskable Interrupt
172 #define EVENT_SW0 100 // Software 0
173 #define EVENT_SW1 101 // Software 1
174 #define EVENT_SW2 102 // Software 2
175 #define EVENT_SW3 103 // Software 3
176 #define EVENT_TRNG 104 // TRNG interrupt
177 #define EVENT_AUX0 105 // AUX MCU trigger 0 event
178 #define EVENT_AUX1 106 // AUX MCU trigger 1 event
179 #define EVENT_AUX2 107 // AUX MCU trigger 2 event
180 #define EVENT_AUX3 108 // AUX MCU trigger 3 event
181 #define EVENT_AUX4 109 // AUX MCU trigger 4 event
182 #define EVENT_AUX5 110 // AUX MCU trigger 5 event
183 #define EVENT_AUX6 111 // AUX MCU trigger 6 event
184 #define EVENT_AUX7 112 // AUX MCU trigger 7 event
185 #define EVENT_AUX8 113 // AUX MCU trigger 8 event
186 #define EVENT_AUX9 114 // AUX MCU trigger 9 event
187 #define EVENT_AUX10 115 // AUX MCU trigger 10 event
188 #define EVENT_AUX_DMA_SW 116 // AUX DMA SW request
189 #define EVENT_AUX_DMA_SINGLE 117 // AUX DMA single request
190 #define EVENT_AUX_DMA_BURST 118 // AUX DMA burst request
191 #define EVENT_AON_RTC_UPD 119 // AON RTC update
192 #define EVENT_HALTED 120 // Halted
193 #define EVENT_ALWAYS_1 121 // Unused - always '1'
413 HWREG(
EVENT_BASE + ui32ProgOut) = ui32EventId;
425 #endif // __EVENT_H__
#define EVENT_TIMER0_A_REQ
#define EVENT_TIMER2_B_COMP
#define EVENT_PAD_IN_TIMER_SUB3
#define EVENT_RFCORE_PROG
#define EVENT_I2C_INTERRUPT
#define EVENT_TIMER1_B_SREQ
#define EVENT_TIMER1_B_REQ
#define EVENT_TIMER3_B_REQ
#define EVENT_UART1_TX_BURST
#define EVENT_TIMER3_B_PROG
#define EVENT_TIMER1_B_COMP
#define EVENT_TIMER1_A_REQ
#define EVENT_TIMER0_B_REQ
#define EVENT_AON_SPIS_RX_SINGLE
#define EVENT_PAD_IN_TIMER_SUB2
#define EVENT_SSI1_TX_SINGLE
#define EVENT_UART1_RX_SINGLE
#define EVENT_PAD_IN_TIMER_SUB4
#define EVENT_TIMER0_B_SREQ
#define EVENT_SSI0_TX_SINGLE
#define EVENT_TIMER3_A_SREQ
#define EVENT_TIMER1_A_SREQ
#define EVENT_TIMER1_B_PROG
#define EVENT_AON_SPIS_RX_BURST
#define EVENT_TIMER0_A_SREQ_
#define EVENT_TIMER2_B_SREQ
#define EVENT_AON_SPIS_CS
#define EVENT_RFCORE_CPE0
#define EVENT_RFCORE_CPE1
#define EVENT_PAD_IN_TIMER_SUB0
#define EVENT_TIMER1_A_PROG
#define EVENT_CRYPTO_RES_RDY
#define EVENT_RFCORE_INPUT_2
#define EVENT_TIMER2_A_REQ
#define EVENT_TIMER3_B_SREQ
#define EVENT_RFCORE_INPUT_4
#define EVENT_UART0_TX_SINGLE
#define EVENT_AON_RTCCOMDLY
#define EVENT_AUX_DMA_BURST
#define EVENT_AON_SPIS_TX_BURST
#define EVENT_TIMER0_B_COMP
#define EVENT_AON_SPIS_TX_SINGLE
#define EVENT_SSI0_TX_BURST
#define EVENT_PAD_IN_TIMER_SUB7
#define EVENT_AON_SPIS_RTX
#define EVENT_TIMER0_A_PROG
#define EVENT_SSI1_TX_BURST
#define EVENT_SSI0_RX_BURST
#define EVENT_UART0_TX_BURST
#define EVENT_SSI1_RX_SINGLE
#define EVENT_TIMER0_A_COMP
#define EVENT_SSI1_RX_BURST
#define EVENT_UART1_TX_SINGLE
#define EVENT_TIMER2_A_PROG
__STATIC_INLINE void EventRegister(uint32_t ui32ProgOut, uint32_t ui32EventId)
Register a dynamic Event in the event fabric and connect a subscriber.
#define EVENT_AON_EDGE_DETECT
#define EVENT_TIMER3_A_PROG
#define EVENT_CRYPTO_DMA_DONE
#define EVENT_TIMER3_A_COMP
#define EVENT_TIMER1_A_COMP
#define EVENT_UART0_RX_BURST
#define EVENT_TIMER0_B_PROG
#define EVENT_TIMER2_B_REQ
#define EVENT_RFCORE_INPUT_3
#define EVENT_FREEZE_PROG
#define EVENT_SW1_DMA_DONE
#define EVENT_PAD_IN_TIMER_SUB6
#define EVENT_AON_RTC_UPD
#define EVENT_TIMER3_A_REQ
#define EVENT_TIMER2_A_COMP
#define EVENT_PAD_IN_TIMER_SUB1
#define EVENT_TIMER2_B_PROG
#define EVENT_TIMER3_B_COMP
#define EVENT_RFCORE_CMD_ACK
#define EVENT_UART0_RX_SINGLE
#define EVENT_UART1_RX_BURST
#define EVENT_RFCORE_INPUT_1
#define EVENT_SSI0_RX_SINGLE
#define EVENT_AUX_DMA_SINGLE
#define EVENT_PAD_IN_TIMER_SUB5
#define EVENT_TIMER2_A_SREQ