Instance: SSI0
Component: SSI
Base address: 0x40000000
Synchronous Serial Interface with master and slave capabilities
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4000 0000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4000 0004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4000 0008 |
|
RO |
32 |
0x0000 0003 |
0x0000 000C |
0x4000 000C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x4000 0010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x4000 0014 |
|
RO |
32 |
0x0000 0008 |
0x0000 0018 |
0x4000 0018 |
|
RO |
32 |
0x0000 0000 |
0x0000 001C |
0x4000 001C |
|
WO |
32 |
0x0000 0000 |
0x0000 0020 |
0x4000 0020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4000 0024 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4000 0000 |
Instance |
SSI0 |
Description |
Control Register 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
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31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
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15:8 |
SCR |
Serial clock rate: |
RW |
0x00 |
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7 |
SPH |
CLKOUT phase (Motorola SPI frame format only)
|
RW |
0 |
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6 |
SPO |
CLKOUT polarity (Motorola SPI frame format only)
|
RW |
0 |
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5:4 |
FRF |
Frame format.
|
RW |
0x0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 |
DSS |
Data Size Select.
|
RW |
0x0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4000 0004 |
Instance |
SSI0 |
Description |
Control Register 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||
3 |
SOD |
Slave-mode output disabled |
RW |
0 |
|||||||||||||
2 |
MS |
Master or slave mode select. This bit can be modified only when SSI is disabled, SSE=0.
|
RW |
0 |
|||||||||||||
1 |
SSE |
Synchronous serial interface enable.
|
RW |
0 |
|||||||||||||
0 |
LBM |
Loop back mode: |
RW |
0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4000 0008 |
Instance |
SSI0 |
Description |
Data Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
DATA |
Transmit/receive data |
RW |
0x0000 |
Address offset |
0x0000 000C |
||
Physical address |
0x4000 000C |
Instance |
SSI0 |
Description |
Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4 |
BSY |
Serial interface busy: |
RO |
0 |
||
3 |
RFF |
Receive FIFO full: |
RO |
0 |
||
2 |
RNE |
Receive FIFO not empty |
RO |
0 |
||
1 |
TNF |
Transmit FIFO not full: |
RO |
1 |
||
0 |
TFE |
Transmit FIFO empty: |
RO |
1 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4000 0010 |
Instance |
SSI0 |
Description |
Clock Prescale Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
CPSDVSR |
Clock prescale divisor: |
RW |
0x00 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4000 0014 |
Instance |
SSI0 |
Description |
Interrupt Mask Set and Clear Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
TXIM |
Transmit FIFO interrupt mask: |
RW |
0 |
||
2 |
RXIM |
Receive FIFO interrupt mask: |
RW |
0 |
||
1 |
RTIM |
Receive timeout interrupt mask: |
RW |
0 |
||
0 |
RORIM |
Receive overrun interrupt mask: |
RW |
0 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4000 0018 |
Instance |
SSI0 |
Description |
Raw Interrupt Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
TXRIS |
Raw transmit FIFO interrupt status: |
RO |
1 |
||
2 |
RXRIS |
Raw interrupt state of receive FIFO interrupt: |
RO |
0 |
||
1 |
RTRIS |
Raw interrupt state of receive timeout interrupt: |
RO |
0 |
||
0 |
RORRIS |
Raw interrupt state of receive overrun interrupt: |
RO |
0 |
Address offset |
0x0000 001C |
||
Physical address |
0x4000 001C |
Instance |
SSI0 |
Description |
Masked Interrupt Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
TXMIS |
Masked interrupt state of transmit FIFO interrupt: |
RO |
0 |
||
2 |
RXMIS |
Masked interrupt state of receive FIFO interrupt: |
RO |
0 |
||
1 |
RTMIS |
Masked interrupt state of receive timeout interrupt: |
RO |
0 |
||
0 |
RORMIS |
Masked interrupt state of receive overrun interrupt: |
RO |
0 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4000 0020 |
Instance |
SSI0 |
Description |
Interrupt Clear Register |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0000 0000 |
||
1 |
RTIC |
Clear the receive timeout interrupt: |
WO |
0 |
||
0 |
RORIC |
Clear the receive overrun interrupt: |
WO |
0 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4000 0024 |
Instance |
SSI0 |
Description |
DMA Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
TXDMAE |
Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. |
RW |
0 |
||
0 |
RXDMAE |
Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. |
RW |
0 |
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