Instance: RFC_TRC
Component: RFC_TRC
Base address: 0x40047000
Component for rfctrc register bank
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4004 7000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4004 7004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4004 7008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4004 700C |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x4004 7014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4004 7018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x4004 701C |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4004 7024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4004 7028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x4004 702C |
Address offset |
0x0000 0000 |
||
Physical address |
0x4004 7000 |
Instance |
RFC_TRC |
Description |
Tracer Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||||||||||
7:6 |
PRESCAL |
Data rate prescaler for bit clock of the serialized data
|
RW |
0x0 |
|||||||||||||||||||||
5 |
TSCLR |
Writing 1 to this bit clears the TX timer |
RW |
0 |
|||||||||||||||||||||
4 |
TSEN |
Enables the Timestamp |
RW |
0 |
|||||||||||||||||||||
3 |
CH3EN |
Enables CH3 traces
|
RW |
0 |
|||||||||||||||||||||
2:1 |
CH2EN |
Enables CH2 traces
|
RW |
0x0 |
|||||||||||||||||||||
0 |
CH1EN |
Enables CH1 traces
|
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4004 7004 |
Instance |
RFC_TRC |
Description |
Channel 1 Command Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:8 |
CH1PKTHDR |
Header Byte. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence. |
RW |
0x00 |
||
7:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
2:0 |
CH1PARCNT |
Number of parameters to transmit. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence. |
RW |
0x0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4004 7008 |
Instance |
RFC_TRC |
Description |
Channel 2 Command Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:8 |
CH2PKTHDR |
Header Byte. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence. |
RW |
0x00 |
||
7:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
2:0 |
CH2PARCNT |
Number of parameters to transmit. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence. |
RW |
0x0 |
Address offset |
0x0000 000C |
||
Physical address |
0x4004 700C |
Instance |
RFC_TRC |
Description |
Channel 3 Command Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:8 |
CH3PKTHDR |
Header Byte. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence. |
RW |
0x00 |
||
7:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
2:0 |
CH3PARCNT |
Number of parameters to transmit. Reverts back to 0 when ready to transmit. A Write starts a transmission sequence. |
RW |
0x0 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4004 7014 |
Instance |
RFC_TRC |
Description |
Channel 1 Parameter 0/1 Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
CH1PAR1 |
Parameter 1 for Channel 1 |
RW |
0x0000 |
||
15:0 |
CH1PAR0 |
Parameter 0 for Channel 1 |
RW |
0x0000 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4004 7018 |
Instance |
RFC_TRC |
Description |
Channel 2 Parameter 0/1 Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
CH2PAR1 |
Parameter 1 for Channel 2 |
RW |
0x0000 |
||
15:0 |
CH2PAR0 |
Parameter 0 for Channel 2 |
RW |
0x0000 |
Address offset |
0x0000 001C |
||
Physical address |
0x4004 701C |
Instance |
RFC_TRC |
Description |
Channel 3 Parameter 0/1 Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
CH3PAR1 |
Parameter 1 for Channel 3 |
RW |
0x0000 |
||
15:0 |
CH3PAR0 |
Parameter 0 for Channel 3 |
RW |
0x0000 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4004 7024 |
Instance |
RFC_TRC |
Description |
Channel 1 Parameter 2/3 Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
CH1PAR3 |
Parameter 3 for Channel 1 |
RW |
0x0000 |
||
15:0 |
CH1PAR2 |
Parameter 2 for Channel 1 |
RW |
0x0000 |
Address offset |
0x0000 0028 |
||
Physical address |
0x4004 7028 |
Instance |
RFC_TRC |
Description |
Channel 2 Parameter 2/3 Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
CH2PAR3 |
Parameter 3 for Channel 2 |
RW |
0x0000 |
||
15:0 |
CH2PAR2 |
Parameter 2 for Channel 2 |
RW |
0x0000 |
Address offset |
0x0000 002C |
||
Physical address |
0x4004 702C |
Instance |
RFC_TRC |
Description |
Channel 3 Parameter 2/3 Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
CH3PAR3 |
Parameter 3 for Channel 3 |
RW |
0x0000 |
||
15:0 |
CH3PAR2 |
Parameter 2 for Channel 3 |
RW |
0x0000 |
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