Instance: UDMA0
Component: UDMA
Base address: 0x40020000
ARM Micro Direct Memory Access Controller
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x001F 0000 |
0x0000 0000 |
0x4002 0000 |
|
WO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4002 0004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4002 0008 |
|
RO |
32 |
0x0000 0200 |
0x0000 000C |
0x4002 000C |
|
RO |
32 |
0xFFFF 1EFF |
0x0000 0010 |
0x4002 0010 |
|
WO |
32 |
0x0000 0000 |
0x0000 0014 |
0x4002 0014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4002 0018 |
|
WO |
32 |
0x0000 0000 |
0x0000 001C |
0x4002 001C |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4002 0020 |
|
WO |
32 |
0x0000 0000 |
0x0000 0024 |
0x4002 0024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4002 0028 |
|
WO |
32 |
0x0000 0000 |
0x0000 002C |
0x4002 002C |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x4002 0030 |
|
WO |
32 |
0x0000 0000 |
0x0000 0034 |
0x4002 0034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4002 0038 |
|
WO |
32 |
0x0000 0000 |
0x0000 003C |
0x4002 003C |
|
RW |
32 |
0x0000 0000 |
0x0000 004C |
0x4002 004C |
|
RW |
32 |
0x0000 0000 |
0x0000 0504 |
0x4002 0504 |
|
RW |
32 |
0x0000 0000 |
0x0000 0520 |
0x4002 0520 |
|
RO |
32 |
0x0000 0004 |
0x0000 0FD0 |
0x4002 0FD0 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4002 0000 |
Instance |
UDMA0 |
Description |
UDMA Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:28 |
TEST |
|
RO |
0x0 |
||
27:21 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
20:16 |
TOTALCHANNELS |
Register value returns number of available uDMA channels minus one. For example a read out value of: |
RO |
0x1F |
||
15:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
7:4 |
STATE |
Current state of the control state machine. State can be one of the following: |
RO |
0x0 |
||
3:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
0 |
MASTERENABLE |
Shows the enable status of the controller as configured by CFG.MASTERENABLE: |
RO |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4002 0004 |
Instance |
UDMA0 |
Description |
UDMA Configuration |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x00 0000 |
||
7:5 |
PRTOCTRL |
Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows: |
WO |
0x0 |
||
4:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0 |
||
0 |
MASTERENABLE |
Enables the controller: |
WO |
0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4002 0008 |
Instance |
UDMA0 |
Description |
Channel Control Data Base Pointer |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:10 |
BASEPTR |
This register point to the base address for the primary data structures of each DMA channel. This is not stored in module, but in system memory, thus space must be allocated for this usage when DMA is in usage |
RW |
0x00 0000 |
||
9:0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x000 |
Address offset |
0x0000 000C |
||
Physical address |
0x4002 000C |
Instance |
UDMA0 |
Description |
Channel Alternate Control Data Base Pointer |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
BASEPTR |
This register shows the base address for the alternate data structures and is calculated by module, thus read only |
RO |
0x0000 0200 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4002 0010 |
Instance |
UDMA0 |
Description |
Channel Wait On Request Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLSTATUS |
Channel wait on request status: |
RO |
0xFFFF 1EFF |
Address offset |
0x0000 0014 |
||
Physical address |
0x4002 0014 |
Instance |
UDMA0 |
Description |
Channel Software Request |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Set the appropriate bit to generate a software uDMA request on the corresponding uDMA channel |
WO |
0x0000 0000 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4002 0018 |
Instance |
UDMA0 |
Description |
Channel Set UseBurst |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Returns the useburst status, or disables individual channels from generating single uDMA requests. The value R is the arbitration rate and stored in the controller data structure. |
RW |
0x0000 0000 |
Address offset |
0x0000 001C |
||
Physical address |
0x4002 001C |
Instance |
UDMA0 |
Description |
Channel Clear UseBurst |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Set the appropriate bit to enable single transfer requests. |
WO |
0x0000 0000 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4002 0020 |
Instance |
UDMA0 |
Description |
Channel Set Request Mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Returns the burst and single request mask status, or disables the corresponding channel from generating uDMA requests. |
RW |
0x0000 0000 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4002 0024 |
Instance |
UDMA0 |
Description |
Clear Channel Request Mask |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Set the appropriate bit to enable DMA request for the channel. |
WO |
0x0000 0000 |
Address offset |
0x0000 0028 |
||
Physical address |
0x4002 0028 |
Instance |
UDMA0 |
Description |
Set Channel Enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Returns the enable status of the channels, or enables the corresponding channels. |
RW |
0x0000 0000 |
Address offset |
0x0000 002C |
||
Physical address |
0x4002 002C |
Instance |
UDMA0 |
Description |
Clear Channel Enable |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Set the appropriate bit to disable the corresponding uDMA channel. |
WO |
0x0000 0000 |
Address offset |
0x0000 0030 |
||
Physical address |
0x4002 0030 |
Instance |
UDMA0 |
Description |
Channel Set Primary-Alternate |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Returns the channel control data structure status, or selects the alternate data structure for the corresponding uDMA channel. |
RW |
0x0000 0000 |
Address offset |
0x0000 0034 |
||
Physical address |
0x4002 0034 |
Instance |
UDMA0 |
Description |
Channel Clear Primary-Alternate |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Clears the appropriate bit to select the primary data structure for the corresponding uDMA channel. |
WO |
0x0000 0000 |
Address offset |
0x0000 0038 |
||
Physical address |
0x4002 0038 |
Instance |
UDMA0 |
Description |
Set Channel Priority |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Returns the channel priority mask status, or sets the channel priority to high. |
RW |
0x0000 0000 |
Address offset |
0x0000 003C |
||
Physical address |
0x4002 003C |
Instance |
UDMA0 |
Description |
Clear Channel Priority |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Clear the appropriate bit to select the default priority level for the specified uDMA channel. |
WO |
0x0000 0000 |
Address offset |
0x0000 004C |
||
Physical address |
0x4002 004C |
Instance |
UDMA0 |
Description |
Clear Bus Error |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0000 0000 |
||
0 |
STATUS |
Returns the status of bus error flag in uDMA, or clears this bit |
RW |
0 |
Address offset |
0x0000 0504 |
||
Physical address |
0x4002 0504 |
Instance |
UDMA0 |
Description |
Channel Request Done |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Reflects the uDMA done status for the given channel, channel [Ch]. It's a sticky done bit. Unless cleared by writing a 1, it holds the value of 1. |
RW |
0x0000 0000 |
Address offset |
0x0000 0520 |
||
Physical address |
0x4002 0520 |
Instance |
UDMA0 |
Description |
Channel Request Done Mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CHNLS |
Controls the propagation of the uDMA done and active state to the assigned peripheral. Specifically used for software channels. |
RW |
0x0000 0000 |
Address offset |
0x0000 0FD0 |
||
Physical address |
0x4002 0FD0 |
Instance |
UDMA0 |
Description |
Peripheral Identification 4 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:4 |
BLOCKCOUNT |
The number of 4KB address blocks you require, to access the registers, expressed in powers of 2. |
RO |
0x0 |
||
3:0 |
JEP106C |
This bit field is a continuation code value and represents how many 0x7F continuation characters occur in the manufacturer's identity code. |
RO |
0x4 |
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