AON_IOC

Instance: AON_IOC
Component: AON_IOC
Base address: 0x40094000

 

Always On (AON) IO Controller - controls IO operation when the MCU IO Controller (IOC) is powered off and resides in the AON domain.

Note: This module only supports 32 bit Read/Write access from MCU.

 

TOP:AON_IOC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

IOSTRMIN

RW

32

0x0000 0003

0x0000 0000

0x4009 4000

IOSTRMED

RW

32

0x0000 0006

0x0000 0004

0x4009 4004

IOSTRMAX

RW

32

0x0000 0005

0x0000 0008

0x4009 4008

IOCLATCH

RW

32

0x0000 0001

0x0000 000C

0x4009 400C

CLK32KCTL

RW

32

0x0000 0001

0x0000 0010

0x4009 4010

TOP:AON_IOC Register Descriptions

TOP:AON_IOC:IOSTRMIN

Address offset

0x0000 0000

Physical address

0x4009 4000

Instance

AON_IOC

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

GRAY_CODE

Internal

RW

0x3



TOP:AON_IOC:IOSTRMED

Address offset

0x0000 0004

Physical address

0x4009 4004

Instance

AON_IOC

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

GRAY_CODE

Internal

RW

0x6



TOP:AON_IOC:IOSTRMAX

Address offset

0x0000 0008

Physical address

0x4009 4008

Instance

AON_IOC

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

GRAY_CODE

Internal

RW

0x5



TOP:AON_IOC:IOCLATCH

Address offset

0x0000 000C

Physical address

0x4009 400C

Instance

AON_IOC

Description

IO Latch Control

Controls transparency of all latches holding I/O or configuration state from the MCU IOC

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

EN

Controls latches between MCU IOC and AON_IOC.

The latches are transparent by default.

They must be closed prior to power off the domain(s) controlling the IOs in order to preserve IO values on external pins.

Value

ENUM name

Description

0

STATIC

Latches are static, meaning the current value on the IO pin is frozen by latches and kept even if GPIO module or a peripheral module is turned off

1

TRANSP

Latches are transparent, meaning the value of the IO is directly controlled by the GPIO or peripheral value

RW

1



TOP:AON_IOC:CLK32KCTL

Address offset

0x0000 0010

Physical address

0x4009 4010

Instance

AON_IOC

Description

SCLK_LF External Output Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

OE_N

0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. IOC:IOCFG0.PORT_ID) set to AON_CLK32K.
1: Output enable not active

RW

1