Instance: ADI_2_REFSYS
Component: ADI_2_REFSYS
Base address: 0x40086000
ADI for REFSYS modules.
Registers Fields should be considered static unless otherwise noted (as dynamic)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
8 |
0x0000 0000 |
0x0000 0000 |
0x4008 6000 |
|
RW |
8 |
0x0000 0000 |
0x0000 0002 |
0x4008 6002 |
|
RW |
8 |
0x0000 0000 |
0x0000 0003 |
0x4008 6003 |
|
RW |
8 |
0x0000 0000 |
0x0000 0004 |
0x4008 6004 |
|
RW |
8 |
0x0000 0000 |
0x0000 0005 |
0x4008 6005 |
|
RW |
8 |
0x0000 0000 |
0x0000 0006 |
0x4008 6006 |
|
RW |
8 |
0x0000 0000 |
0x0000 0007 |
0x4008 6007 |
|
RW |
8 |
0x0000 0000 |
0x0000 000A |
0x4008 600A |
|
RW |
8 |
0x0000 0000 |
0x0000 000B |
0x4008 600B |
|
RW |
8 |
0x0000 0000 |
0x0000 000C |
0x4008 600C |
Address offset |
0x0000 0000 |
||
Physical address |
0x4008 6000 |
Instance |
ADI_2_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
4:0 |
TRIM_IREF |
Internal |
RW |
0x00 |
Address offset |
0x0000 0002 |
||
Physical address |
0x4008 6002 |
Instance |
ADI_2_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:4 |
VTRIM_UDIG |
Internal |
RW |
0x0 |
||
3:0 |
VTRIM_BOD |
Internal |
RW |
0x0 |
Address offset |
0x0000 0003 |
||
Physical address |
0x4008 6003 |
Instance |
ADI_2_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:4 |
VTRIM_COARSE |
Internal |
RW |
0x0 |
||
3:0 |
VTRIM_DIG |
Internal |
RW |
0x0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4008 6004 |
Instance |
ADI_2_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
2:0 |
VTRIM_DELTA |
Internal |
RW |
0x0 |
Address offset |
0x0000 0005 |
||
Physical address |
0x4008 6005 |
Instance |
ADI_2_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
7:6 |
ITRIM_DIGLDO_LOAD |
Internal |
RW |
0x0 |
|||||||||||||||||||||
5:3 |
ITRIM_DIGLDO |
Internal
|
RW |
0x0 |
|||||||||||||||||||||
2:0 |
ITRIM_UDIGLDO |
Internal |
RW |
0x0 |
Address offset |
0x0000 0006 |
||
Physical address |
0x4008 6006 |
Instance |
ADI_2_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
|||||||||||||
6:5 |
UDIG_ITEST_EN |
Internal |
RW |
0x0 |
|||||||||||||
4:2 |
DIG_ITEST_EN |
Internal |
RW |
0x0 |
|||||||||||||
1 |
BIAS_DIS |
Internal |
RW |
0 |
|||||||||||||
0 |
UDIG_LDO_EN |
Internal
|
RW |
0 |
Address offset |
0x0000 0007 |
||
Physical address |
0x4008 6007 |
Instance |
ADI_2_REFSYS |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
7:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
|||||||||||||||||||||
3 |
IMON_ITEST_EN |
Internal |
RW |
0 |
|||||||||||||||||||||
2:0 |
TESTSEL |
Internal
|
RW |
0x0 |
Address offset |
0x0000 000A |
||
Physical address |
0x4008 600A |
Instance |
ADI_2_REFSYS |
Description |
Bulk Acoustic Wave Control 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
7 |
FILTER_EN |
Enable BAW Bias filter |
RW |
0 |
|||||||||||||||||||||
6:5 |
BIAS_RECHARGE_DLY |
When BAWCTL2.BIAS_HOLD_MODE_EN = 1, low-power sample and hold mode for BAW bias is enabled. This field sets the recharge delay for this sample and hold mode by counting number of 48 MHz clock edges.
|
RW |
0x0 |
|||||||||||||||||||||
4:3 |
TUNE_CAP |
Cap to shift BAW center frequency.
|
RW |
0x0 |
|||||||||||||||||||||
2:1 |
SERIES_CAP |
Cap to set BAW into proper mode. Set 1 time in factory. |
RW |
0x0 |
|||||||||||||||||||||
0 |
DIV3_BYPASS |
Bypass for divide by 3 in divider.
|
RW |
0 |
Address offset |
0x0000 000B |
||
Physical address |
0x4008 600B |
Instance |
ADI_2_REFSYS |
Description |
Bulk Acoustic Wave Control 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
7 |
SPARE7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
|||||||||||||
6 |
SET_VREF |
Select which VREF is used for BAW: BGAP or VDD.
|
RW |
0 |
|||||||||||||
5 |
BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
|||||||||||||
4 |
PWRDET_EN |
Enable signal for BAW power detector. |
RW |
0 |
|||||||||||||
3:0 |
BIAS_RES_SET |
Adjust the BAW bias resistor to set the current in the BAW core. Two's complement encoding. |
RW |
0x0 |
Address offset |
0x0000 000C |
||
Physical address |
0x4008 600C |
Instance |
ADI_2_REFSYS |
Description |
Bulk Acoustic Wave Control 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7 |
BIAS_HOLD_MODE_EN |
Enable signal for bias sample and hold mode. Should give some power savings at expense of increased phase noise or spurs. |
RW |
0 |
||
6 |
TESTMUX_EN |
Enable signal for BAW test mux. |
RW |
0 |
||
5:4 |
ATEST_SEL |
ATEST Selection Control |
RW |
0x0 |
||
3:0 |
CURRMIRR_RATIO |
Set current mirror ratio in BAW. Controls amount of current flowing in BAW oscillator core. May need to increase from nominal if nominal setting does not result in oscillation. Two's complement encoding. |
RW |
0x0 |
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