Instance: SPIS
Component: SPIS
Base address: 0x40085000
SPI Slave block in switchable power domain with interface to SPI block in always-on power domain
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4008 5000 |
|
WO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4008 5004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4008 5008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4008 500C |
|
RW |
32 |
0x0000 000E |
0x0000 0010 |
0x4008 5010 |
|
WO |
32 |
0x0000 0000 |
0x0000 0014 |
0x4008 5014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4008 5018 |
|
RO |
32 |
0x0000 000E |
0x0000 001C |
0x4008 501C |
|
RW |
32 |
0x0000 0007 |
0x0000 0020 |
0x4008 5020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4008 5024 |
|
WO |
32 |
0x0000 0000 |
0x0000 0028 |
0x4008 5028 |
|
WO |
32 |
0x0000 0000 |
0x0000 002C |
0x4008 502C |
|
RO |
32 |
0x0000 0000 |
0x0000 0040 |
0x4008 5040 |
|
RO |
32 |
0x0000 0000 |
0x0000 0044 |
0x4008 5044 |
|
RO |
32 |
0x0000 0000 |
0x0000 0048 |
0x4008 5048 |
|
RW |
32 |
0x0000 000E |
0x0000 004C |
0x4008 504C |
|
WO |
32 |
0x0000 0000 |
0x0000 0050 |
0x4008 5050 |
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0x4008 5054 |
|
RO |
32 |
0x0000 000E |
0x0000 0058 |
0x4008 5058 |
|
RW |
32 |
0x0000 0007 |
0x0000 005C |
0x4008 505C |
|
RW |
32 |
0x0000 0000 |
0x0000 0060 |
0x4008 5060 |
|
RO |
32 |
0x0000 0000 |
0x0000 0064 |
0x4008 5064 |
|
WO |
32 |
0x0000 0000 |
0x0000 0068 |
0x4008 5068 |
|
RO |
32 |
0x0000 0000 |
0x0000 0080 |
0x4008 5080 |
|
RO |
32 |
0x0000 0000 |
0x0000 0084 |
0x4008 5084 |
|
RO |
32 |
0x0000 0000 |
0x0000 0088 |
0x4008 5088 |
|
RO |
32 |
0x0000 0000 |
0x0000 0400-0x0000 043C |
0x4008 5400- 0x4008 543C |
|
RO |
32 |
0x0000 0000 |
0x0000 0800-0x0000 083C |
0x4008 5800- 0x4008 583C |
Address offset |
0x0000 0000 |
||
Physical address |
0x4008 5000 |
Instance |
SPIS |
Description |
SPI Slave General Purpose Flags |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
BYTE_DONE |
0 |
RW |
0 |
||
2 |
BYTE_RX_OVF |
Parallel receive data overflow event. |
RW |
0 |
||
1 |
BYTE_ABORT |
Incomplete SPI transfer event. |
RW |
0 |
||
0 |
CS |
Chip select event. |
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4008 5004 |
Instance |
SPIS |
Description |
SPI Slave General Purpose Flags Set |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
RESERVED4 |
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
WO |
0x000 0000 |
||
3 |
BYTE_DONE |
0: No effect. |
WO |
0 |
||
2 |
BYTE_RX_OVF |
0: No effect. |
WO |
0 |
||
1 |
BYTE_ABORT |
0: No effect. |
WO |
0 |
||
0 |
CS |
0: No effect. |
WO |
0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4008 5008 |
Instance |
SPIS |
Description |
SPI Slave General Purpose Flags Mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
5 |
RX_DMA_DONE |
Enable bit for DMA done, DMA channel with RX FIFO as source. |
RW |
0 |
||
4 |
TX_DMA_DONE |
0 |
RW |
0 |
||
3 |
BYTE_DONE |
Enable bit for GPFLAGS.BYTE_DONE as event signal. |
RW |
0 |
||
2 |
BYTE_RX_OVF |
Enable bit for GPFLAGS.BYTE_RX_OVF as event signal. |
RW |
0 |
||
1 |
BYTE_ABORT |
Enable bit for GPFLAGS.BYTE_ABORT as event signal. |
RW |
0 |
||
0 |
CS |
Enable bit for GPFLAGS.CS as event signal. |
RW |
0 |
Address offset |
0x0000 000C |
||
Physical address |
0x4008 500C |
Instance |
SPIS |
Description |
SPI Slave Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4 |
RX_DMA_REQ_TYPE |
RX DMA request type select. |
RW |
0 |
||
3 |
TX_DMA_REQ_TYPE |
TX DMA request type select. |
RW |
0 |
||
2 |
RX_BIT_ORDER |
MOSI first bit configuration. |
RW |
0 |
||
1 |
TX_BIT_ORDER |
MISO first bit configuration. |
RW |
0 |
||
0 |
POL |
SPI clock polarity. |
RW |
0 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4008 5010 |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Flags Clear |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
6 |
OVF |
TX FIFO overflow flag. |
RW |
0 |
||
5 |
UNF |
TX FIFO underflow flag. |
RW |
0 |
||
4 |
NOT_EMPTY |
TX FIFO has one or more bytes. |
RW |
0 |
||
3 |
LE_THR |
TX FIFO less than or equal TX FIFO threshold count set by TXFTHR.CNT. |
RW |
1 |
||
2 |
GE_THR |
TX FIFO greater than or equal to TX FIFO threshold count set by TXFTHR.CNT. |
RW |
1 |
||
1 |
EMPTY |
TX FIFO empty flag. |
RW |
1 |
||
0 |
FULL |
TX FIFO full flag. |
RW |
0 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4008 5014 |
Instance |
SPIS |
Description |
TX FIFO Flags Set |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x000 0000 |
||
6 |
OVF |
TX FIFO overflow flag. |
WO |
0 |
||
5 |
UNF |
TX FIFO underflow flag. |
WO |
0 |
||
4 |
NOT_EMPTY |
TX FIFO has data flag. |
WO |
0 |
||
3 |
LE_THR |
TX FIFO threshold count event. |
WO |
0 |
||
2 |
GE_THR |
TX FIFO GE threshold count event. |
WO |
0 |
||
1 |
EMPTY |
TX FIFO empty event. |
WO |
0 |
||
0 |
FULL |
TX FIFO full event. |
WO |
0 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4008 5018 |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Flags Mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
6 |
OVF |
Enable bit for TXFFLAGSCLRN.OVF as event signal. |
RW |
0 |
||
5 |
UNF |
Enable bit for TXFFLAGSCLRN.UNF as event signal. |
RW |
0 |
||
4 |
NOT_EMPTY |
Enable bit for TXFFLAGSCLRN.NOT_EMPTY as event signal. |
RW |
0 |
||
3 |
LE_THR |
Enable bit for TXFFLAGSCLRN.LE_THR as event signal. |
RW |
0 |
||
2 |
GE_THR |
Enable bit for TXFFLAGSCLRN.GE_THR as event signal. |
RW |
0 |
||
1 |
EMPTY |
Enable bit for TXFFLAGSCLRN.EMPTY as event signal. |
RW |
0 |
||
0 |
FULL |
Enable bit for TXFFLAGSCLRN.FULL as event signal. |
RW |
0 |
Address offset |
0x0000 001C |
||
Physical address |
0x4008 501C |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4 |
NOT_EMPTY |
TX FIFO has one or more bytes status. |
RO |
0 |
||
3 |
LE_THR |
TX FIFO less than or equal to TX FIFO threshold count set by TXFTHR.CNT. |
RO |
1 |
||
2 |
GE_THR |
TX FIFO greater than or equal to TX FIFO threshold count set by TXFTHR.CNT. |
RO |
1 |
||
1 |
EMPTY |
TX FIFO empty status. |
RO |
1 |
||
0 |
FULL |
TX FIFO full status. |
RO |
0 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4008 5020 |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Event Source |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||||||||||||||||||
2:0 |
SEL |
TX FIFO Status event source select
|
RW |
0x7 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4008 5024 |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Threshold Count |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3:0 |
CNT |
TXFIFO count threshold. |
RW |
0x0 |
Address offset |
0x0000 0028 |
||
Physical address |
0x4008 5028 |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Push |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x00 0000 |
||
7:0 |
DATA |
Data to be pushed into TX FIFO. |
WO |
0x00 |
Address offset |
0x0000 002C |
||
Physical address |
0x4008 502C |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Flush |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0000 0000 |
||
0 |
FLUSH |
Execute TX FIFO flush command. |
WO |
0 |
Address offset |
0x0000 0040 |
||
Physical address |
0x4008 5040 |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Memory Read Pointer |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3:0 |
POS |
Read pointer position. |
RO |
0x0 |
Address offset |
0x0000 0044 |
||
Physical address |
0x4008 5044 |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Memory Write Pointer |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3:0 |
POS |
Write pointer position. |
RO |
0x0 |
Address offset |
0x0000 0048 |
||
Physical address |
0x4008 5048 |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Count |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4:0 |
CNT |
Number of bytes present in the TX FIFO. |
RO |
0x00 |
Address offset |
0x0000 004C |
||
Physical address |
0x4008 504C |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Flag Clear |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
6 |
OVF |
RX FIFO overflow flag. |
RW |
0 |
||
5 |
UNF |
RX FIFO underflow. |
RW |
0 |
||
4 |
NOT_EMPTY |
RX FIFO has one or more bytes. |
RW |
0 |
||
3 |
LE_THR |
RX FIFO less than or equal RX FIFO threshold count. |
RW |
1 |
||
2 |
GE_THR |
RX FIFO greater than or equal to RX FIFO threshold count . |
RW |
1 |
||
1 |
EMPTY |
RX FIFO empty flag. |
RW |
1 |
||
0 |
FULL |
RX FIFO full flag. |
RW |
0 |
Address offset |
0x0000 0050 |
||
Physical address |
0x4008 5050 |
Instance |
SPIS |
Description |
RX FIFO Flags Set |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x000 0000 |
||
6 |
OVF |
RX FIFO overflow flag. |
WO |
0 |
||
5 |
UNF |
RX FIFO underflow flag. |
WO |
0 |
||
4 |
NOT_EMPTY |
RX FIFO has data flag. |
WO |
0 |
||
3 |
LE_THR |
RX FIFO threshold count event. |
WO |
0 |
||
2 |
GE_THR |
RX FIFO GE threshold count event. |
WO |
0 |
||
1 |
EMPTY |
RX FIFO empty event. |
WO |
0 |
||
0 |
FULL |
RX FIFO full event. |
WO |
0 |
Address offset |
0x0000 0054 |
||
Physical address |
0x4008 5054 |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Flags Mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
6 |
OVF |
Enable bit for RXFFLAGSCLRN.OVF as event signal. |
RW |
0 |
||
5 |
UNF |
Enable bit for RXFFLAGSCLRN.UNF as event signal. |
RW |
0 |
||
4 |
NOT_EMPTY |
Enable bit for RXFFLAGSCLRN.NOT_EMPTY as event signal. |
RW |
0 |
||
3 |
LE_THR |
Enable bit for RXFFLAGSCLRN.LE_THR as event signal. |
RW |
0 |
||
2 |
GE_THR |
Enable bit for RXFFLAGSCLRN.GE_THR as event signal. |
RW |
0 |
||
1 |
EMPTY |
Enable bit for RXFFLAGSCLRN.EMPTY as event signal. |
RW |
0 |
||
0 |
FULL |
Enable bit for RXFFLAGSCLRN.FULL as event signal. |
RW |
0 |
Address offset |
0x0000 0058 |
||
Physical address |
0x4008 5058 |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4 |
NOT_EMPTY |
RX FIFO has one or more bytes status. |
RO |
0 |
||
3 |
LE_THR |
RX FIFO byte count less than or equal to RX FIFO threshold count RXFTHR.CNT. |
RO |
1 |
||
2 |
GE_THR |
RX FIFO byte count greater than or equal to RX FIFO threshold count RXFTHR.CNT. |
RO |
1 |
||
1 |
EMPTY |
RX FIFO empty status. |
RO |
1 |
||
0 |
FULL |
RX FIFO full status. |
RO |
0 |
Address offset |
0x0000 005C |
||
Physical address |
0x4008 505C |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Event Source |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||||||||||||||||||
2:0 |
SEL |
RX FIFO Status source select
|
RW |
0x7 |
Address offset |
0x0000 0060 |
||
Physical address |
0x4008 5060 |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Threshold |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3:0 |
CNT |
Threshold count. |
RW |
0x0 |
Address offset |
0x0000 0064 |
||
Physical address |
0x4008 5064 |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Pop |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
DATA |
Data read from RX FIFO. |
RO |
0x00 |
Address offset |
0x0000 0068 |
||
Physical address |
0x4008 5068 |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Flush |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0000 0000 |
||
0 |
FLUSH |
Execute RX FIFO flush command. |
WO |
0 |
Address offset |
0x0000 0080 |
||
Physical address |
0x4008 5080 |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Memory Read Position |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3:0 |
POS |
RX FIFO read pointer value. |
RO |
0x0 |
Address offset |
0x0000 0084 |
||
Physical address |
0x4008 5084 |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Memory Write Position |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3:0 |
POS |
FIFO write pointer value. |
RO |
0x0 |
Address offset |
0x0000 0088 |
||
Physical address |
0x4008 5088 |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Byte Count |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4:0 |
CNT |
Number of bytes in present in RX FIFO. |
RO |
0x00 |
Address offset |
0x0000 0400-0x0000 043C |
||
Physical address |
0x4008 5400- 0x4008 543C |
Instance |
SPIS |
Description |
SPI Slave TX FIFO Memory |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
RESERVED8 |
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
RO |
0x00 0000 |
||
7:0 |
DATA |
FIFO data element |
RO |
0x00 |
Address offset |
0x0000 0800-0x0000 083C |
||
Physical address |
0x4008 5800- 0x4008 583C |
Instance |
SPIS |
Description |
SPI Slave RX FIFO Data |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
RESERVED8 |
Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
RO |
0x00 0000 |
||
7:0 |
DATA |
FIFO data. |
RO |
0x00 |
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