Instance: UART0
Component: UART
Base address: 0x40001000
Universal Asynchronous Receiver/Transmitter (UART) interface
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4000 1000 |
|
WO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4000 1004 |
|
RO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4000 1004 |
|
RO |
32 |
0x0000 0090 |
0x0000 0018 |
0x4000 1018 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4000 1024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4000 1028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x4000 102C |
|
RW |
32 |
0x0000 0300 |
0x0000 0030 |
0x4000 1030 |
|
RW |
32 |
0x0000 0012 |
0x0000 0034 |
0x4000 1034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4000 1038 |
|
RO |
32 |
0x0000 000D |
0x0000 003C |
0x4000 103C |
|
RO |
32 |
0x0000 0000 |
0x0000 0040 |
0x4000 1040 |
|
WO |
32 |
0x0000 0000 |
0x0000 0044 |
0x4000 1044 |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x4000 1048 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4000 1000 |
Instance |
UART0 |
Description |
UART Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
||
11 |
OE |
UART Overrun Error: |
RO |
0 |
||
10 |
BE |
UART Break Error: |
RO |
0 |
||
9 |
PE |
UART Parity Error: |
RO |
0 |
||
8 |
FE |
UART Framing Error: |
RO |
0 |
||
7:0 |
DATA |
Data transmitted or received: |
RW |
0x00 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4000 1004 |
Instance |
UART0 |
Description |
UART Error Clear Register |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x000 0000 |
||
3 |
OE |
The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. |
WO |
0 |
||
2 |
BE |
The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. |
WO |
0 |
||
1 |
PE |
The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. |
WO |
0 |
||
0 |
FE |
The framing (FE), parity (PE), break (BE) and overrun (OE) errors are cleared to 0 by any write to this register. |
WO |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4000 1004 |
Instance |
UART0 |
Description |
UART Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
3 |
OE |
UART Overrun Error: |
RO |
0 |
||
2 |
BE |
UART Break Error: |
RO |
0 |
||
1 |
PE |
UART Parity Error: |
RO |
0 |
||
0 |
FE |
UART Framing Error: |
RO |
0 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4000 1018 |
Instance |
UART0 |
Description |
UART Flag Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7 |
TXFE |
UART Transmit FIFO Empty: |
RO |
1 |
||
6 |
RXFF |
UART Receive FIFO Full: |
RO |
0 |
||
5 |
TXFF |
UART Transmit FIFO Full: |
RO |
0 |
||
4 |
RXFE |
UART Receive FIFO Empty: |
RO |
1 |
||
3 |
BUSY |
UART Busy: |
RO |
0 |
||
2:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
0 |
CTS |
Clear To Send: |
RO |
0 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4000 1024 |
Instance |
UART0 |
Description |
UART Integer Baud-Rate Divisor |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 |
||
15:0 |
DIVINT |
The integer baud rate divisor: |
RW |
0x0000 |
Address offset |
0x0000 0028 |
||
Physical address |
0x4000 1028 |
Instance |
UART0 |
Description |
UART Fractional Baud-Rate Divisor |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x000 0000 |
||
5:0 |
DIVFRAC |
Fractional Baud-Rate Divisor: |
RW |
0x00 |
Address offset |
0x0000 002C |
||
Physical address |
0x4000 102C |
Instance |
UART0 |
Description |
UART Line Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 0000 |
|||||||||||||||||||||
7 |
SPS |
UART Stick Parity Select: |
RW |
0 |
|||||||||||||||||||||
6:5 |
WLEN |
UART Word Length:
|
RW |
0x0 |
|||||||||||||||||||||
4 |
FEN |
UART Enable FIFOs
|
RW |
0 |
|||||||||||||||||||||
3 |
STP2 |
UART Two Stop Bits Select: |
RW |
0 |
|||||||||||||||||||||
2 |
EPS |
UART Even Parity Select
|
RW |
0 |
|||||||||||||||||||||
1 |
PEN |
UART Parity Enable
|
RW |
0 |
|||||||||||||||||||||
0 |
BRK |
UART Send Break |
RW |
0 |
Address offset |
0x0000 0030 |
||
Physical address |
0x4000 1030 |
Instance |
UART0 |
Description |
UART Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
|||||||||||||
15 |
CTSEN |
CTS hardware flow control enable
|
RW |
0 |
|||||||||||||
14 |
RTSEN |
RTS hardware flow control enable
|
RW |
0 |
|||||||||||||
13:12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
|||||||||||||
11 |
RTS |
Request to Send |
RW |
0 |
|||||||||||||
10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
|||||||||||||
9 |
RXE |
UART Receive Enable
|
RW |
1 |
|||||||||||||
8 |
TXE |
UART Transmit Enable
|
RW |
1 |
|||||||||||||
7 |
LBE |
UART Loop Back Enable:
|
RW |
0 |
|||||||||||||
6:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 |
|||||||||||||
0 |
UARTEN |
UART Enable
|
RW |
0 |
Address offset |
0x0000 0034 |
||
Physical address |
0x4000 1034 |
Instance |
UART0 |
Description |
UART Interrupt FIFO Level Select |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||
31:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x000 0000 |
|||||||||||||||||||||||||
5:3 |
RXSEL |
Receive interrupt FIFO level select:
|
RW |
0x2 |
|||||||||||||||||||||||||
2:0 |
TXSEL |
Transmit interrupt FIFO level select:
|
RW |
0x2 |
Address offset |
0x0000 0038 |
||
Physical address |
0x4000 1038 |
Instance |
UART0 |
Description |
UART Interrupt Mask Set/Clear Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:11 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 0000 |
||
10 |
OEIM |
Overrun error interrupt mask. A read returns the current mask for UART's overrun error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not reflect the interrupt. |
RW |
0 |
||
9 |
BEIM |
Break error interrupt mask. A read returns the current mask for UART's break error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.BEMIS. A write of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. |
RW |
0 |
||
8 |
PEIM |
Parity error interrupt mask. A read returns the current mask for UART's parity error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not reflect the interrupt. |
RW |
0 |
||
7 |
FEIM |
Framing error interrupt mask. A read returns the current mask for UART's framing error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not reflect the interrupt. |
RW |
0 |
||
6 |
RTIM |
Receive timeout interrupt mask. A read returns the current mask for UART's receive timeout interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not reflect the interrupt. |
RW |
0 |
||
5 |
TXIM |
Transmit interrupt mask. A read returns the current mask for UART's transmit interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt. |
RW |
0 |
||
4 |
RXIM |
Receive interrupt mask. A read returns the current mask for UART's receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt. |
RW |
0 |
||
3:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
1 |
CTSMIM |
Clear to Send (CTS) modem interrupt mask. A read returns the current mask for UART's clear to send interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not reflect the interrupt. |
RW |
0 |
||
0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
Address offset |
0x0000 003C |
||
Physical address |
0x4000 103C |
Instance |
UART0 |
Description |
Raw Interrupt Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:11 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
10 |
OERIS |
Overrun error interrupt status: |
RO |
0 |
||
9 |
BERIS |
Break error interrupt status: |
RO |
0 |
||
8 |
PERIS |
Parity error interrupt status: |
RO |
0 |
||
7 |
FERIS |
Framing error interrupt status: |
RO |
0 |
||
6 |
RTRIS |
Receive timeout interrupt status: |
RO |
0 |
||
5 |
TXRIS |
Transmit interrupt status: |
RO |
0 |
||
4 |
RXRIS |
Receive interrupt status: |
RO |
0 |
||
3:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x3 |
||
1 |
CTSRMIS |
Clear to Send (CTS) modem interrupt status: |
RO |
0 |
||
0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
1 |
Address offset |
0x0000 0040 |
||
Physical address |
0x4000 1040 |
Instance |
UART0 |
Description |
UART Masked Interrupt Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:11 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
10 |
OEMIS |
Overrun error masked interrupt status: |
RO |
0 |
||
9 |
BEMIS |
Break error masked interrupt status: |
RO |
0 |
||
8 |
PEMIS |
Parity error masked interrupt status: |
RO |
0 |
||
7 |
FEMIS |
Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM. |
RO |
0 |
||
6 |
RTMIS |
Receive timeout masked interrupt status: |
RO |
0 |
||
5 |
TXMIS |
Transmit masked interrupt status: |
RO |
0 |
||
4 |
RXMIS |
Receive masked interrupt status: |
RO |
0 |
||
3:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
1 |
CTSMMIS |
Clear to Send (CTS) modem masked interrupt status: |
RO |
0 |
||
0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
Address offset |
0x0000 0044 |
||
Physical address |
0x4000 1044 |
Instance |
UART0 |
Description |
UART Interrupt Clear |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0000 |
||
15:11 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x00 |
||
10 |
OEIC |
Overrun error interrupt clear: |
WO |
0 |
||
9 |
BEIC |
Break error interrupt clear: |
WO |
0 |
||
8 |
PEIC |
Parity error interrupt clear: |
WO |
0 |
||
7 |
FEIC |
Framing error interrupt clear: |
WO |
0 |
||
6 |
RTIC |
Receive timeout interrupt clear: |
WO |
0 |
||
5 |
TXIC |
Transmit interrupt clear: |
WO |
0 |
||
4 |
RXIC |
Receive interrupt clear: |
WO |
0 |
||
3:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0 |
WO |
0x0 |
||
1 |
CTSMIC |
Clear to Send (CTS) modem interrupt clear: |
WO |
0 |
||
0 |
RESERVED0 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Write 0. |
WO |
0 |
Address offset |
0x0000 0048 |
||
Physical address |
0x4000 1048 |
Instance |
UART0 |
Description |
DMA Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 0000 |
||
2 |
DMAONERR |
DMA on error. If this bit is set to 1, the DMA receive request outputs (for single and burst requests) are disabled when the UART error interrupt is asserted (more specifically if any of the error interrupts RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). |
RW |
0 |
||
1 |
TXDMAE |
Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. |
RW |
0 |
||
0 |
RXDMAE |
Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. |
RW |
0 |
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