Instance: AON_RTC
Component: AON_RTC
Base address: 0x40092000
This component control the Real Time Clock residing in AON
Note: This module is only supporting 32 bit ReadWrite access.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4009 2000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4009 2004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4009 2008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4009 200C |
|
RO |
32 |
0x0080 0000 |
0x0000 0010 |
0x4009 2010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x4009 2014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4009 2018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x4009 201C |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4009 2020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4009 2024 |
|
RO |
32 |
0x0000 0000 |
0x0000 0028 |
0x4009 2028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x4009 202C |
Address offset |
0x0000 0000 |
||
Physical address |
0x4009 2000 |
Instance |
AON_RTC |
Description |
RTC Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:19 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
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18:16 |
COMB_EV_MASK |
Eventmask selecting which delayed events that form the combined event.
|
RW |
0x0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:8 |
EV_DELAY |
Number of SCLK_LF clock cycles waited before generating delayed events. (Common setting for all RTC cannels) the delayed event is delayed
|
RW |
0x0 |
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7 |
RESET |
RTC Counter reset. |
WO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 |
RTC_4KHZ_EN |
RTC_4KHZ is a 4 KHz reference output, tapped from [SUBSEC:VALUE] bit 19 which is used by AUX timer. |
RW |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 |
RTC_UPD_EN |
RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is SCLK_LF divided by 2 |
RW |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 |
EN |
Enable RTC counter |
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4009 2004 |
Instance |
AON_RTC |
Description |
RTC Status Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:17 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
16 |
CH2 |
Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or passes the CH2CMP value. |
RW |
0 |
||
15:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
8 |
CH1 |
Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: |
RW |
0 |
||
7:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
0 |
CH0 |
Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or passes the CH0CMP value. |
RW |
0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4009 2008 |
Instance |
AON_RTC |
Description |
Second Counter Value, Integer Part |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
VALUE |
Unsigned integer representing Real Time Clock in seconds. |
RW |
0x0000 0000 |
Address offset |
0x0000 000C |
||
Physical address |
0x4009 200C |
Instance |
AON_RTC |
Description |
Second Counter Value, Fractional Part |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
VALUE |
Unsigned integer representing Real Time Clock in fractions of a second (VALUE/2^32 seconds) at the time when SEC register was read. |
RW |
0x0000 0000 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4009 2010 |
Instance |
AON_RTC |
Description |
Subseconds Increment Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:24 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
23:0 |
VALUEINC |
This value compensates for a SCLK_LF clock which has an offset from 32768 Hz. |
RO |
0x80 0000 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4009 2014 |
Instance |
AON_RTC |
Description |
Channel Configuration Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:19 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
18 |
CH2_CONT_EN |
Set to enable continuous opereation of Channel 2 |
RW |
0 |
||
17 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
||
16 |
CH2_EN |
RTC Channel 2 Enable |
RW |
0 |
||
15:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
9 |
CH1_CAPT_EN |
Set Channel 1 mode |
RW |
0 |
||
8 |
CH1_EN |
RTC Channel 1 Enable |
RW |
0 |
||
7:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
0 |
CH0_EN |
RTC Channel 0 Enable |
RW |
0 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4009 2018 |
Instance |
AON_RTC |
Description |
Channel 0 Compare Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
VALUE |
RTC Channel 0 compare value. |
RW |
0x0000 0000 |
Address offset |
0x0000 001C |
||
Physical address |
0x4009 201C |
Instance |
AON_RTC |
Description |
Channel 1 Compare Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
VALUE |
RTC Channel 1 compare value. |
RW |
0x0000 0000 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4009 2020 |
Instance |
AON_RTC |
Description |
Channel 2 Compare Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
VALUE |
RTC Channel 2 compare value. |
RW |
0x0000 0000 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4009 2024 |
Instance |
AON_RTC |
Description |
Channel 2 Compare Value Auto-increment |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
VALUE |
If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every channel 2 compare event. |
RW |
0x0000 0000 |
Address offset |
0x0000 0028 |
||
Physical address |
0x4009 2028 |
Instance |
AON_RTC |
Description |
Channel 1 Capture Value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
SEC |
Value of SEC.VALUE bits 15:0 at capture time. |
RO |
0x0000 |
||
15:0 |
SUBSEC |
Value of SUBSEC.VALUE bits 31:16 at capture time. |
RO |
0x0000 |
Address offset |
0x0000 002C |
||
Physical address |
0x4009 202C |
Instance |
AON_RTC |
Description |
AON Synchronization Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
WBUSY |
This register will always return 0,- however it will not return the value until there are no outstanding write requests between MCU and AON |
RW |
0 |
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