Instance: I2C0
Component: I2C
Base address: 0x40002000
I2CMaster/Slave Serial Controler
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4000 2000 |
|
RO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4000 2004 |
|
WO |
32 |
0x0000 0000 |
0x0000 0004 |
0x4000 2004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4000 2008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4000 200C |
|
RO |
32 |
0x0000 0000 |
0x0000 0010 |
0x4000 2010 |
|
RO |
32 |
0x0000 0000 |
0x0000 0014 |
0x4000 2014 |
|
WO |
32 |
0x0000 0000 |
0x0000 0018 |
0x4000 2018 |
|
RW |
32 |
0x0000 0000 |
0x0000 0800 |
0x4000 2800 |
|
RO |
32 |
0x0000 0020 |
0x0000 0804 |
0x4000 2804 |
|
WO |
32 |
0x0000 0000 |
0x0000 0804 |
0x4000 2804 |
|
RW |
32 |
0x0000 0000 |
0x0000 0808 |
0x4000 2808 |
|
RW |
32 |
0x0000 0001 |
0x0000 080C |
0x4000 280C |
|
RW |
32 |
0x0000 0000 |
0x0000 0810 |
0x4000 2810 |
|
RO |
32 |
0x0000 0000 |
0x0000 0814 |
0x4000 2814 |
|
RO |
32 |
0x0000 0000 |
0x0000 0818 |
0x4000 2818 |
|
WO |
32 |
0x0000 0000 |
0x0000 081C |
0x4000 281C |
|
RW |
32 |
0x0000 0000 |
0x0000 0820 |
0x4000 2820 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4000 2000 |
Instance |
I2C0 |
Description |
I2C Slave Own Address |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
6:0 |
OAR |
I2C slave own address |
RW |
0x00 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4000 2004 |
Instance |
I2C0 |
Description |
I2C Slave Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
FBR |
First byte received |
RO |
0 |
||
1 |
TREQ |
Transmit request |
RO |
0 |
||
0 |
RREQ |
Receive request |
RO |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4000 2004 |
Instance |
I2C0 |
Description |
I2C Slave Control |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
RESERVED1 |
Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. |
WO |
0x0000 0000 |
||
0 |
DA |
Device active |
WO |
0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4000 2008 |
Instance |
I2C0 |
Description |
I2C Slave Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
DATA |
Data for transfer |
RW |
0x00 |
Address offset |
0x0000 000C |
||
Physical address |
0x4000 200C |
Instance |
I2C0 |
Description |
I2C Slave Interrupt Mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||
2 |
STOPIM |
Stop condition interrupt mask
|
RW |
0 |
|||||||||||||
1 |
STARTIM |
Start condition interrupt mask
|
RW |
0 |
|||||||||||||
0 |
DATAIM |
Data interrupt mask |
RW |
0 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4000 2010 |
Instance |
I2C0 |
Description |
I2C Slave Raw Interrupt Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
STOPRIS |
Stop condition raw interrupt status |
RO |
0 |
||
1 |
STARTRIS |
Start condition raw interrupt status |
RO |
0 |
||
0 |
DATARIS |
Data raw interrupt status |
RO |
0 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4000 2014 |
Instance |
I2C0 |
Description |
I2C Slave Masked Interrupt Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
STOPMIS |
Stop condition masked interrupt status |
RO |
0 |
||
1 |
STARTMIS |
Start condition masked interrupt status |
RO |
0 |
||
0 |
DATAMIS |
Data masked interrupt status |
RO |
0 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4000 2018 |
Instance |
I2C0 |
Description |
I2C Slave Interrupt Clear |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0000 0000 |
||
2 |
STOPIC |
Stop condition interrupt clear |
WO |
0 |
||
1 |
STARTIC |
Start condition interrupt clear |
WO |
0 |
||
0 |
DATAIC |
Data interrupt clear |
WO |
0 |
Address offset |
0x0000 0800 |
||
Physical address |
0x4000 2800 |
Instance |
I2C0 |
Description |
I2C Master Salve Address |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||
7:1 |
SA |
I2C master slave address |
RW |
0x00 |
|||||||||||||
0 |
RS |
Receive or Send
|
RW |
0 |
Address offset |
0x0000 0804 |
||
Physical address |
0x4000 2804 |
Instance |
I2C0 |
Description |
I2C Master Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
6 |
BUSBSY |
Bus busy |
RO |
0 |
||
5 |
IDLE |
I2C idle |
RO |
1 |
||
4 |
ARBLST |
Arbitration lost |
RO |
0 |
||
3 |
DATACK_N |
Data Was Not Acknowledge |
RO |
0 |
||
2 |
ADRACK_N |
Address Was Not Acknowledge |
RO |
0 |
||
1 |
ERR |
Error |
RO |
0 |
||
0 |
BUSY |
I2C busy |
RO |
0 |
Address offset |
0x0000 0804 |
||
Physical address |
0x4000 2804 |
Instance |
I2C0 |
Description |
I2C Master Control |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x000 0000 |
|||||||||||||
3 |
ACK |
Data acknowledge enable
|
WO |
0 |
|||||||||||||
2 |
STOP |
This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition.
|
WO |
0 |
|||||||||||||
1 |
START |
This bit-field generates the Start or Repeated Start condition.
|
WO |
0 |
|||||||||||||
0 |
RUN |
I2C master enable
|
WO |
0 |
Address offset |
0x0000 0808 |
||
Physical address |
0x4000 2808 |
Instance |
I2C0 |
Description |
I2C Master Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
DATA |
When Read: Last RX Data is returned |
RW |
0x00 |
Address offset |
0x0000 080C |
||
Physical address |
0x4000 280C |
Instance |
I2C0 |
Description |
I2C Master Timer Period |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7 |
TPR_7 |
Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. |
RW |
0 |
||
6:0 |
TPR |
SCL clock period |
RW |
0x01 |
Address offset |
0x0000 0810 |
||
Physical address |
0x4000 2810 |
Instance |
I2C0 |
Description |
I2C Master Interrupt Mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||
0 |
IM |
Interrupt mask
|
RW |
0 |
Address offset |
0x0000 0814 |
||
Physical address |
0x4000 2814 |
Instance |
I2C0 |
Description |
I2C Master Raw Interrupt Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
RIS |
Raw interrupt status |
RO |
0 |
Address offset |
0x0000 0818 |
||
Physical address |
0x4000 2818 |
Instance |
I2C0 |
Description |
I2C Master Masked Interrupt Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
MIS |
Masked interrupt status |
RO |
0 |
Address offset |
0x0000 081C |
||
Physical address |
0x4000 281C |
Instance |
I2C0 |
Description |
I2C Master Interrupt Clear |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x0000 0000 |
||
0 |
IC |
Interrupt clear |
WO |
0 |
Address offset |
0x0000 0820 |
||
Physical address |
0x4000 2820 |
Instance |
I2C0 |
Description |
I2C Master Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||
7:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
|||||||||||||
5 |
SFE |
I2C slave function enable
|
RW |
0 |
|||||||||||||
4 |
MFE |
I2C master function enable
|
RW |
0 |
|||||||||||||
3:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
|||||||||||||
0 |
LPBK |
I2C loopback
|
RW |
0 |
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