Instance: PRCM
Component: PRCM
Base address: 0x40000000
Power, Reset and Clock Management
Register Name |
Type |
Register Width (Bits) |
IR |
WO |
3 |
0 |
|
WO |
3 |
1 |
|
WO |
3 |
2 |
|
RO |
24 |
3 |
|
RO |
24 |
4 |
|
RO |
8 |
5 |
IR |
0 |
||
Description |
Force clocks to run |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
2 |
CLK_SYSBUS |
0: No action |
WO |
0 |
||
1 |
CLK_CPUFREE |
0: No action |
WO |
0 |
||
0 |
CLK_CPUCORE |
0: No action |
WO |
0 |
IR |
1 |
||
Description |
Force resets |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
2 |
RESET_SYSBUS_N |
0: Hold module in reset. No pulse generation. Must clear bit to 0 to release reset. |
WO |
1 |
||
1 |
SPARE |
Not connected in PRCM |
WO |
1 |
||
0 |
RESET_CPUCORE_N |
0: Hold module in reset. No pulse generation. Must clear bit to 0 to release reset. |
WO |
1 |
IR |
2 |
||
Description |
Force power domains on |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
2 |
POWER_ON_ALL |
0: No action |
WO |
0 |
||
1 |
CPU |
0: No action |
WO |
0 |
||
0 |
BUS |
0: No action |
WO |
0 |
IR |
3 |
||
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
23 |
OBS_CLK_I2S |
0: Clk not running |
RO |
0 |
||
22 |
OBS_CLK_SSI_1 |
0: Clk not running |
RO |
0 |
||
21 |
OBS_CLK_SSI_0 |
0: Clk not running |
RO |
0 |
||
20 |
OBS_CLK_UART_1 |
0: Clk not running |
RO |
0 |
||
19 |
OBS_CLK_UART_0 |
0: Clk not running |
RO |
0 |
||
18 |
OBS_CLK_I2C_1 |
0: Clk not running |
RO |
0 |
||
17 |
OBS_CLK_I2C_0 |
0: Clk not running |
RO |
0 |
||
16 |
OBS_CLK_SSI_DMA_1 |
0: Clk not running |
RO |
0 |
||
15 |
OBS_CLK_UART_DMA |
0: Clk not running |
RO |
0 |
||
14 |
OBS_CLK_GPTM_3 |
0: Clk not running |
RO |
0 |
||
13 |
OBS_CLK_GPTM_2 |
0: Clk not running |
RO |
0 |
||
12 |
OBS_CLK_GPTM_1 |
0: Clk not running |
RO |
0 |
||
11 |
OBS_CLK_GPTM_0 |
0: Clk not running |
RO |
0 |
||
10 |
OBS_CLK_GPIO |
0: Clk not running |
RO |
0 |
||
9 |
OBS_CLK_DMA |
0: Clk not running |
RO |
0 |
||
8 |
OBS_CLK_TRNG |
0: Clk not running |
RO |
0 |
||
7 |
OBS_CLK_SEC |
0: Clk not running |
RO |
0 |
||
6 |
OBS_CLK_PERBUSCPU |
0: Clk not running |
RO |
0 |
||
5 |
OBS_CLK_CPUCORE |
0: Clk not running |
RO |
0 |
||
4 |
OBS_CLK_CPUFREE |
0: Clk not running |
RO |
0 |
||
3 |
OBS_CLK_SYSBUS |
0: Clk not running |
RO |
0 |
||
2 |
OBS_CLK_FLASH |
0: Clk not running |
RO |
0 |
||
1 |
OBS_CLK_RFCORE |
0: Clk not running |
RO |
0 |
||
0 |
OBS_CLK_PERBUSULL |
0: Clk not running |
RO |
0 |
IR |
4 |
||
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
23 |
OBS_RESET_I2S_N |
0: Reset active |
RO |
0 |
||
22 |
OBS_RESET_SSI_N_1 |
0: Reset active |
RO |
0 |
||
21 |
OBS_RESET_SSI_N_0 |
0: Reset active |
RO |
0 |
||
20 |
OBS_RESET_UART_N_1 |
0: Reset active |
RO |
0 |
||
19 |
OBS_RESET_UART_N_0 |
0: Reset active |
RO |
0 |
||
18 |
OBS_RESET_I2C_N_1 |
0: Reset active |
RO |
0 |
||
17 |
OBS_RESET_I2C_N_0 |
0: Reset active |
RO |
0 |
||
16 |
OBS_RESET_PERDMA_N |
0: Reset active |
RO |
0 |
||
15 |
OBS_RESET_PERBUSDMA_N |
0: Reset active |
RO |
0 |
||
14 |
OBS_RESET_GPTM_N_3 |
0: Reset active |
RO |
0 |
||
13 |
OBS_RESET_GPTM_N_2 |
0: Reset active |
RO |
0 |
||
12 |
OBS_RESET_GPTM_N_1 |
0: Reset active |
RO |
0 |
||
11 |
OBS_RESET_GPTM_N_0 |
0: Reset active |
RO |
0 |
||
10 |
OBS_RESET_GPIO_N |
0: Reset active |
RO |
0 |
||
9 |
OBS_RESET_DMA_N |
0: Reset active |
RO |
0 |
||
8 |
OBS_RESET_TRNG_N |
0: Reset active |
RO |
0 |
||
7 |
OBS_RESET_SEC_N |
0: Reset active |
RO |
0 |
||
6 |
OBS_RESET_PERBUSCPU_N |
0: Reset active |
RO |
0 |
||
5 |
OBS_RESET_CPUCORE_N |
0: Reset active |
RO |
0 |
||
4 |
OBS_RESET_CPUFREE_N |
0: Reset active |
RO |
0 |
||
3 |
OBS_RESET_SYSBUS_N |
0: Reset active |
RO |
0 |
||
2 |
OBS_RESET_FLASH_N |
0: Reset active |
RO |
0 |
||
1 |
OBS_RESET_RFCORE_N |
0: Reset active |
RO |
0 |
||
0 |
OBS_RESET_PERBUSULL_N |
0: Reset active |
RO |
0 |
IR |
5 |
||
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
7 |
OBS_RFCORE |
0: Power domain off or in transition |
RO |
0 |
||
6 |
OBS_SERIAL |
0: Power domain off or in transition |
RO |
0 |
||
5 |
OBS_PERIPH |
0: Power domain off or in transition |
RO |
0 |
||
4 |
SPARE |
Identical to OBS_PERIPH |
RO |
0 |
||
3 |
OBS_CPU |
0: Power domain off or in transition |
RO |
0 |
||
2 |
OBS_VIMS |
0: Power domain off or in transition |
RO |
0 |
||
1 |
OBS_BUS |
0: Power domain off or in transition |
RO |
0 |
||
0 |
OBS_CLKCTRL |
0: Power domain off or in transition |
RO |
0 |
© 2015. Texas Instruments | All Rights Reserved |