CPU_TPIU

Instance: CPU_TPIU
Component: CPU_TPIU
Base address: 0xe0040000

 

Cortex-M3's Trace Port Interface Unit (TPIU)

 

TOP:CPU_TPIU Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SSPSR

RO

32

0x0000 000B

0x0000 0000

0xE004 0000

CSPSR

RW

32

0x0000 0001

0x0000 0004

0xE004 0004

ACPR

RW

32

0x0000 0000

0x0000 0010

0xE004 0010

SPPR

RW

32

0x0000 0001

0x0000 00F0

0xE004 00F0

FFSR

RO

32

0x0000 0008

0x0000 0300

0xE004 0300

FFCR

RW

32

0x0000 0102

0x0000 0304

0xE004 0304

FSCR

RO

32

0x0000 0000

0x0000 0308

0xE004 0308

CLAIMMASK

RO

32

0x0000 000F

0x0000 0FA0

0xE004 0FA0

CLAIMSET

WO

32

0x0000 000F

0x0000 0FA0

0xE004 0FA0

CLAIMTAG

RO

32

0x0000 0000

0x0000 0FA4

0xE004 0FA4

CLAIMCLR

WO

32

0x0000 0000

0x0000 0FA4

0xE004 0FA4

DEVID

RO

32

0x0000 0CA0

0x0000 0FC8

0xE004 0FC8

TOP:CPU_TPIU Register Descriptions

TOP:CPU_TPIU:SSPSR

Address offset

0x0000 0000

Physical address

0xE004 0000

Instance

CPU_TPIU

Description

Supported Sync Port Sizes Register
This register represents a single port size that is supported on the device, that is, 4, 2 or 1. This is to ensure that tools do not attempt to select a port width that an attached TPA cannot capture.

Type

RO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED4

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000 0000

3

FOUR

4-bit port size support

0x0: Not supported
0x1: Supported

RO

1

2

THREE

3-bit port size support

0x0: Not supported
0x1: Supported

RO

0

1

TWO

2-bit port size support

0x0: Not supported
0x1: Supported

RO

1

0

ONE

1-bit port size support

0x0: Not supported
0x1: Supported

RO

1



TOP:CPU_TPIU:CSPSR

Address offset

0x0000 0004

Physical address

0xE004 0004

Instance

CPU_TPIU

Description

Current Sync Port Size Register
This register has the same format as SSPSR but only one bit can be set, and all others must be zero. Writing values with more than one bit set, or setting a bit that is not indicated as supported can cause Unpredictable behavior. On reset this defaults to the smallest possible port size, 1 bit.

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

RESERVED4

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x000 0000

3

FOUR

4-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior.

RW

0

2

THREE

3-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior.

RW

0

1

TWO

2-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior.

RW

0

0

ONE

1-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior.

RW

1



TOP:CPU_TPIU:ACPR

Address offset

0x0000 0010

Physical address

0xE004 0010

Instance

CPU_TPIU

Description

Async Clock Prescaler Register
This register scales the baud rate of the asynchronous output.

Type

RW

Bits

Field Name

Description

Type

Reset

31:13

RESERVED13

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x0 0000

12:0

PRESCALER

Divisor for input trace clock is (PRESCALER + 1).

RW

0x0000



TOP:CPU_TPIU:SPPR

Address offset

0x0000 00F0

Physical address

0xE004 00F0

Instance

CPU_TPIU

Description

Selected Pin Protocol Register
This register selects the protocol to be used for trace output.
Note: If this register is changed while trace data is being output, data corruption occurs.

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x0000 0000

1:0

PROTOCOL

Trace output protocol

Value

ENUM name

Description

0x0

TRACEPORT

TracePort mode

0x1

SWO_MANCHESTER

SerialWire Output (Manchester). This is the reset value.

0x2

SWO_NRZ

SerialWire Output (NRZ)

RW

0x1



TOP:CPU_TPIU:FFSR

Address offset

0x0000 0300

Physical address

0xE004 0300

Instance

CPU_TPIU

Description

Formatter and Flush Status Register

Type

RO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED4

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x000 0000

3

FTNONSTOP

0: Formatter can be stopped
1: Formatter cannot be stopped

RO

1

2:0

RESERVED0

This field always reads as zero

RO

0x0



TOP:CPU_TPIU:FFCR

Address offset

0x0000 0304

Physical address

0xE004 0304

Instance

CPU_TPIU

Description

Formatter and Flush Control Register
When one of the two single wire output (SWO) modes is selected, ENFCONT enables the formatter to be bypassed. If the formatter is bypassed, only the ITM/DWT trace source (ATDATA2) passes through. The TPIU accepts and discards data that is presented on the ETM port (ATDATA1). This function is intended to be used when it is necessary to connect a device containing an ETM to a trace capture device that is only able to capture Serial Wire Output (SWO) data. Enabling or disabling the formatter causes momentary data corruption.
Note: If the selected pin protocol register (SPPR.PROTOCOL) is set to 0x00 (TracePort mode), this register always reads 0x102, because the formatter is automatically enabled. If one of the serial wire modes is then selected, the register reverts to its previously programmed value.

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

RESERVED9

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x00 0000

8

TRIGIN

Indicates that triggers are inserted when a trigger pin is asserted.

RW

1

7:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x00

1

ENFCONT

Enable continuous formatting:

0: Continuous formatting disabled
1: Continuous formatting enabled

RW

1

0

RESERVED0

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0



TOP:CPU_TPIU:FSCR

Address offset

0x0000 0308

Physical address

0xE004 0308

Instance

CPU_TPIU

Description

Formatter Synchronization Counter Register

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

FSCR

The global synchronization trigger is generated by the Program Counter (PC) Sampler block. This means that there is no synchronization counter in the TPIU.

RO

0x0000 0000



TOP:CPU_TPIU:CLAIMMASK

Address offset

0x0000 0FA0

Physical address

0xE004 0FA0

Instance

CPU_TPIU

Description

Claim Tag Mask Register

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

CLAIMMASK

This register forms one half of the Claim Tag value. When reading this register returns the number of bits that can be set (each bit is considered separately):

0: This claim tag bit is not implemented
1: This claim tag bit is not implemented

The behavior when writing to this register is described in CLAIMSET.

RO

0x0000 000F



TOP:CPU_TPIU:CLAIMSET

Address offset

0x0000 0FA0

Physical address

0xE004 0FA0

Instance

CPU_TPIU

Description

Claim Tag Set Register

Type

WO

Bits

Field Name

Description

Type

Reset

31:0

CLAIMSET

This register forms one half of the Claim Tag value. Writing to this location allows individual bits to be set (each bit is considered separately):

0: No effect
1: Set this bit in the claim tag

The behavior when reading from this location is described in CLAIMMASK.

WO

0x0000 000F



TOP:CPU_TPIU:CLAIMTAG

Address offset

0x0000 0FA4

Physical address

0xE004 0FA4

Instance

CPU_TPIU

Description

Current Claim Tag Register

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

CLAIMTAG

This register forms one half of the Claim Tag value. Reading this register returns the current Claim Tag value.
Reading CLAIMMASK determines how many bits from this register must be used.

The behavior when writing to this register is described in CLAIMCLR.

RO

0x0000 0000



TOP:CPU_TPIU:CLAIMCLR

Address offset

0x0000 0FA4

Physical address

0xE004 0FA4

Instance

CPU_TPIU

Description

Claim Tag Clear Register

Type

WO

Bits

Field Name

Description

Type

Reset

31:0

CLAIMCLR

This register forms one half of the Claim Tag value. Writing to this location enables individual bits to be cleared (each bit is considered separately):

0: No effect
1: Clear this bit in the claim tag.

The behavior when reading from this location is described in CLAIMTAG.

WO

0x0000 0000



TOP:CPU_TPIU:DEVID

Address offset

0x0000 0FC8

Physical address

0xE004 0FC8

Instance

CPU_TPIU

Description

Device ID Register

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

DEVID

This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no ETM present.

RO

0x0000 0CA0