Instance: ADI_1_SYNTH
Component: ADI_1_SYNTH
Base address: 0x10000000
ADI for synthesizer modules (analog part).
Registers Fields should be considered static unless otherwise noted (as dynamic)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
8 |
0x0000 0000 |
0x0000 0000 |
0x1000 0000 |
|
8 |
0x0000 0000 |
0x0000 0001 |
0x1000 0001 |
||
8 |
0x0000 0000 |
0x0000 0002 |
0x1000 0002 |
||
RW |
8 |
0x0000 0000 |
0x0000 0003 |
0x1000 0003 |
|
RW |
8 |
0x0000 0000 |
0x0000 0004 |
0x1000 0004 |
|
RW |
8 |
0x0000 0000 |
0x0000 0008 |
0x1000 0008 |
|
RW |
8 |
0x0000 0000 |
0x0000 0009 |
0x1000 0009 |
|
RW |
8 |
0x0000 0000 |
0x0000 000A |
0x1000 000A |
|
RO |
8 |
0x0000 0000 |
0x0000 000F |
0x1000 000F |
Address offset |
0x0000 0000 |
||
Physical address |
0x1000 0000 |
Instance |
ADI_1_SYNTH |
Description |
LDOVCO Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:5 |
RESERVED5 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
||
4 |
ATEST_V_EN |
Enables regulated output voltage to ATEST. |
RW |
0 |
||
3 |
BYPASS_REG_EN |
Bypass LDO and short VDDR and LDO output. |
RW |
0 |
||
2 |
RDY_EN |
Enable LDO ready Signal generation circuit. |
RW |
0 |
||
1 |
BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
||
0 |
EN |
Enable regulator for supplying VCO, VCO Divider |
RW |
0 |
Address offset |
0x0000 0001 |
||
Physical address |
0x1000 0001 |
Instance |
ADI_1_SYNTH |
Description |
Low DropOut Regulator for Voltage Controlled Oscillator Control 1 |
||
Type |
Bits |
Field Name |
Description |
Type |
Reset |
||
7 |
RESERVED7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
6 |
ATEST_I_EN |
Enable test current (2.5% of pass device current) to ATEST. |
RW |
0 |
||
5:0 |
TRIM_OUT |
Trim LDO's output voltage linearly with a signed 2's complement number. Step size is approximately 5 mV. |
RW |
0x00 |
Address offset |
0x0000 0002 |
||
Physical address |
0x1000 0002 |
Instance |
ADI_1_SYNTH |
Description |
Low DropOut Regulator for Voltage Controlled Oscillator Configuration |
||
Type |
Bits |
Field Name |
Description |
Type |
Reset |
||
7 |
RESERVED7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
6 |
DIV_BIAS_DIS |
Disable RF divider dummy bias current. |
RW |
0 |
||
5:3 |
COMP_RES |
Trim compensation resistor in series with Miller cap in nonlinear steps. Default should be 0x3. Unsigned number. |
RW |
0x0 |
||
2:0 |
COMP_CAP |
Trim compensation Miller cap in linear steps of 0.5 pF. Default should be 0x4. Unsigned. Tradeoff stability for speed. |
RW |
0x0 |
Address offset |
0x0000 0003 |
||
Physical address |
0x1000 0003 |
Instance |
ADI_1_SYNTH |
Description |
Synthesizer Low DropOut Regultaror Control 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
6 |
COMP_CAP |
Enable compensation cap |
RW |
0 |
||
5 |
ATEST_I_EN |
Enable test current (2% of pass device current) to ATEST. |
RW |
0 |
||
4 |
ATEST_V_EN |
Enables regulated output voltage to ATEST. |
RW |
0 |
||
3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
2 |
RDY_EN |
Enable LDO ready Signal generation circuit. |
RW |
0 |
||
1 |
BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
||
0 |
EN |
Enable regulator for supplying RF synthesizer core, TDC and clock retimer |
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x1000 0004 |
Instance |
ADI_1_SYNTH |
Description |
Synthesizer Low DropOut Regulator Control 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
5:0 |
TRIM_OUT |
Trim LDO's output voltage linearly with a signed 2's complement number. Step size is approximately 5 mV. |
RW |
0x00 |
Address offset |
0x0000 0008 |
||
Physical address |
0x1000 0008 |
Instance |
ADI_1_SYNTH |
Description |
Synthesizer Control of Initialisation |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:2 |
RESERVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
0x00 |
|||
1 |
CLK_EN |
Enable for clock from XOSC to synthesizer |
0 |
|||
0 |
DDI_RESET_N |
Reset digital core of synthesizer DDI |
0 |
Address offset |
0x0000 0009 |
||
Physical address |
0x1000 0009 |
Instance |
ADI_1_SYNTH |
Description |
Analog Test Control 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||
7:0 |
TESTSEL |
Control muxing of analog test signals from RF_TOP.
|
0x00 |
Address offset |
0x0000 000A |
||
Physical address |
0x1000 000A |
Instance |
ADI_1_SYNTH |
Description |
Analog Test Control 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||
7:2 |
RESEREVED2 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
0x00 |
||||||||||||||||||
1:0 |
TESTSEL |
Control muxing of analog test signals from RF_TOP.
|
0x0 |
Address offset |
0x0000 000F |
||
Physical address |
0x1000 000F |
Instance |
ADI_1_SYNTH |
Description |
Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
7:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
2 |
SYNTH_TUNE_ACK |
Acknowledgement from digital part of frequency synthesizer that the current calibration step has completed. |
RO |
0 |
||
1 |
SLDO_RDY |
Status of SLDO |
RO |
0 |
||
0 |
LDOVCO_RDY |
Status of LDOVCO. |
RO |
0 |
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