Instance: I2S0
Component: I2S
Base address: 0x40021000
I2S Audio DMA module supporting formats I2S, LJF, RJF and DSP
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4002 1000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4002 1004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4002 1008 |
|
RW |
32 |
0x0000 0170 |
0x0000 000C |
0x4002 100C |
|
RW |
32 |
0x0000 0003 |
0x0000 0010 |
0x4002 1010 |
|
RW |
32 |
0x0000 0003 |
0x0000 0014 |
0x4002 1014 |
|
RW |
32 |
0x0000 0003 |
0x0000 0018 |
0x4002 1018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x4002 101C |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x4002 1020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4002 1024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x4002 1028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x4002 102C |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x4002 1034 |
|
RO |
32 |
0x0000 0000 |
0x0000 0038 |
0x4002 1038 |
|
RO |
32 |
0x0000 0000 |
0x0000 003C |
0x4002 103C |
|
RO |
32 |
0x0000 0000 |
0x0000 0040 |
0x4002 1040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4002 1044 |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x4002 1048 |
|
RW |
32 |
0x0000 0000 |
0x0000 004C |
0x4002 104C |
|
RW |
32 |
0x0000 0000 |
0x0000 0050 |
0x4002 1050 |
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0x4002 1054 |
|
RW |
32 |
0x0000 FFFF |
0x0000 0058 |
0x4002 1058 |
|
RO |
32 |
0x0000 0000 |
0x0000 005C |
0x4002 105C |
|
RO |
32 |
0x0000 0000 |
0x0000 0060 |
0x4002 1060 |
|
RO |
32 |
0x0000 0000 |
0x0000 0064 |
0x4002 1064 |
|
RO |
32 |
0x0000 0000 |
0x0000 0068 |
0x4002 1068 |
|
RW |
32 |
0x0000 0000 |
0x0000 0070 |
0x4002 1070 |
|
RO |
32 |
0x0000 0000 |
0x0000 0074 |
0x4002 1074 |
|
WO |
32 |
0x0000 0000 |
0x0000 0078 |
0x4002 1078 |
|
WO |
32 |
0x0000 0000 |
0x0000 007C |
0x4002 107C |
Address offset |
0x0000 0000 |
||
Physical address |
0x4002 1000 |
Instance |
I2S0 |
Description |
WCLK Source Selection |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||
2 |
WCLK_INV |
Inverts WCLK source (pad or internal) when set. |
RW |
0 |
|||||||||||||||||||||
1:0 |
WCLK_SRC |
Selects WCLK source for AIF (should be the same as the BCLK source). The BCLK source is defined in the PRCM:I2SBCLKSEL.SRC
|
RW |
0x0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4002 1004 |
Instance |
I2S0 |
Description |
DMA Buffer Size Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
END_FRAME_IDX |
Defines the length of the Writing a non-zero value to this registerfield enables and initializes AIF. Note that before doing so, all other configuration must have been done, and AIFINPTR/AIFOUTPTR must have been loaded. |
RW |
0x00 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4002 1008 |
Instance |
I2S0 |
Description |
Pin Direction |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||
31:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||||||
9:8 |
AD2 |
Configures the AD2 audio data pin usage
|
RW |
0x0 |
|||||||||||||||||
7:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
|||||||||||||||||
5:4 |
AD1 |
Configures the AD1 audio data pin usage:
|
RW |
0x0 |
|||||||||||||||||
3:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
|||||||||||||||||
1:0 |
AD0 |
Configures the AD0 audio data pin usage:
|
RW |
0x0 |
Address offset |
0x0000 000C |
||
Physical address |
0x4002 100C |
Instance |
I2S0 |
Description |
Serial Interface Format Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
|||||||||||||
15:8 |
DATA_DELAY |
The number of BCLK periods between a WCLK edge and MSB of the first word in a phase: |
RW |
0x01 |
|||||||||||||
7 |
MEM_LEN_24 |
The size of each word stored to or loaded from memory:
|
RW |
0 |
|||||||||||||
6 |
SMPL_EDGE |
On the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK.
|
RW |
1 |
|||||||||||||
5 |
DUAL_PHASE |
Selects dual- or single-phase format. |
RW |
1 |
|||||||||||||
4:0 |
WORD_LEN |
Number of bits per word (8-24): |
RW |
0x10 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4002 1010 |
Instance |
I2S0 |
Description |
Word Selection Bit Mask for Pin 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 0000 |
||
7:0 |
MASK |
Bit-mask indicating valid channels in a frame on AD0. |
RW |
0x03 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4002 1014 |
Instance |
I2S0 |
Description |
Word Selection Bit Mask for Pin 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
MASK |
Bit-mask indicating valid channels in a frame on AD1. |
RW |
0x03 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4002 1018 |
Instance |
I2S0 |
Description |
Word Selection Bit Mask for Pin 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
MASK |
Bit-mask indicating valid channels in a frame on AD2 |
RW |
0x03 |
Address offset |
0x0000 001C |
||
Physical address |
0x4002 101C |
Instance |
I2S0 |
Description |
Audio Interface PWM Debug Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PULSE_WIDTH |
The value written to this register determines the width of the active high PWM pulse (pwm_debug), which starts together with MSB of the first output word in a DMA buffer: |
RW |
0x0000 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4002 1020 |
Instance |
I2S0 |
Description |
DMA Input Buffer Next Pointer |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
PTR |
Pointer to the first byte in the next DMA input buffer. |
RW |
0x0000 0000 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4002 1024 |
Instance |
I2S0 |
Description |
DMA Input Buffer Current Pointer |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
PTR |
Value of the DMA input buffer pointer currently used by the DMA controller. Incremented by 1 (byte) or 2 (word) for each AHB access. |
RW |
0x0000 0000 |
Address offset |
0x0000 0028 |
||
Physical address |
0x4002 1028 |
Instance |
I2S0 |
Description |
DMA Output Buffer Next Pointer |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
PTR |
Pointer to the first byte in the next DMA output buffer. |
RW |
0x0000 0000 |
Address offset |
0x0000 002C |
||
Physical address |
0x4002 102C |
Instance |
I2S0 |
Description |
DMA Output Buffer Current Pointer |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
PTR |
Value of the DMA output buffer pointer currently used by the DMA controller Incremented by 1 (byte) or 2 (word) for each AHB access. |
RW |
0x0000 0000 |
Address offset |
0x0000 0034 |
||
Physical address |
0x4002 1034 |
Instance |
I2S0 |
Description |
SampleStaMP Generator Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
OUT_RDY |
Low until the output pins are ready to be started by the samplestamp generator. When started (i.e. STMPOUTTRIG equals the WCLK counter) the bit goes back low. |
RO |
0 |
||
1 |
IN_RDY |
Low until the input pins are ready to be started by the samplestamp generator. When started (i.e. STMPINTRIG equals the WCLK counter) the bit goes back low. |
RO |
0 |
||
0 |
STMP_EN |
Enables the samplestamp generator. The samplestamp generator should only be enabled after it has been properly configured. |
RW |
0 |
Address offset |
0x0000 0038 |
||
Physical address |
0x4002 1038 |
Instance |
I2S0 |
Description |
Captured XOSC Counter Value, Capture Channel 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
CAPT_VALUE |
The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected WCLK. |
RO |
0x0000 |
Address offset |
0x0000 003C |
||
Physical address |
0x4002 103C |
Instance |
I2S0 |
Description |
XOSC Period Value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VALUE |
The number of 24 MHz clock cycles in the previous WCLK period (i.e. the next value of the XOSC counter at the positive WCLK edge, had it not been reset to 0). |
RO |
0x0000 |
Address offset |
0x0000 0040 |
||
Physical address |
0x4002 1040 |
Instance |
I2S0 |
Description |
Captured WCLK Counter Value, Capture Channel 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
CAPT_VALUE |
The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of positive WCLK edges since the samplestamp generator was enabled (not taking modification through STMPWADD/STMPWSET into account). |
RO |
0x0000 |
Address offset |
0x0000 0044 |
||
Physical address |
0x4002 1044 |
Instance |
I2S0 |
Description |
WCLK Counter Period Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VALUE |
Used to define when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer. This is thus a modulo value for the WCLK counter. This number should correspond to the size of the sample buffer used by the system (i.e. the index of the last sample plus 1). |
RW |
0x0000 |
Address offset |
0x0000 0048 |
||
Physical address |
0x4002 1048 |
Instance |
I2S0 |
Description |
WCLK Counter Trigger Value for Input Pins |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
IN_START_WCNT |
Compare value used to start the incoming audio streams. |
RW |
0x0000 |
Address offset |
0x0000 004C |
||
Physical address |
0x4002 104C |
Instance |
I2S0 |
Description |
WCLK Counter Trigger Value for Output Pins |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
OUT_START_WCNT |
Compare value used to start the outgoing audio streams. |
RW |
0x0000 |
Address offset |
0x0000 0050 |
||
Physical address |
0x4002 1050 |
Instance |
I2S0 |
Description |
WCLK Counter Set Operation |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VALUE |
WCLK counter modification: Sets the running WCLK counter equal to the written value. |
RW |
0x0000 |
Address offset |
0x0000 0054 |
||
Physical address |
0x4002 1054 |
Instance |
I2S0 |
Description |
WCLK Counter Add Operation |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VALUE_INC |
WCLK counter modification: Adds the written value to the running WCLK counter. If a positive edge of WCLK occurs at the same time as the operation, this will be taken into account. |
RW |
0x0000 |
Address offset |
0x0000 0058 |
||
Physical address |
0x4002 1058 |
Instance |
I2S0 |
Description |
XOSC Minimum Period Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
VALUE |
Each time STMPXPER is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register. |
RW |
0xFFFF |
Address offset |
0x0000 005C |
||
Physical address |
0x4002 105C |
Instance |
I2S0 |
Description |
Current Value of WCNT |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
CURR_VALUE |
Current value of the WCLK counter |
RO |
0x0000 |
Address offset |
0x0000 0060 |
||
Physical address |
0x4002 1060 |
Instance |
I2S0 |
Description |
Current Value of XCNT |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
CURR_VALUE |
Current value of the XOSC counter, latched when reading STMPWCNT. |
RO |
0x0000 |
Address offset |
0x0000 0064 |
||
Physical address |
0x4002 1064 |
Instance |
I2S0 |
Description |
Captured XOSC Counter Value, Capture Channel 1 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
CAPT_VALUE |
Channel 1 is idle and can not be sampled from an external pulse as with Channel 0 STMPXCNTCAPT0 |
RO |
0x0000 |
Address offset |
0x0000 0068 |
||
Physical address |
0x4002 1068 |
Instance |
I2S0 |
Description |
Captured WCLK Counter Value, Capture Channel 1 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
CAPT_VALUE |
Channel 1 is idle and can not be sampled from an external event as with Channel 0 STMPWCNTCAPT0 |
RO |
0x0000 |
Address offset |
0x0000 0070 |
||
Physical address |
0x4002 1070 |
Instance |
I2S0 |
Description |
I2S Masked Interrupt Status Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x000 0000 |
||
5 |
AIF_DMA_IN |
Defines the masks state for the interrupt of IRQFLAGS.AIF_DMA_IN |
RW |
0 |
||
4 |
AIF_DMA_OUT |
Defines the masks state for the interrupt of IRQFLAGS.AIF_DMA_OUT |
RW |
0 |
||
3 |
WCLK_TIMEOUT |
Defines the masks state for the interrupt of IRQFLAGS.WCLK_TIMEOUT |
RW |
0 |
||
2 |
BUS_ERR |
Defines the masks state for the interrupt of IRQFLAGS.BUS_ERR |
RW |
0 |
||
1 |
WCLK_ERR |
Defines the masks state for the interrupt of IRQFLAGS.WCLK_ERR |
RW |
0 |
||
0 |
PTR_ERR |
Defines the masks state for the interrupt of IRQFLAGS.PTR_ERR |
RW |
0 |
Address offset |
0x0000 0074 |
||
Physical address |
0x4002 1074 |
Instance |
I2S0 |
Description |
I2S Raw Interrupt Status Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
5 |
AIF_DMA_IN |
Set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTR), see description of AIFINPTR register |
RO |
0 |
||
4 |
AIF_DMA_OUT |
Set when condition for this bit field event occurs (auto cleared when output pointer is updated - AIFOUTPTR), see description of AIFOUTPTR register for details |
RO |
0 |
||
3 |
WCLK_TIMEOUT |
Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods. This signalizes that the internal or external BCLK and WCLK generator source has been disabled. |
RO |
0 |
||
2 |
BUS_ERR |
Set when a DMA operation is not completed in time (i.e. audio output buffer underflow, or audio input buffer overflow). |
RO |
0 |
||
1 |
WCLK_ERR |
Set when: |
RO |
0 |
||
0 |
PTR_ERR |
Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next block address in time. |
RO |
0 |
Address offset |
0x0000 0078 |
||
Physical address |
0x4002 1078 |
Instance |
I2S0 |
Description |
I2S Interrupt Set Register |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x000 0000 |
||
5 |
AIF_DMA_IN |
1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria was given at the same time, in which the set will be ignored) |
WO |
0 |
||
4 |
AIF_DMA_OUT |
1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria was given at the same time, in which the set will be ignored) |
WO |
0 |
||
3 |
WCLK_TIMEOUT |
1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT |
WO |
0 |
||
2 |
BUS_ERR |
1: Sets the interrupt of IRQFLAGS.BUS_ERR |
WO |
0 |
||
1 |
WCLK_ERR |
1: Sets the interrupt of IRQFLAGS.WCLK_ERR |
WO |
0 |
||
0 |
PTR_ERR |
1: Sets the interrupt of IRQFLAGS.PTR_ERR |
WO |
0 |
Address offset |
0x0000 007C |
||
Physical address |
0x4002 107C |
Instance |
I2S0 |
Description |
I2S Interrupt Clear Register |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text) |
WO |
0x000 0000 |
||
5 |
AIF_DMA_IN |
1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was given at the same time in which the clear will be ignored) |
WO |
0 |
||
4 |
AIF_DMA_OUT |
1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was given at the same time in which the clear will be ignored) |
WO |
0 |
||
3 |
WCLK_TIMEOUT |
1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was given at the same time in which the clear will be ignored) |
WO |
0 |
||
2 |
BUS_ERR |
1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given at the same time in which the clear will be ignored) |
WO |
0 |
||
1 |
WCLK_ERR |
1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was given at the same time in which the clear will be ignored) |
WO |
0 |
||
0 |
PTR_ERR |
1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given at the same time in which the clear will be ignored) |
WO |
0 |
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