CC26xx Driver Library
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Modules Pages
sys_ctrl.c
Go to the documentation of this file.
1 /******************************************************************************
2 * Filename: sys_ctrl.c
3 * Revised: 2015-01-15 14:12:37 +0100 (to, 15 jan 2015)
4 * Revision: 42392
5 *
6 * Description: Driver for the System Control.
7 *
8 * Copyright (c) 2015, Texas Instruments Incorporated
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1) Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 *
17 * 2) Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 *
21 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
22 * be used to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 ******************************************************************************/
38 
39 // Hardware headers
40 #include <inc/hw_types.h>
41 #include <inc/hw_ccfg.h>
42 // Driverlib headers
43 #include <driverlib/aon_batmon.h>
44 #include <driverlib/sys_ctrl.h>
45 
46 //*****************************************************************************
47 //
48 // Handle support for DriverLib in ROM:
49 // This section will undo prototype renaming made in the header file
50 //
51 //*****************************************************************************
52 #ifndef DRIVERLIB_GENERATE_ROM
53  #undef SysCtrlPowerEverything
54  #define SysCtrlPowerEverything NOROM_SysCtrlPowerEverything
55  #undef SysCtrlStandby
56  #define SysCtrlStandby NOROM_SysCtrlStandby
57  #undef SysCtrlPowerdown
58  #define SysCtrlPowerdown NOROM_SysCtrlPowerdown
59  #undef SysCtrlShutdown
60  #define SysCtrlShutdown NOROM_SysCtrlShutdown
61  #undef SysCtrlClockGet
62  #define SysCtrlClockGet NOROM_SysCtrlClockGet
63  #undef SysCtrlPeripheralClockGet
64  #define SysCtrlPeripheralClockGet NOROM_SysCtrlPeripheralClockGet
65  #undef SysCtrlResetSourceGet
66  #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet
67 #endif
68 
69 //*****************************************************************************
70 //
71 // Recharge calculator defines and globals
72 //
73 //*****************************************************************************
74 
75 #define PD_STATE_CACHE_RET 1
76 #define PD_STATE_RFMEM_RET 2
77 #define PD_STATE_XOSC_LPM 4
78 
79 typedef struct {
80  uint32_t pdTime ;
81  uint16_t pdRechargePeriod ;
82  uint8_t pdState ;
83  int8_t pdTemp ;
85 
86 static PowerQualGlobals_t powerQualGlobals;
87 
88 
89 //*****************************************************************************
90 //
91 // Arrays that maps the "peripheral set" number (which is stored in the
92 // third nibble of the PRCM_PERIPH_* defines) to the PRCM register that
93 // contains the relevant bit for that peripheral.
94 //
95 //*****************************************************************************
96 
97 // Run mode registers
98 static const uint32_t g_pui32ModuleCG[] =
99 {
113 };
114 
115 //*****************************************************************************
116 //
118 //
119 //*****************************************************************************
120 void
122 {
123  uint32_t ui32Idx;
124  uint32_t ui32AuxClocks;
125 
126  //
127  // Force power on AUX
128  //
131  { }
132 
133  //
134  // Enable all the AUX domain clocks and wait for them to be ready
135  //
136  ui32AuxClocks = AUX_WUC_ADI_CLOCK | AUX_WUC_OSCCTRL_CLOCK |
142  AUXWUCClockEnable(ui32AuxClocks);
143  while(AUXWUCClockStatus(ui32AuxClocks) != AUX_WUC_CLOCK_READY)
144  { }
145 
146  //
147  // Request to switch to the crystal to enable radio operation.
148  // It takes a while for the XTAL to be ready so it is possible to
149  // perform other tasks while waiting.
152 
153  //
154  // Switch the HF source to XTAL - must be performed safely out of ROM to
155  // avoid flash issues when switching the clock.
156  //
157  // NB. If already running XTAL on HF clock source the ROM will wait forever
158  // on a flag that will never be set - need to check.
159  //
162  }
163 
164  //
165  // Turn on all the MCU power domains
166  // If the CPU is running and executing code the SYSBUS, VIMS and CPU are
167  // automatically on as well.
168  //
171  //
172  // Wait for power to be on
173  //
176 
177  //
178  // Minimize all domain clock dividers and wait for the clock settings to
179  // take effect
180  //
184  PRCMLoadSet();
185  while(!PRCMLoadGet());
186 
187  //
188  // Ensure the domain clocks are running and wait for the clock settings to
189  // take effect
190  //
192  PRCMLoadSet();
193  while(!PRCMLoadGet())
194  { }
195 
196  //
197  // Enable all the RF Core clocks
198  // TBD Encapsulate in an API
199  //
200  // Do not read back to check, for two reasons:
201  // 1. CPE will update the PWMCLKENABLE register right after boot
202  // 2. The PWMCLKENABLE register always reads back what is written
203  HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x7FF;
204 
205  //
206  // Enable all peripheral clocks in CM3 run/sleep/deep-sleep mode.
207  //
208  for(ui32Idx = 0; ui32Idx < sizeof(g_pui32ModuleCG) / sizeof(uint32_t);
209  ui32Idx++)
210  {
211  PRCMPeripheralRunEnable(g_pui32ModuleCG[ui32Idx]);
212  PRCMPeripheralSleepEnable(g_pui32ModuleCG[ui32Idx]);
213  PRCMPeripheralDeepSleepEnable(g_pui32ModuleCG[ui32Idx]);
214  }
215  PRCMLoadSet();
216  while(!PRCMLoadGet())
217  { }
218 }
219 
220 //*****************************************************************************
221 //
223 //
224 //*****************************************************************************
225 void SysCtrlStandby(void)
226 {
227  //
228  // Enable the oscillator configuration interface
229  //
231 
232  //
233  // Ensure the low frequency clock source is sourced from a low frequency
234  // oscillator. The XTAL will provide the most accurate real time clock.
235  //
237 
238  //
239  // Enable the oscillator configuration interface
240  //
242 
243  //
244  // Execute the transition to standby
245  //
247 }
248 
249 //*****************************************************************************
250 //
252 //
253 //*****************************************************************************
254 void
256 {
257  //
258  // Make sure the oscillator interface is enabled
259  //
261 
262  //
263  // Source the LF clock from the low frequency XTAL_OSC.
264  // HF and MF are sourced from the high frequency RC_OSC.
265  //
268 
269  //
270  // Check if already sourcing the HF clock from RC_OSC.
271  // If a switch of the clock source is not required, then the call to ROM
272  // will loop forever.
273  //
275  {
277  }
278 
279  //
280  // Disable the oscillator interface
281  //
283 
284  //
285  // Execute the transition to power down.
286  //
288 }
289 
290 //*****************************************************************************
291 //
293 //
294 //*****************************************************************************
295 void
297 {
298  //
299  // Make sure the oscillator interface is enabled
300  //
302 
303  //
304  // Source the LF clock from the low frequency RC_OSC.
305  // HF and MF are sourced from the high frequency RC_OSC.
306  // TBD - Modify to source LF clock from XTAL
307  //
310 
311  //
312  // Check if already sourcing the HF clock from RC_OSC.
313  // If a switch of the clock source is not required, then the call to ROM
314  // will loop forever.
315  //
317  {
319  }
320 
321  //
322  // Disable the oscillator interface
323  //
325 
326  //
327  // Execute transition to shutdown.
328  //
330 }
331 
332 //*****************************************************************************
333 //
335 //
336 //*****************************************************************************
337 uint32_t
339 {
340  uint32_t ui32Div;
341 
342  //
343  // Get the current clock divider for the CPU.
344  //
345  ui32Div = HWREG(PRCM_BASE + PRCM_O_CPUCLKDIV) ? 2 : 1;
346 
347  //
348  // Get the current clock divider for the SYSBUS.
349  //
350  ui32Div <<= HWREG(PRCM_BASE + PRCM_O_SYSBUSCLKDIV);
351 
352  //
353  // Return the current value of the divided clock.
354  //
355  return (GET_MCU_CLOCK / ui32Div);
356 }
357 
358 //*****************************************************************************
359 //
361 //
362 //*****************************************************************************
363 uint32_t
364 SysCtrlPeripheralClockGet(uint32_t ui32Peripheral, uint32_t ui32BusMode)
365 {
366  uint32_t ui32SysBusDiv;
367  uint32_t ui32PerDiv;
368  uint32_t ui32Div;
369  uint32_t ui32ClkFreq;
370 
371  //
372  // Check the arguments.
373  //
374  ASSERT((ui32BusMode == SYSCTRL_SYSBUS_ON) ||
375  (ui32BusMode == SYSCTRL_SYSBUS_OFF));
376 
377  //
378  // Get the system bus clock divider.
379  //
380  ui32SysBusDiv = PRCMClockConfigureGet(PRCM_DOMAIN_SYSBUS);
381 
382  //
383  // Get the Peripheral clock divider.
384  //
386 
387  //
388  // Check clock mode.
389  //
390  ui32PerDiv = (ui32BusMode == SYSCTRL_SYSBUS_ON) ? ui32SysBusDiv : ui32PerDiv;
391 
392  //
393  // Check type of peripheral and return correct clock frequency.
394  //
395  switch(ui32Peripheral)
396  {
397  case PRCM_PERIPH_TIMER0 :
398  case PRCM_PERIPH_TIMER1 :
399  case PRCM_PERIPH_TIMER2 :
400  case PRCM_PERIPH_TIMER3 :
401  //
402  // Get the Timer clock divider and calculate the frequency.
403  //
405 
406  if(ui32PerDiv < ui32Div)
407  {
408  ui32ClkFreq = GET_MCU_CLOCK >> ui32Div;
409  }
410  else
411  {
412  ui32ClkFreq = GET_MCU_CLOCK >> ui32PerDiv;
413  }
414  break;
415  case PRCM_PERIPH_SSI0 :
416  case PRCM_PERIPH_SSI1 :
417  case PRCM_PERIPH_UART0 :
418  case PRCM_PERIPH_UART1 :
419  //
420  // Get the Serial clock divider and calculate the frequency.
421  //
423  ui32ClkFreq = GET_MCU_CLOCK >> ui32Div;
424  break;
425  case PRCM_PERIPH_I2C0 :
426  case PRCM_PERIPH_I2C1 :
427  case PRCM_PERIPH_UDMA :
428  case PRCM_PERIPH_TRNG :
429  case PRCM_PERIPH_CRYPTO :
430  case PRCM_PERIPH_GPIO :
431  case PRCM_PERIPH_I2S :
432  ui32ClkFreq = GET_MCU_CLOCK >> ui32PerDiv;
433  break;
434  default :
435  ui32ClkFreq = 0;
436  break;
437  }
438 
439  //
440  // Return the clock frequency.
441  //
442  return (ui32ClkFreq);
443 }
444 
445 
446 //*****************************************************************************
447 //
448 // SysCtrlSetRechargeBeforePowerDown( xoscPowerMode )
449 //
450 //*****************************************************************************
451 void
453 {
454  int32_t curTemp ;
455  int32_t shiftedTemp ;
456  uint32_t curState ;
457  uint32_t prcmRamRetention ;
458  uint32_t di ;
459  uint32_t dii ;
460  uint32_t ti ;
461  uint32_t cd ;
462  uint32_t cl ;
463  uint32_t load ;
464  uint32_t k ;
465  uint32_t vddrCap ;
466  uint32_t newRechargePeriod ;
467  uint32_t perE ;
468  uint32_t perM ;
469  const uint32_t * pLookupTable ;
470 
471  //--- Spec. point 1 ---
472  curTemp = AON_BatmonTempGetDegC();
473  curState = 0;
474  prcmRamRetention = HWREG( PRCM_BASE + PRCM_O_RAMRETEN );
475  if ( prcmRamRetention & PRCM_RAMRETEN_VIMS_M ) {
476  curState |= PD_STATE_CACHE_RET;
477  }
478  if ( prcmRamRetention & PRCM_RAMRETEN_RFC ) {
479  curState |= PD_STATE_RFMEM_RET;
480  }
481  if ( xoscPowerMode != XoscInHighPowerMode ) {
482  curState |= PD_STATE_XOSC_LPM;
483  }
484 
485  pLookupTable = (uint32_t *)( FCFG1_BASE + FCFG1_O_PWD_CURR_20C );
486 
487  //--- Spec. point 2 ---
488  if ((( curTemp - powerQualGlobals.pdTemp ) >= 5 ) || ( curState != powerQualGlobals.pdState )) {
489  //--- Spec. point 3 ---
490  shiftedTemp = curTemp - 15;
491 
492  //--- Spec point 4 ---
493  //4. Check for external VDDR load option (may not be supported): ext_load = (VDDR_EXT_LOAD=0 in CCFG)
494  // Currently not implementing external load handling
495  // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) {
496  // }
497 
498  //--- Spec point 5 ---
499  di = 0;
500  ti = 0;
501  if ( shiftedTemp >= 0 ) {
502  //--- Spec point 5.a ---
503  shiftedTemp += ( shiftedTemp << 4 );
504 
505  //--- Spec point 5.b ---
506  ti = ( shiftedTemp >> 8 );
507  if ( ti > 7 ) {
508  ti = 7;
509  }
510  dii = ti;
511  if ( dii > 6 ) {
512  dii = 6;
513  }
514 
515  //--- Spec point 5.c ---
516  cd = pLookupTable[ dii + 1 ] - pLookupTable[ dii ];
517 
518  //--- Spec point 5.d ---
519  di = cd & 0xFF;
520 
521  //--- Spec point 5.e ---
522  if ( curState & PD_STATE_XOSC_LPM ) {
523  di += (( cd >> 8 ) & 0xFF );
524  }
525  if ( curState & PD_STATE_RFMEM_RET ) {
526  di += (( cd >> 16 ) & 0xFF );
527  }
528  if ( curState & PD_STATE_CACHE_RET ) {
529  di += (( cd >> 24 ) & 0xFF );
530  }
531 
532  //--- Spec point 5.f ---
533  // Currently not implementing external load handling
534  }
535 
536  //--- Spec. point 6 ---
537  cl = pLookupTable[ ti ];
538 
539  //--- Spec. point 7 ---
540  load = cl & 0xFF;
541 
542  //--- Spec. point 8 ---
543  if ( curState & PD_STATE_XOSC_LPM ) {
544  load += (( cl >> 8 ) & 0xFF );
545  }
546  if ( curState & PD_STATE_RFMEM_RET ) {
547  load += (( cl >> 16 ) & 0xFF );
548  }
549  if ( curState & PD_STATE_CACHE_RET ) {
550  load += (( cl >> 24 ) & 0xFF );
551  }
552 
553  //--- Spec. point 9 ---
554  load += ((( di * ( shiftedTemp - ( ti << 8 ))) + 128 ) > 8 );
555 
556  // Currently not implementing external load handling
557  // if ( __ccfg.ulModeConfig & MODE_CONF_VDDR_EXT_LOAD ) {
558  //--- Spec. point 10 ---
559  // } else {
560  //--- Spec. point 11 ---
561  k = 468;
562  // }
563 
564  //--- Spec. point 12 ---
565 
567  newRechargePeriod = ( vddrCap * k ) / load;
568  if ( newRechargePeriod > 0xFFFF ) {
569  newRechargePeriod = 0xFFFF;
570  }
571  powerQualGlobals.pdRechargePeriod = newRechargePeriod;
572  }
573 
574  //--- Spec. point 13 ---
575  if ( curTemp > 127 ) curTemp = 127;
576  if ( curTemp < -128 ) curTemp = -128;
577  powerQualGlobals.pdTemp = curTemp;
578  powerQualGlobals.pdState = curState;
579  powerQualGlobals.pdTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC );
580 
581  // Calculate PER_E and PER_M (based on powerQualGlobals.pdRechargePeriod)
582  // Round downwards but make sure PER_E=0 and PER_M=1 is the minimum possible setting.
583  perE = 0;
584  perM = powerQualGlobals.pdRechargePeriod;
585  if ( perM < 31 ) {
586  perM = 31;
587  powerQualGlobals.pdRechargePeriod = 31;
588  }
589  while ( perM > 511 ) {
590  perM >>= 1;
591  perE += 1;
592  }
593  perM = ( perM - 15 ) >> 4;
594 
596  ( 0x80A4FF00 ) |
597  ( perM << AON_WUC_RECHARGECFG_PER_M_S ) |
598  ( perE << AON_WUC_RECHARGECFG_PER_E_S ) ;
599  HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) = 0;
600 }
601 
602 
603 //*****************************************************************************
604 //
605 // SysCtrlAdjustRechargeAfterPowerDown()
606 //
607 //*****************************************************************************
608 void
610 {
611  int32_t curTemp ;
612  uint32_t longestRechargePeriod ;
613  uint32_t newRechargePeriod ;
614 
615  //--- Spec. point 1 ---
616  curTemp = AON_BatmonTempGetDegC();
617  if ( curTemp < powerQualGlobals.pdTemp ) {
618  if ( curTemp < -128 ) {
619  curTemp = -128;
620  }
621  powerQualGlobals.pdTemp = curTemp;
622  }
623 
624  //--- Spec. point 2 ---
625  longestRechargePeriod = ( HWREG( AON_WUC_BASE + AON_WUC_O_RECHARGESTAT ) &
628 
629  if ( longestRechargePeriod == 0 ) {
630  //--- Spec. point 3 ---
631  powerQualGlobals.pdRechargePeriod >>= 1;
632  } else {
633  //--- Spec. point 4 ---
634  if ( longestRechargePeriod < powerQualGlobals.pdRechargePeriod ) {
635  powerQualGlobals.pdRechargePeriod = longestRechargePeriod;
636  } else {
637  //--- Spec. point 5 ---
638  uint32_t deltaTime = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ) - powerQualGlobals.pdTime + 1;
639  if ( deltaTime > 31 ) {
640  deltaTime = 31;
641  }
642  newRechargePeriod = powerQualGlobals.pdRechargePeriod + (( longestRechargePeriod - powerQualGlobals.pdRechargePeriod ) >> deltaTime );
643  if ( newRechargePeriod > 0xFFFF ) {
644  newRechargePeriod = 0xFFFF;
645  }
646  powerQualGlobals.pdRechargePeriod = newRechargePeriod;
647  }
648  }
649 }
650 
651 
652 //*****************************************************************************
653 //
654 // SysCtrl_DCDC_VoltageConditionalControl()
655 //
656 //*****************************************************************************
657 void
659 {
660  uint32_t batThreshold ;
661  uint32_t aonBatmonBat ;
662  uint32_t aonSysctlPwrctl ;
663  uint32_t ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
664 
665  //
666  // Check if Voltage Conditional Control is enabled
667  // It is enabled if both:
668  // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero).
669  // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 )
670  //
671  if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) ||
672  (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) &&
674  {
675  aonSysctlPwrctl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL );
676  aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT );
677  batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) &
679  CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 );
680 
681  if ( aonSysctlPwrctl & ( AON_SYSCTL_PWRCTL_DCDC_EN_M | AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M )) {
682  //
683  // DCDC is ON, check if it should be switched off
684  //
685  if ( aonBatmonBat < batThreshold ) {
687 
688  HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl;
689  }
690  } else {
691  //
692  // DCDC is OFF, check if it should be switched on
693  //
694  if ( aonBatmonBat > batThreshold ) {
695  if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_EN_M ;
696  if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonSysctlPwrctl |= AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M ;
697 
698  HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_PWRCTL ) = aonSysctlPwrctl;
699  }
700  }
701  }
702 }
703 
704 
705 //*****************************************************************************
706 //
707 // SysCtrlResetSourceGet()
708 //
709 //*****************************************************************************
710 uint32_t
712 {
714  return ( RSTSRC_WAKEUP_FROM_SHUTDOWN );
715  } else {
716  return (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) &
719  }
720 }
#define AUX_WUC_TDC_CLOCK
Definition: aux_wuc.h:113
uint32_t SysCtrlPeripheralClockGet(uint32_t ui32Peripheral, uint32_t ui32BusMode)
Get the clock for a peripheral.
Definition: sys_ctrl.c:364
#define PRCM_PERIPH_TIMER1
Definition: prcm.h:185
void AUXWUCClockEnable(uint32_t ui32Clocks)
Enable clocks for peripherals in the AUX domain.
Definition: aux_wuc.c:64
__STATIC_INLINE bool PRCMLoadGet(void)
Check if any of the load sensitive register has been updated.
Definition: prcm.h:608
#define OSC_SRC_CLK_MF
Definition: osc.h:107
#define AUX_WUC_OSCCTRL_CLOCK
Definition: aux_wuc.h:109
void SysCtrl_DCDC_VoltageConditionalControl(void)
Turns DCDC on or off depending of what’s considered to be optimal usage.
Definition: sys_ctrl.c:658
uint32_t AUXWUCClockStatus(uint32_t ui32Clocks)
Get the status of a clock.
Definition: aux_wuc.c:162
#define PRCM_PERIPH_TRNG
Definition: prcm.h:195
uint32_t PRCMClockConfigureGet(uint32_t ui32Domain)
Get the clock configuration for a specific sub system in the MCU Voltage Domain.
Definition: prcm.c:335
#define PRCM_PERIPH_I2S
Definition: prcm.h:198
#define AUX_WUC_SOC_CLOCK
Definition: aux_wuc.h:107
uint32_t OSCClockSourceGet(uint32_t ui32SrcClk)
Get the source clock settings.
Definition: osc.c:155
uint8_t pdState
Definition: sys_ctrl.c:82
#define PRCM_PERIPH_TIMER0
Definition: prcm.h:184
#define ASSERT(expr)
Definition: debug.h:65
uint32_t PRCMPowerDomainStatus(uint32_t ui32Domains)
Get the status for a specific power domain.
Definition: prcm.c:728
#define AUX_WUC_CLOCK_READY
Definition: aux_wuc.h:119
#define PRCM_PERIPH_UART1
Definition: prcm.h:191
uint32_t SysCtrlResetSourceGet(void)
Returns last reset source (including "wakeup from shutdown")
Definition: sys_ctrl.c:711
#define PRCM_DOMAIN_VIMS
Definition: prcm.h:146
__STATIC_INLINE void PRCMLoadSet(void)
Use this function to synchronize the load settings.
Definition: prcm.h:588
#define AUX_WUC_AIODIO0_CLOCK
Definition: aux_wuc.h:104
#define PD_STATE_XOSC_LPM
Definition: sys_ctrl.c:77
#define AUX_WUC_ADI_CLOCK
Definition: aux_wuc.h:110
#define PD_STATE_CACHE_RET
Definition: sys_ctrl.c:75
#define PRCM_PERIPH_TIMER2
Definition: prcm.h:186
void OSCInterfaceEnable(void)
Enable CM3 access to the OSC_DIG module.
Definition: osc.c:189
#define AONWUC_AUX_POWER_ON
Definition: aon_wuc.h:178
#define OSC_SRC_CLK_HF
Definition: osc.h:106
void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral)
Enables a peripheral in sleep mode.
Definition: prcm.c:648
#define OSC_RCOSC_HF
Definition: osc.h:110
#define AUX_WUC_AIODIO1_CLOCK
Definition: aux_wuc.h:105
#define PRCM_DOMAIN_PERIPH
Definition: prcm.h:142
#define OSC_XOSC_HF
Definition: osc.h:111
#define SYSCTRL_SYSBUS_ON
Definition: sys_ctrl.h:120
#define PRCM_PERIPH_SSI0
Definition: prcm.h:188
#define AONWUC_AUX_WAKEUP
Definition: aon_wuc.h:158
#define OSC_SRC_CLK_LF
Definition: osc.h:108
#define PRCM_PERIPH_TIMER3
Definition: prcm.h:187
#define PRCM_PERIPH_SSI1
Definition: prcm.h:189
int32_t AON_BatmonTempGetDegC(void)
Get the current temperature measurement as a signed value in Deg Celsius.
Definition: aon_batmon.c:55
#define PRCM_PERIPH_I2C1
Definition: prcm.h:193
void SysCtrlAdjustRechargeAfterPowerDown(void)
Adjust Recharge calculations to be used next.
Definition: sys_ctrl.c:609
void AONWUCAuxWakeupEvent(uint32_t ui32Mode)
Control the wake up procedure of the AUX domain.
Definition: aon_wuc.c:158
#define PRCM_DOMAIN_TIMER
Definition: prcm.h:150
#define AUX_WUC_SMPH_CLOCK
Definition: aux_wuc.h:103
#define SYSCTRL_SYSBUS_OFF
Definition: sys_ctrl.h:121
#define PD_STATE_RFMEM_RET
Definition: sys_ctrl.c:76
#define PRCM_PERIPH_CRYPTO
Definition: prcm.h:194
uint32_t SysCtrlClockGet(void)
Get the CPU core clock frequency.
Definition: sys_ctrl.c:338
void SysCtrlShutdown(void)
Force the system in to shutdown.
Definition: sys_ctrl.c:296
void SysCtrlStandby(void)
Force the system in to standby mode.
Definition: sys_ctrl.c:225
#define AUX_WUC_REF_CLOCK
Definition: aux_wuc.h:115
#define PRCM_PERIPH_GPIO
Definition: prcm.h:197
__STATIC_INLINE void OSCInterfaceDisable(void)
Disable CM3 access to the OSC_DIG module.
Definition: osc.h:303
#define PWRCTRL_STANDBY
Definition: pwr_ctrl.h:105
void PowerCtrlStateSet(uint32_t ui32Powerstate)
Force the system in to low power modes.
Definition: pwr_ctrl.c:60
#define PRCM_PERIPH_UART0
Definition: prcm.h:190
#define OSC_RCOSC_LF
Definition: osc.h:112
#define PRCM_PERIPH_UDMA
Definition: prcm.h:196
#define AUX_WUC_TDCIF_CLOCK
Definition: aux_wuc.h:108
#define PWRCTRL_SHUTDOWN
Definition: pwr_ctrl.h:107
#define PRCM_DOMAIN_SYSBUS
Definition: prcm.h:144
#define PRCM_CLOCK_DIV_1
Definition: prcm.h:122
#define PRCM_DOMAIN_POWER_ON
Definition: prcm.h:157
void PRCMPowerDomainOn(uint32_t ui32Domains)
Turn power on in power domains in the MCU domain.
Definition: prcm.c:514
When xosc_hf is in HIGH_POWER_XOSC.
Definition: sys_ctrl.h:295
#define PRCM_DOMAIN_SERIAL
Definition: prcm.h:140
XoscPowerMode_t
Enumeration describing possible input options to SysCtrlSetRechargeBeforePowerDown().
Definition: sys_ctrl.h:294
#define PRCM_DOMAIN_RFCORE
Definition: prcm.h:138
void PRCMClockConfigureSet(uint32_t ui32Domains, uint32_t ui32ClkDiv)
Setup the clock division factor for a subsystem in the MCU voltage domain.
Definition: prcm.c:276
#define PRCM_DOMAIN_CPU
Definition: prcm.h:148
void PRCMPeripheralRunEnable(uint32_t ui32Peripheral)
Enables a peripheral in Run mode.
Definition: prcm.c:608
void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral)
Enables a peripheral in deep-sleep mode.
Definition: prcm.c:688
uint32_t pdTime
Definition: sys_ctrl.c:80
#define AUX_WUC_ADC_CLOCK
Definition: aux_wuc.h:114
void SysCtrlPowerdown(void)
Force the system in to power down.
Definition: sys_ctrl.c:255
void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc)
Configure the oscillator input to the a source clock.
Definition: osc.c:85
__STATIC_INLINE void OSCHfSourceSwitch(void)
Switch the high frequency clock.
Definition: osc.h:265
#define RSTSRC_WAKEUP_FROM_SHUTDOWN
Definition: sys_ctrl.h:378
void SysCtrlSetRechargeBeforePowerDown(XoscPowerMode_t xoscPowerMode)
Set Recharge values before entering Power Down.
Definition: sys_ctrl.c:452
__STATIC_INLINE void PRCMDomainEnable(uint32_t ui32Domains)
Enable clock domains in the MCU voltage domain.
Definition: prcm.h:638
uint16_t pdRechargePeriod
Definition: sys_ctrl.c:81
__STATIC_INLINE uint32_t AONWUCPowerStatus(void)
Get the power status of the device.
Definition: aon_wuc.h:707
#define OSC_XOSC_LF
Definition: osc.h:113
#define PRCM_PERIPH_I2C0
Definition: prcm.h:192
#define PWRCTRL_POWER_DOWN
Definition: pwr_ctrl.h:106
#define AUX_WUC_TIMER_CLOCK
Definition: aux_wuc.h:106
void SysCtrlPowerEverything(void)
Power up everything.
Definition: sys_ctrl.c:121