Instance: CPU_ROM_TABLE
Component: CPU_ROM_TABLE
Base address: 0xe00ff000
Cortex-M's ROM table
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0xFFF0 F003 |
0x0000 0000 |
0xE00F F000 |
|
RO |
32 |
0xFFF0 2003 |
0x0000 0004 |
0xE00F F004 |
|
RO |
32 |
0xFFF0 3003 |
0x0000 0008 |
0xE00F F008 |
|
RO |
32 |
0xFFF0 1003 |
0x0000 000C |
0xE00F F00C |
|
RO |
32 |
0xFFF4 1003 |
0x0000 0010 |
0xE00F F010 |
|
RO |
32 |
0xFFF4 2002 |
0x0000 0014 |
0xE00F F014 |
|
RO |
32 |
0x0000 0000 |
0x0000 0018 |
0xE00F F018 |
|
RO |
32 |
0x0000 0001 |
0x0000 0FCC |
0xE00F FFCC |
Address offset |
0x0000 0000 |
||
Physical address |
0xE00F F000 |
Instance |
CPU_ROM_TABLE |
Description |
System Control Space Component |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
SCS |
Points to the SCS at 0xE000E000. |
RO |
0xFFF0 F003 |
Address offset |
0x0000 0004 |
||
Physical address |
0xE00F F004 |
Instance |
CPU_ROM_TABLE |
Description |
Data Watchpoint and Trace Component |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
DWT |
Points to the Data Watchpoint and Trace block at 0xE0001000. |
RO |
0x7FF8 1001 |
||
0 |
DWT_PRESENT |
RO |
1 |
Address offset |
0x0000 0008 |
||
Physical address |
0xE00F F008 |
Instance |
CPU_ROM_TABLE |
Description |
Flash Patch and Breakpoint Component |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
FPB |
Points to the Flash Patch and Breakpoint block at 0xE0002000. |
RO |
0x7FF8 1801 |
||
0 |
FPB_PRESENT |
RO |
1 |
Address offset |
0x0000 000C |
||
Physical address |
0xE00F F00C |
Instance |
CPU_ROM_TABLE |
Description |
Instrumentation Trace Component |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
ITM |
Points to the Instrumentation Trace block at 0xE0000000. |
RO |
0x7FF8 0801 |
||
0 |
ITM_PRESENT |
RO |
1 |
Address offset |
0x0000 0010 |
||
Physical address |
0xE00F F010 |
Instance |
CPU_ROM_TABLE |
Description |
Trace Port Interface Component |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
TPIU |
Points to the TPIU. TPIU is at 0xE0040000. |
RO |
0x7FFA 0801 |
||
0 |
TPIU_PRESENT |
RO |
1 |
Address offset |
0x0000 0014 |
||
Physical address |
0xE00F F014 |
Instance |
CPU_ROM_TABLE |
Description |
Enhanced Trace Component |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
ETM |
Points to the ETM. ETM is at 0xE0041000. |
RO |
0x7FFA 1001 |
||
0 |
ETM_PRESENT |
RO |
0 |
Address offset |
0x0000 0018 |
||
Physical address |
0xE00F F018 |
Instance |
CPU_ROM_TABLE |
Description |
End Marker |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
END |
End of the ROM table |
RO |
0x0000 0000 |
Address offset |
0x0000 0FCC |
||
Physical address |
0xE00F FFCC |
Instance |
CPU_ROM_TABLE |
Description |
System Memory Map Access for DAP |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
RESERVED1 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 0000 |
||
0 |
SYSTEM_ACCESS |
1: The system memory map is accessible using the DAP |
RO |
1 |
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