Instance: TEST
Component: TEST
Base address: 0x50000000
Debug subsystem. TAP interface to various modules.
Register Name |
Type |
Register Width (Bits) |
IR |
WO |
90 |
0 |
|
WO |
90 |
1 |
|
WO |
28 |
2 |
|
WO |
20 |
3 |
|
WO |
26 |
4 |
|
WO |
11 |
5 |
|
RO |
11 |
5 |
|
WO |
1 |
6 |
|
WO |
17 |
7 |
|
WO |
32 |
8 |
|
WO |
27 |
9 |
|
WO |
2 |
10 |
|
WO |
12 |
11 |
|
WO |
2 |
12 |
Bits |
Field Name |
Description |
Type |
Reset |
||
89 |
DOM_ENBL_0_89 |
Description required |
WO |
0 |
||
88 |
DOM_ENBL_0_88 |
Description required |
WO |
0 |
||
87 |
DOM_ENBL_0_87 |
Description required |
WO |
0 |
||
86 |
DOM_ENBL_0_86 |
Description required |
WO |
0 |
||
85 |
DOM_ENBL_0_85 |
Description required |
WO |
0 |
||
84 |
DOM_ENBL_0_84 |
Description required |
WO |
0 |
||
83 |
DOM_ENBL_0_83 |
Description required |
WO |
0 |
||
82 |
DOM_ENBL_0_82 |
Description required |
WO |
0 |
||
81 |
DOM_ENBL_0_81 |
Description required |
WO |
0 |
||
80 |
DOM_ENBL_0_80 |
Description required |
WO |
0 |
||
79 |
DOM_ENBL_0_79 |
Description required |
WO |
0 |
||
78 |
DOM_ENBL_0_78 |
Description required |
WO |
0 |
||
77 |
DOM_ENBL_0_77 |
Description required |
WO |
0 |
||
76 |
DOM_ENBL_0_76 |
Description required |
WO |
0 |
||
75 |
DOM_ENBL_0_75 |
Description required |
WO |
0 |
||
74 |
DOM_ENBL_0_74 |
Description required |
WO |
0 |
||
73 |
DOM_ENBL_0_73 |
Description required |
WO |
0 |
||
72 |
DOM_ENBL_0_72 |
Description required |
WO |
0 |
||
71 |
DOM_ENBL_0_71 |
Description required |
WO |
0 |
||
70 |
DOM_ENBL_0_70 |
Description required |
WO |
0 |
||
69 |
DOM_ENBL_0_69 |
Description required |
WO |
0 |
||
68 |
DOM_ENBL_0_68 |
Description required |
WO |
0 |
||
67 |
DOM_ENBL_0_67 |
Description required |
WO |
0 |
||
66 |
DOM_ENBL_0_66 |
Description required |
WO |
0 |
||
65 |
DOM_ENBL_0_65 |
Description required |
WO |
0 |
||
64 |
DOM_ENBL_0_64 |
Description required |
WO |
0 |
||
63 |
DOM_ENBL_0_63 |
Description required |
WO |
0 |
||
62 |
DOM_ENBL_0_62 |
Description required |
WO |
0 |
||
61 |
DOM_ENBL_0_61 |
Description required |
WO |
0 |
||
60 |
DOM_ENBL_0_60 |
Description required |
WO |
0 |
||
59 |
DOM_ENBL_0_59 |
Description required |
WO |
0 |
||
58 |
DOM_ENBL_0_58 |
Description required |
WO |
0 |
||
57 |
DOM_ENBL_0_57 |
Description required |
WO |
0 |
||
56 |
DOM_ENBL_0_56 |
Description required |
WO |
0 |
||
55 |
DOM_ENBL_0_55 |
Description required |
WO |
0 |
||
54 |
DOM_ENBL_0_54 |
Description required |
WO |
0 |
||
53 |
DOM_ENBL_0_53 |
Description required |
WO |
0 |
||
52 |
DOM_ENBL_0_52 |
Description required |
WO |
0 |
||
51 |
DOM_ENBL_0_51 |
Description required |
WO |
0 |
||
50 |
DOM_ENBL_0_50 |
Description required |
WO |
0 |
||
49 |
DOM_ENBL_0_49 |
Description required |
WO |
0 |
||
48 |
DOM_ENBL_0_48 |
Description required |
WO |
0 |
||
47 |
DOM_ENBL_0_47 |
Description required |
WO |
0 |
||
46 |
DOM_ENBL_0_46 |
Description required |
WO |
0 |
||
45 |
DOM_ENBL_0_45 |
Description required |
WO |
0 |
||
44 |
DOM_ENBL_0_44 |
Description required |
WO |
0 |
||
43 |
DOM_ENBL_0_43 |
Description required |
WO |
0 |
||
42 |
DOM_ENBL_0_42 |
Description required |
WO |
0 |
||
41 |
DOM_ENBL_0_41 |
Description required |
WO |
0 |
||
40 |
DOM_ENBL_0_40 |
Description required |
WO |
0 |
||
39 |
DOM_ENBL_0_39 |
Description required |
WO |
0 |
||
38 |
DOM_ENBL_0_38 |
Description required |
WO |
0 |
||
37 |
DOM_ENBL_0_37 |
Description required |
WO |
0 |
||
36 |
DOM_ENBL_0_36 |
Description required |
WO |
0 |
||
35 |
DOM_ENBL_0_35 |
Description required |
WO |
0 |
||
34 |
DOM_ENBL_0_34 |
Description required |
WO |
0 |
||
33 |
DOM_ENBL_0_33 |
Description required |
WO |
0 |
||
32 |
DOM_ENBL_0_32 |
Description required |
WO |
0 |
||
31 |
DOM_ENBL_0_31 |
Description required |
WO |
0 |
||
30 |
DOM_ENBL_0_30 |
Description required |
WO |
0 |
||
29 |
DOM_ENBL_0_29 |
Description required |
WO |
0 |
||
28 |
DOM_ENBL_0_28 |
Description required |
WO |
0 |
||
27 |
DOM_ENBL_0_27 |
Description required |
WO |
0 |
||
26 |
DOM_ENBL_0_26 |
Description required |
WO |
0 |
||
25 |
DOM_ENBL_0_25 |
Description required |
WO |
0 |
||
24 |
DOM_ENBL_0_24 |
Description required |
WO |
0 |
||
23 |
DOM_ENBL_0_23 |
Description required |
WO |
0 |
||
22 |
DOM_ENBL_0_22 |
Description required |
WO |
0 |
||
21 |
DOM_ENBL_0_21 |
Description required |
WO |
0 |
||
20 |
DOM_ENBL_0_20 |
Description required |
WO |
0 |
||
19 |
DOM_ENBL_0_19 |
Description required |
WO |
0 |
||
18 |
DOM_ENBL_0_18 |
Description required |
WO |
0 |
||
17 |
DOM_ENBL_0_17 |
Description required |
WO |
0 |
||
16 |
DOM_ENBL_0_16 |
Description required |
WO |
0 |
||
15 |
DOM_ENBL_0_15 |
Description required |
WO |
0 |
||
14 |
DOM_ENBL_0_14 |
Description required |
WO |
0 |
||
13 |
DOM_ENBL_0_13 |
Description required |
WO |
0 |
||
12 |
DOM_ENBL_0_12 |
Description required |
WO |
0 |
||
11 |
DOM_ENBL_0_11 |
Description required |
WO |
0 |
||
10 |
DOM_ENBL_0_10 |
Description required |
WO |
0 |
||
9 |
DOM_ENBL_0_9 |
Description required |
WO |
0 |
||
8 |
DOM_ENBL_0_8 |
Description required |
WO |
0 |
||
7 |
DOM_ENBL_0_7 |
Description required |
WO |
0 |
||
6 |
DOM_ENBL_0_6 |
Description required |
WO |
0 |
||
5 |
DOM_ENBL_0_5 |
Description required |
WO |
0 |
||
4 |
DOM_ENBL_0_4 |
Description required |
WO |
0 |
||
3 |
DOM_ENBL_0_3 |
Description required |
WO |
0 |
||
2 |
DOM_ENBL_0_2 |
Description required |
WO |
0 |
||
1 |
DOM_ENBL_0_1 |
Description required |
WO |
0 |
||
0 |
DOM_ENBL_0_0 |
Description required |
WO |
0 |
Bits |
Field Name |
Description |
Type |
Reset |
||
89 |
DOM_ENBL_1_89 |
Description required |
WO |
0 |
||
88 |
DOM_ENBL_1_88 |
Description required |
WO |
0 |
||
87 |
DOM_ENBL_1_87 |
Description required |
WO |
0 |
||
86 |
DOM_ENBL_1_86 |
Description required |
WO |
0 |
||
85 |
DOM_ENBL_1_85 |
Description required |
WO |
0 |
||
84 |
DOM_ENBL_1_84 |
Description required |
WO |
0 |
||
83 |
DOM_ENBL_1_83 |
Description required |
WO |
0 |
||
82 |
DOM_ENBL_1_82 |
Description required |
WO |
0 |
||
81 |
DOM_ENBL_1_81 |
Description required |
WO |
0 |
||
80 |
DOM_ENBL_1_80 |
Description required |
WO |
0 |
||
79 |
DOM_ENBL_1_79 |
Description required |
WO |
0 |
||
78 |
DOM_ENBL_1_78 |
Description required |
WO |
0 |
||
77 |
DOM_ENBL_1_77 |
Description required |
WO |
0 |
||
76 |
DOM_ENBL_1_76 |
Description required |
WO |
0 |
||
75 |
DOM_ENBL_1_75 |
Description required |
WO |
0 |
||
74 |
DOM_ENBL_1_74 |
Description required |
WO |
0 |
||
73 |
DOM_ENBL_1_73 |
Description required |
WO |
0 |
||
72 |
DOM_ENBL_1_72 |
Description required |
WO |
0 |
||
71 |
DOM_ENBL_1_71 |
Description required |
WO |
0 |
||
70 |
DOM_ENBL_1_70 |
Description required |
WO |
0 |
||
69 |
DOM_ENBL_1_69 |
Description required |
WO |
0 |
||
68 |
DOM_ENBL_1_68 |
Description required |
WO |
0 |
||
67 |
DOM_ENBL_1_67 |
Description required |
WO |
0 |
||
66 |
DOM_ENBL_1_66 |
Description required |
WO |
0 |
||
65 |
DOM_ENBL_1_65 |
Description required |
WO |
0 |
||
64 |
DOM_ENBL_1_64 |
Description required |
WO |
0 |
||
63 |
DOM_ENBL_1_63 |
Description required |
WO |
0 |
||
62 |
DOM_ENBL_1_62 |
Description required |
WO |
0 |
||
61 |
DOM_ENBL_1_61 |
Description required |
WO |
0 |
||
60 |
DOM_ENBL_1_60 |
Description required |
WO |
0 |
||
59 |
DOM_ENBL_1_59 |
Description required |
WO |
0 |
||
58 |
DOM_ENBL_1_58 |
Description required |
WO |
0 |
||
57 |
DOM_ENBL_1_57 |
Description required |
WO |
0 |
||
56 |
DOM_ENBL_1_56 |
Description required |
WO |
0 |
||
55 |
DOM_ENBL_1_55 |
Description required |
WO |
0 |
||
54 |
DOM_ENBL_1_54 |
Description required |
WO |
0 |
||
53 |
DOM_ENBL_1_53 |
Description required |
WO |
0 |
||
52 |
DOM_ENBL_1_52 |
Description required |
WO |
0 |
||
51 |
DOM_ENBL_1_51 |
Description required |
WO |
0 |
||
50 |
DOM_ENBL_1_50 |
Description required |
WO |
0 |
||
49 |
DOM_ENBL_1_49 |
Description required |
WO |
0 |
||
48 |
DOM_ENBL_1_48 |
Description required |
WO |
0 |
||
47 |
DOM_ENBL_1_47 |
Description required |
WO |
0 |
||
46 |
DOM_ENBL_1_46 |
Description required |
WO |
0 |
||
45 |
DOM_ENBL_1_45 |
Description required |
WO |
0 |
||
44 |
DOM_ENBL_1_44 |
Description required |
WO |
0 |
||
43 |
DOM_ENBL_1_43 |
Description required |
WO |
0 |
||
42 |
DOM_ENBL_1_42 |
Description required |
WO |
0 |
||
41 |
DOM_ENBL_1_41 |
Description required |
WO |
0 |
||
40 |
DOM_ENBL_1_40 |
Description required |
WO |
0 |
||
39 |
DOM_ENBL_1_39 |
Description required |
WO |
0 |
||
38 |
DOM_ENBL_1_38 |
Description required |
WO |
0 |
||
37 |
DOM_ENBL_1_37 |
Description required |
WO |
0 |
||
36 |
DOM_ENBL_1_36 |
Description required |
WO |
0 |
||
35 |
DOM_ENBL_1_35 |
Description required |
WO |
0 |
||
34 |
DOM_ENBL_1_34 |
Description required |
WO |
0 |
||
33 |
DOM_ENBL_1_33 |
Description required |
WO |
0 |
||
32 |
DOM_ENBL_1_32 |
Description required |
WO |
0 |
||
31 |
DOM_ENBL_1_31 |
Description required |
WO |
0 |
||
30 |
DOM_ENBL_1_30 |
Description required |
WO |
0 |
||
29 |
DOM_ENBL_1_29 |
Description required |
WO |
0 |
||
28 |
DOM_ENBL_1_28 |
Description required |
WO |
0 |
||
27 |
DOM_ENBL_1_27 |
Description required |
WO |
0 |
||
26 |
DOM_ENBL_1_26 |
Description required |
WO |
0 |
||
25 |
DOM_ENBL_1_25 |
Description required |
WO |
0 |
||
24 |
DOM_ENBL_1_24 |
Description required |
WO |
0 |
||
23 |
DOM_ENBL_1_23 |
Description required |
WO |
0 |
||
22 |
DOM_ENBL_1_22 |
Description required |
WO |
0 |
||
21 |
DOM_ENBL_1_21 |
Description required |
WO |
0 |
||
20 |
DOM_ENBL_1_20 |
Description required |
WO |
0 |
||
19 |
DOM_ENBL_1_19 |
Description required |
WO |
0 |
||
18 |
DOM_ENBL_1_18 |
Description required |
WO |
0 |
||
17 |
DOM_ENBL_1_17 |
Description required |
WO |
0 |
||
16 |
DOM_ENBL_1_16 |
Description required |
WO |
0 |
||
15 |
DOM_ENBL_1_15 |
Description required |
WO |
0 |
||
14 |
DOM_ENBL_1_14 |
Description required |
WO |
0 |
||
13 |
DOM_ENBL_1_13 |
Description required |
WO |
0 |
||
12 |
DOM_ENBL_1_12 |
Description required |
WO |
0 |
||
11 |
DOM_ENBL_1_11 |
Description required |
WO |
0 |
||
10 |
DOM_ENBL_1_10 |
Description required |
WO |
0 |
||
9 |
DOM_ENBL_1_9 |
Description required |
WO |
0 |
||
8 |
DOM_ENBL_1_8 |
Description required |
WO |
0 |
||
7 |
DOM_ENBL_1_7 |
Description required |
WO |
0 |
||
6 |
DOM_ENBL_1_6 |
Description required |
WO |
0 |
||
5 |
DOM_ENBL_1_5 |
Description required |
WO |
0 |
||
4 |
DOM_ENBL_1_4 |
Description required |
WO |
0 |
||
3 |
DOM_ENBL_1_3 |
Description required |
WO |
0 |
||
2 |
DOM_ENBL_1_2 |
Description required |
WO |
0 |
||
1 |
DOM_ENBL_1_1 |
Description required |
WO |
0 |
||
0 |
DOM_ENBL_1_0 |
Description required |
WO |
0 |
IR |
2 |
||
Description |
Description required |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
27 |
SLDO_BYPASS_EN |
Description required |
WO |
0 |
||
26 |
VDD_BYPASS_EN |
Description required |
WO |
0 |
||
25 |
MCU_PSCON_SPARE |
Description required |
WO |
0 |
||
24 |
MCU_PSCON_AONONLY_SEL |
Description required |
WO |
0 |
||
23 |
MCU_PSCON_TSTCLK_BYPASS |
Description required |
WO |
0 |
||
22 |
MCU_PSCON_BLOCKOUT |
Description required |
WO |
0 |
||
21 |
MCU_PSCON_MODE |
Description required |
WO |
0 |
||
20 |
MCU_PSCON_MCUTM_SEL |
Description required |
WO |
0 |
||
19 |
SPARE |
Description required |
WO |
0 |
||
18 |
TEST_TAP_CLK_MX_SEL |
Description required |
WO |
0 |
||
17 |
PACKAGED_DEVIC |
(REPLACEDWITHVDD/SLDOBYPASSEN). Description required |
WO |
0 |
||
16 |
BURNIN_MODE |
Description required |
WO |
0 |
||
15 |
IO_FLASH_IDDQ_MODE |
(+TRNG). Description required |
WO |
0 |
||
14 |
LCG_BROADCAST_EN |
Description required |
WO |
0 |
||
13 |
DTCTESTSIGDFT_ISO_LATCH_OVERRIDE |
Description required |
WO |
0 |
||
12 |
DTCTESTSIGDFT_ISO_EN_OVERRIDE |
Description required |
WO |
0 |
||
11 |
ISOTESTMODE |
Description required |
WO |
0 |
||
10 |
SHAPER_ON |
Description required |
WO |
0 |
||
9 |
SHAPER_CLK_EN |
Description required |
WO |
0 |
||
8 |
TEST_EVENT_CTRL |
Description required |
WO |
0 |
||
7 |
TEST_LATCH_EN |
Description required |
WO |
0 |
||
6 |
TEST_CLK_BYPASS |
Description required |
WO |
0 |
||
5 |
TFTMODE |
Description required |
WO |
0 |
||
4 |
DTCTESTSIGPCG_EN |
Description required |
WO |
0 |
||
3 |
CLKINVDIS |
Description required |
WO |
0 |
||
2 |
RCG_EN |
Description required |
WO |
0 |
||
1 |
LCG_CTRL_EN_N |
Description required |
WO |
0 |
||
0 |
DFT_RST_BYPASS |
Description required |
WO |
0 |
IR |
3 |
||
Description |
Description required |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
19:17 |
SPARE |
Description required |
WO |
0x0 |
||
16 |
ONE_HOT_CLUSTER_LCG_DOMAIN_EN_MODE |
Description required |
WO |
0 |
||
15:14 |
MR_DR |
Description required |
WO |
0x0 |
||
13 |
MARGIN_MODE_OVRD |
Description required |
WO |
0 |
||
12 |
GLG_VDDAR_VDD_SW |
Description required |
WO |
0 |
||
11 |
PBIST_MODE |
Description required |
WO |
0 |
||
10 |
GXG_DFT_MODE |
Description required |
WO |
0 |
||
9 |
GLX_DFT_MODE |
Description required |
WO |
0 |
||
8 |
GLG_DFT_MODE |
Description required |
WO |
0 |
||
7 |
GLG_VDDAR_SW |
Description required |
WO |
0 |
||
6 |
GLGULL_VDDAR_VDD_SW |
Description required |
WO |
0 |
||
5 |
PBIST_COMBINER_SEL |
Description required |
WO |
0 |
||
4 |
PBIST_DATALOG_EN |
Description required |
WO |
0 |
||
3:1 |
COMPMODE |
001: 4 si/so bypass |
WO |
0x0 |
||
0 |
ATPG_MODE |
Description required |
WO |
0 |
IR |
4 |
||
Description |
Spare?? Doesn't look like a spare to me.. |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
25 |
DTC_DTC_SIGNAL_SPARE25 |
Description required |
WO |
0 |
||
24 |
DTC_TEST_SIGNAL_SPARE |
Description required |
WO |
0 |
||
23 |
PARTIAL_SCAN_SPARE |
Description required |
WO |
0 |
||
22 |
PARTIAL_SCAN_FLASH |
Description required |
WO |
0 |
||
21 |
RARTIAL_SCAN_RAM_ROM |
Description required |
WO |
0 |
||
20 |
PARTIAL_SCAN_DLO_DTX |
Description required |
WO |
0 |
||
19 |
PARTIAL_SCAN_OSCDIG_DCDC_ADC |
Description required |
WO |
0 |
||
18 |
PARTIAL_SCAN_ADI3_ADI4 |
Description required |
WO |
0 |
||
17 |
PARTIAL_SCAN_ADI1 |
Description required |
WO |
0 |
||
16 |
PARTIAL_SCAN_ADI0_ADI2 |
Description required |
WO |
0 |
||
15 |
DTC_DTC_SIGNAL_SPARE |
Description required |
WO |
0 |
||
14 |
DTC_DTC_SIGNAL_T2C_DFT_RETENTION |
Description required |
WO |
0 |
||
13 |
DTC_DTC_SIGNAL_DFT_ISO_LATCH_OVERRIDE |
Description required |
WO |
0 |
||
12 |
DTC_DTC_SIGNAL_DFT_ISO_EN_OVERRIDE |
Description required |
WO |
0 |
||
11 |
T2C_VDDAR_SW_OVERRIDE |
Description required |
WO |
0 |
||
10 |
EFC_EFCCLK_CLKINEN_ |
Description required |
WO |
0 |
||
9 |
DEBUGSS_CLK_BYPASS |
Description required |
WO |
0 |
||
8 |
DEBUGSS_PCG_EN |
Description required |
WO |
0 |
||
7 |
DEBUGSS_RCG_EN |
Description required |
WO |
0 |
||
6 |
DTC_DTC_SIGNAL_PCG_EN |
Description required |
WO |
0 |
||
5 |
DTC_DTC_SIGNAL_ISOOVERRIDE_MEM |
Description required |
WO |
0 |
||
4 |
DTC_DTC_SIGNAL_ISOOVERRIDE |
Description required |
WO |
0 |
||
3 |
DTC_DTC_SIGNAL_DFT_RST_N |
Description required |
WO |
0 |
||
2 |
DTC_TEST_SIGNAL_ISOOVERRIDE_MEM |
Description required |
WO |
0 |
||
1 |
DTC_TEST_SIGNAL_ISOOVERRIDE |
Description required |
WO |
0 |
||
0 |
SPARE0 |
Description required |
WO |
0 |
IR |
5 |
||
Description |
Description required |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
10 |
GONOGOEN |
Description required |
WO |
0 |
||
9 |
GONOGORESETN |
Description required |
WO |
0 |
||
8 |
TST_FRO_DELAY |
Description required |
WO |
0 |
||
7 |
TST_FRO_ENABLE |
Description required |
WO |
0 |
||
6:2 |
TST_FRO_SELECT |
Description required |
WO |
0x00 |
||
1 |
TESTOSC |
Description required |
WO |
0 |
||
0 |
TST_FRO_CTRL_EN |
Description required |
WO |
0 |
IR |
5 |
||
Description |
Description required |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
10 |
GONOGO |
Description required |
RO |
0 |
||
9:0 |
SPARE0 |
Description required |
RO |
0x000 |
IR |
6 |
||
Description |
Description required |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
0 |
TITAN_SPARE |
Description required |
WO |
0 |
IR |
7 |
||
Description |
Description required |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
16 |
SPARE |
Description required |
WO |
0 |
||
15 |
TITAN_SCAN_PIPE_BYPASS_EN_DR |
Description required |
WO |
0 |
||
14 |
TITAN_IODFT_EN_STICKY_ERROR |
Description required |
WO |
0 |
||
13 |
TITAN_IODFT_GZ |
Description required |
WO |
0 |
||
12 |
TITAN_BURNIN_MODE_DR |
Description required |
WO |
0 |
||
11 |
TITAN_INTRL_SCAN_EN_DR |
Description required |
WO |
0 |
||
10 |
TITAN_JTAG_IO_BYPASS_EN_DR |
Description required |
WO |
0 |
||
9 |
IO_LBEN |
Description required |
WO |
0 |
||
8 |
IO_LATCHCTRL |
Description required |
WO |
0 |
||
7 |
TITAN_IO_TESTMODE |
Description required |
WO |
0 |
||
6 |
TITAN_IODFT_ERR_OUT_SEL_DR |
Description required |
WO |
0 |
||
5 |
TITAN_EXTRNL_SCAN_EN_DR |
Description required |
WO |
0 |
||
4 |
TITAN_IODFT_MODE_DR |
Description required |
WO |
0 |
||
3 |
TITAN_PBIST_MODE_DR |
Description required |
WO |
0 |
||
2 |
TITAN_ESTAC_SRL_MODE_DR |
Description required |
WO |
0 |
||
1 |
TITAN_ATPG_MODE_DR |
Description required |
WO |
0 |
||
0 |
CNTRL |
Description required |
WO |
0 |
IR |
8 |
||
Description |
Description required |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TITAN_IODFT_MASK_DR |
Description required |
WO |
0x0000 0000 |
IR |
9 |
||
Description |
Description required |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
26:25 |
SPARE |
Description required |
WO |
0x0 |
||
24:23 |
TITAN_CAPT_CNT_DR |
Description required |
WO |
0x0 |
||
22:20 |
TITAN_SCAN_CAPT_OFFSET_DR |
Description required |
WO |
0x0 |
||
19:17 |
BYTEFILL |
Description required |
WO |
0x0 |
||
16:12 |
TITAN_SCAN_OFF_CNT_DR |
Description required |
WO |
0x00 |
||
11:0 |
TITAN_SCAN_ON_CNT_DR |
Description required |
WO |
0x000 |
IR |
10 |
||
Description |
Description required |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
1 |
MCU_ATPG_SO7 |
Description required |
WO |
0 |
||
0 |
TEST_TAP_TDI9 |
Description required |
WO |
0 |
IR |
11 |
||
Description |
On Device Process Monitor Controll This register controls the ODP monitor in the analog domain directly. |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
11 |
SENSE_ENABLE_2 |
Enable Tgate that connects VDD to VSENSE |
WO |
0 |
||
10 |
SENSE_ENABLE_1 |
Enable Tgate that connects VSS to VSENSE |
WO |
0 |
||
9 |
SENSE_ENABLE_0 |
Enable Tgate that connects IFORCE to VSENSE |
WO |
0 |
||
8 |
GATE_DRIVE_ENABLE |
0: Ngate=VDD and Pgate=VSS |
WO |
0 |
||
7 |
XTR_TYPE |
NMOS/PMOS DUT gate selection |
WO |
0 |
||
6:1 |
DUT_ENABLE |
Enable NMOS-PMOS DUT[5:0] |
WO |
0x00 |
||
0 |
SELECT |
Enable ODP |
WO |
0 |
IR |
12 |
||
Description |
Description required |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
1 |
ESTAC_SO |
Description required |
WO |
0 |
||
0 |
TEST_TAP_TDI12 |
Description required |
WO |
0 |
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