AON_WUC

Instance: AON_WUC
Component: AON_WUC
Base address: 0x40091000

 

This component control the Wakeup controller residing in the AON domain.

Note: This module is only supporting 32 bit ReadWrite access from MCU

 

TOP:AON_WUC Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

MCUCLK

RW

32

0x0000 0000

0x0000 0000

0x4009 1000

AUXCLK

RW

32

0x0000 0001

0x0000 0004

0x4009 1004

MCUCFG

RW

32

0x0000 000F

0x0000 0008

0x4009 1008

AUXCFG

RW

32

0x0000 0001

0x0000 000C

0x4009 100C

AUXCTL

RW

32

0x0000 0000

0x0000 0010

0x4009 1010

PWRSTAT

RW

32

0x0380 0000

0x0000 0014

0x4009 1014

SHUTDOWN

RW

32

0x0000 0000

0x0000 0018

0x4009 1018

CTL0

RW

32

0x0000 0000

0x0000 0020

0x4009 1020

CTL1

RW

32

0x0000 0000

0x0000 0024

0x4009 1024

RECHARGECFG

RW

32

0x0000 0000

0x0000 0030

0x4009 1030

RECHARGESTAT

RW

32

0x0000 0000

0x0000 0034

0x4009 1034

OSCCFG

RW

32

0x0000 0000

0x0000 0038

0x4009 1038

JTAGCFG

RW

32

0x0000 0100

0x0000 0040

0x4009 1040

JTAGUSERCODE

RW

32

0x0B99 A02F

0x0000 0044

0x4009 1044

TOP:AON_WUC Register Descriptions

TOP:AON_WUC:MCUCLK

Address offset

0x0000 0000

Physical address

0x4009 1000

Instance

AON_WUC

Description

MCU Clock Management

This register contains bitfields related to the MCU clock.

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2

RCOSC_HF_CAL_DONE

MCU bootcode will set this bit when RCOSC_HF is calibrated. The FLASH can not be used until this bit is set.

1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up.
0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF is safe

RW

0

1:0

PWR_DWN_SRC

Controls the clock source for the entire MCU domain while MCU is requesting powerdown.

When MCU requests powerdown with SCLK_HF as source, then WUC will switch over to this clock source during powerdown, and automatically switch back to SCLK_HF when MCU is no longer requesting powerdown and system is back in active mode.

Value

ENUM name

Description

0x0

NONE

No clock in Powerdown

0x1

SCLK_LF

Use SCLK_LF in Powerdown

0x2

SCLK_MF

Use SCLK_MF in Powerdown

RW

0x0



TOP:AON_WUC:AUXCLK

Address offset

0x0000 0004

Physical address

0x4009 1004

Instance

AON_WUC

Description

AUX Clock Management

This register contains bitfields that are relevant for setting up the clock to the AUX domain.

Type

RW

Bits

Field Name

Description

Type

Reset

31:13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

12:11

PWR_DWN_SRC

When AUX requests powerdown with SCLK_HF as source, then WUC will switch over to this clock source during powerdown, and automatically switch back to SCLK_HF when AUX system is back in active mode

Value

ENUM name

Description

0x0

NONE

No clock in Powerdown

0x1

SCLK_LF

Use SCLK_LF in Powerdown

0x2

SCLK_MF

Use SCLK_MF in Powerdown

RW

0x0

10:8

SCLK_HF_DIV

Select the AUX clock divider for SCLK_HF

NB: It is not supported to change the AUX clock divider while SCLK_HF is active source for AUX

Value

ENUM name

Description

0x0

DIV2

Divide by 2

0x1

DIV4

Divide by 4

0x2

DIV8

Divide by 8

0x3

DIV16

Divide by 16

0x4

DIV32

Divide by 32

0x5

DIV64

Divide by 64

0x6

DIV128

Divide by 128

0x7

DIV256

Divide by 256

RW

0x0

7:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

2:0

SRC

Selects the clock source for AUX:

NB: Switching the clock source is guaranteed to be glitchless

Value

ENUM name

Description

0x1

SCLK_HF

HF Clock (SCLK_HF)

0x2

SCLK_MF

MF Clock (SCLK_MF)

0x4

SCLK_LF

LF Clock (SCLK_LF)

RW

0x1



TOP:AON_WUC:MCUCFG

Address offset

0x0000 0008

Physical address

0x4009 1008

Instance

AON_WUC

Description

MCU Configuration

This register contains power management related bitfields for the MCU domain.

Type

RW

Bits

Field Name

Description

Type

Reset

31:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

17

VIRT_OFF

Controls action taken when receiving a request to power-off MCU domain:

0: Power-off MCU
1: Assert reset and stop clock, but keep MCU powered (virtual power-off)

RW

0

16

FIXED_WU_EN

Controls timing of MCU wakeup:

0: MCU wake-up is immediately following triggering event
1: MCU wake-up is forced to happen a fixed number of 32 KHz clocks following the triggering event.

The number of 32 KHz clock cycles is configured in CTL0.FIXED_WU_PER register
This bit is used to ensure that the MCU is always woken up an exact number of clocks following the triggering event by compensating for any variable delays caused by other activities going on at the time of wakeup (such as a recharge event etc.)

RW

0

15:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

3:0

SRAM_RET_EN

MCU SRAM is partitioned into 4 banks . This register controls which of the banks that has retention during MCU power off

Value

ENUM name

Description

0x0

RET_NONE

Retention is disabled

0x1

RET_LEVEL1

Retention on for SRAM:BANK0

0x3

RET_LEVEL2

Retention on for SRAM:BANK0 and SRAM:BANK1

0x7

RET_LEVEL3

Retention on for SRAM:BANK0, SRAM:BANK1 and SRAM:BANK2

0xF

RET_FULL

Retention on for all banks (SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2 and SRAM:BANK3)

RW

0xF



TOP:AON_WUC:AUXCFG

Address offset

0x0000 000C

Physical address

0x4009 100C

Instance

AON_WUC

Description

AUX Configuration

This register contains power management related signals for the AUX domain.

Type

RW

Bits

Field Name

Description

Type

Reset

31:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

17

VIRT_OFF

Controls action taken when receiving a request to power AUX domain off:

0: Power-off AUX
1: Assert reset and stop clock, but keep AUX powered (virtual power-off)

RW

0

16

FIXED_WU_EN

Controls timing of AUX wakeup:

0: AUX wake-up is immediately following triggering event
1: AUX wake-up is forced to happen a fixed number of 32 KHz clocks following the triggering event.

The number of 32KHz clock cycles is configured in CTL0.FIXED_WU_PER register.
This bit is used to ensure that the AUX is always woken up an exact number of clocks following the triggering event by compensating for any variable delays caused by other activities going on at the time of wakeup (such as a recharge event etc.)
NB: Waking up AUX by AUXCTL.AUX_FORCE_ON and AUXCTL.SWEV is not affected by this bit

RW

0

15:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

0

RAM_RET_EN

This bit controls retention mode for the AUX_RAM:BANK0:

0: Retention is disabled
1: Retention is enabled

NB: If retention is disabled, the AUX_RAM will be powered off when it would otherwise be put in retention mode

RW

1



TOP:AON_WUC:AUXCTL

Address offset

0x0000 0010

Physical address

0x4009 1010

Instance

AON_WUC

Description

AUX Control

This register contains events and control signals for the AUX domain.

Type

RW

Bits

Field Name

Description

Type

Reset

31

RESET_REQ

Reset request for AUX. Writing 1 to this register will assert reset to AUX. The reset will be held until the bit is cleared again.

0: AUX reset pin will be deasserted
1: AUX reset pin will be asserted

RW

0

30:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

2

SCE_RUN_EN

Enables (1) or disables (0) AUX_SCE execution. AUX_SCE execution will begin when AUX Domain is powered and either this or AUX_SCE:CTL.CLK_EN is set.

Setting this bit will assure that AUX_SCE execution starts as soon as AUX power domain is woken up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX power domain has been off)

0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0
1: AUX_SCE execution is enabled.

RW

0

1

SWEV

Writing 1 sets the software event to the AUX domain, which can be read through AUX_WUC:WUEVFLAGS.AON_SW.

This event is normally cleared by AUX_SCE through the AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0 to this register.

Reading 0 means that there is no outstanding software event for AUX.

Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from AUX.

RW

0

0

AUX_FORCE_ON

Forces the AUX domain into active mode, overriding the requests from AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL.
Note that an ongoing AUX_WUC:PWROFFREQ will complete before this bit will set the AUX domain into active mode.

MCU must set this bit in order to access the AUX peripherals.
The AUX domain status can be read from PWRSTAT.AUX_PD_ON

0: AUX is allowed to Power Off, Power Down or Disconnect.
1: AUX Power OFF, Power Down or Disconnect requests will be overruled

RW

0



TOP:AON_WUC:PWRSTAT

Address offset

0x0000 0014

Physical address

0x4009 1014

Instance

AON_WUC

Description

Power Status Register

This register is used to monitor various power management related signals in AON. Most signals are for test, calibration and debug purpose only, and others can be used to detect that AUX or JTAG domains are powered up.

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

SW

General purpose Read/Write register that can be read through the test subsystem tap. This register is dedicated for the Power Profiler tool.

RW

0x0

29:26

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

25

VDDS_OK

Observation of VDDS_BOD_OK signal from VDDS brown out detection circuit

0: VDDS_BOD_OK signal is low.
1: VDDS_BOD_OK signal is high indication that VDDS voltage is OK.

RO

1

24

VDDR_OK

Observation of VDDR_OK from VDDR brown out detection circuit

1: VDDR_OK signal is high indication that VDDR voltage is OK.
0: VDDR_OK signal is low.

RO

1

23

VDD_OK

Observation of VDD_BOD_OK signal from VDD brown out detection circuit

0: VDD_BOD_OK signal is low
1: VDD_BOD_OK signal is high indicating that VDD voltage is good

RO

1

22

OSC_GBIAS

Indicates OSC GBIAS state:

0: OSC is not requesting GBIAS
1: OSC is requesting GBIAS

RO

0

21

AUX_GBIAS

Indicates AUX GBIAS state:

0: AUX is not requesting GBIAS
1: AUX is requesting GBIAS

RO

0

20

MCU_GBIAS

Indicates MCU GBIAS state:

0: MCU is not requesting GBIAS
1: MCU is requesting GBIAS

RO

0

19

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

18

OSC_BGAP

Indicates OSC BGAP state:

0: OSC is not requesting BGAP
1: OSC is requesting BGAP

RO

0

17

AUX_BGAP

Indicates AUX BGAP state:

0: AUX is not requesting BGAP
1: AUX is requesting BGAP

RO

0

16

MCU_BGAP

Indicates MCU BGAP state:

0: MCU is not requesting BGAP
1: MCU is requesting BGAP

RO

0

15

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

14

GBIAS_ON99

Indicates GBIAS state:

0: GBIAS is powered off
1: GBIAS is powered on and steady within 99%

RO

0

13

GBIAS_ON

Indicates GBIAS state:

0: GBIAS is powered off
1: GBIAS is powered on and steady within 95%

RO

0

12

BGAP_ON

Indicates BGAP state:

0: BGAP is powered off
1: BGAP is powered on

RO

0

11:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

9

AUX_PWR_DWN

Indicates the AUX powerdown state when AUX domain is powered up.

0: Active mode
1: AUX Powerdown request has been granted

RO

0

8

MCU_PWR_DWN

Indicates the MCU powerdown state when MCU is powered up.

0: Active mode
1: MCU Powerdown request has been granted. ( MCU in STANDBY)

Note: MCU can only read 0 from this register due to the nature of the signal.

RO

0

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

6

JTAG_PD_ON

Indicates JTAG power state:

0: JTAG is powered off
1: JTAG is powered on

RO

0

5

AUX_PD_ON

Indicates AUX power state:

0: AUX is not ready for use ( may be powered off or in power state transition )
1: AUX is powered on, connected to bus and ready for use,

RO

0

4

MCU_PD_ON

Indicates MCU power state:

0: MCU Power sequencing is not yet finalized and MCU_AONIF registers may not be reliable
1: MCU Power sequencing is finalized and all MCU_AONIF registers are reliable

RO

0

3

AUX_BUS_RESET_DONE

Indicates Reset Done from AUX Bus:

0: AUX Bus is being reset
1: AUX Bus reset is released

RO

0

2

AUX_BUS_CONNECTED

Indicates that AUX Bus is connected:

0: AUX bus is not connected
1: AUX bus is connected ( idle_ack = 0 )

RO

0

1

AUX_RESET_DONE

Indicates Reset Done from AUX:

0: AUX is being reset
1: AUX reset is released

RO

0

0

PWR_DWN

Indicates state of power supply:

0: Active mode
1: System is running of uLDO

Note MCU can normally only read 0 from this register due to the nature of signal

RO

0



TOP:AON_WUC:SHUTDOWN

Address offset

0x0000 0018

Physical address

0x4009 1018

Instance

AON_WUC

Description

Shutdown Control

This register contains bitfields required for entering shutdown mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

JTAG_OVR

This register is ignored. Shutdown requests can be overridden directly from WUC_TAP

RW

0

0

EN

Writing a 1 to this bit forces a shutdown request to be registered and all I/O values to be latched - in the PAD ring, possibly enabling I/O wakeup. Writing 0 will cancel a registered shutdown request and open th I/O latches residing in the PAD ring.

A registered shutdown request takes effect the next time power down conditions exists. At this time, the will not enter Powerdown mode, but instead it will turn off all internal powersupplies, effectively putting the device into Shutdown mode.

RW

0



TOP:AON_WUC:CTL0

Address offset

0x0000 0020

Physical address

0x4009 1020

Instance

AON_WUC

Description

General Configuration

This register contains various chip level control and debug bitfields.

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8

PWR_DWN_DIS

Controls whether MCU and AUX requesting to be powered off will enable a transition to powerdown:

0: Enabled
1: Disabled

RW

0

7:4

FIXED_WU_PER

Select a wakeup period for AUX and MCU wakeup. Wakeup time will take at least the number of SCLK_LF cycles specified in this register, when enabed by MCUCFG.FIXED_WU_EN and/or AUXCFG.FIXED_WU_EN

RW

0x0

3

Reserved

Internal field controlled by TI provided startup code

WO

0

2

Reserved

WO

0

1

Reserved

RO

0

0

Reserved

RO

0



TOP:AON_WUC:CTL1

Address offset

0x0000 0024

Physical address

0x4009 1024

Instance

AON_WUC

Description

General Control Register

This register contains various chip level control and debug bitfields.

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:16

TAP_SECURITY_CTL

Readback of security ctrl word of WUC_TAP

Bit 0: t2c_wuc_sec_totalerase
Bit 1: t2c_wuc_sec_chiperase
Bit 2: t2c_wuc_sec_bddat
Bit 3: t2c_wuc_sec_bdrdy
Bit 4: t2c_wuc_sec_aux_reset_req
Bit 5: t2c_wuc_sec_mcu_reset_req
Bit 6: t2c_wuc_sec_shutdown_waitforjtagdisconnect
Bit 7: t2c_wuc_sec_sys_reset_req ( note: always reads 0 )

RO

0x00

15:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

9

Reserved

RW

0

8

CHIP_ERASE

Request set by WUC_TAP to request ROM FW to perform a Chip erase

Read 0: No Chip Erase request is registered
Read 1: A Chip Erase has been requested via WUC_TAP.
Write 0: No effect.
Write 1: Will clear a registered Chip Erase request. The WUC_TAP CHIP_ERASE request must be cleared and set again before a new requst is registered.

A Chip Erase will be effectuated by the ROM FW if this bit is set when MCU is booting. User must therefore issue a MCU reset request ( via WUC_TAP) before the Chip Erase takes effect

RW

0

7:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

1

MCU_RESET_SRC

Indicates source of last MCU Voltage Domain warm reset request:

0: MCU SW reset
1: JTAG reset

This bit can only be cleared by writing a 1 to it

RW

0

0

MCU_WARM_RESET

Indicates type of last MCU Voltage Domain reset:

0: Last MCU reset was not a warm reset
1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated in MCU_RESET_SRC)

This bit can only be cleared by writing a 1 to it

RW

0



TOP:AON_WUC:RECHARGECFG

Address offset

0x0000 0030

Physical address

0x4009 1030

Instance

AON_WUC

Description

Recharge Controller Configuration

This register sets all relevant patameters for controlling the recharge algorithm.

Type

RW

Bits

Field Name

Description

Type

Reset

31

ADAPTIVE_EN

Enable adaptive recharge

Note: Recharge can be turned completely of by setting MAX_PER_E=7 and MAX_PER_M=31 and this bitfield to 0

RW

0

30:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:20

C2

Gain factor for adaptive recharge algorithm

period_new=period * ( 1+/-(2^-C1+2^-C2) )
Valid values for C2 is 2 to 10

Note: Rounding may cause adaptive recharge not to start for very small values of both Gain and Initial period. Criteria for algorithm to start is MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1

RW

0x0

19:16

C1

Gain factor for adaptive recharge algorithm

period_new=period * ( 1+/-(2^-C1+2^-C2) )
Valid values for C1 is 1 to 10

Note: Rounding may cause adaptive recharge not to start for very small values of both Gain and Initial period. Criteria for algorithm to start is MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1

RW

0x0

15:11

MAX_PER_M

This register defines the maximum period that the recharge algorithm can take, i.e. it defines the maximum number of cycles between 2 recharges.
The maximum number of cycles is specified with a 5 bit mantissa and 3 bit exponent:
MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E
This field sets the mantissa of MAXCYCLES

RW

0x00

10:8

MAX_PER_E

This register defines the maximum period that the recharge algorithm can take, i.e. it defines the maximum number of cycles between 2 recharges.
The maximum number of cycles is specified with a 5 bit mantissa and 3 bit exponent:
MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E
This field sets the exponent MAXCYCLES

RW

0x0

7:3

PER_M

Number of 32 KHz clocks between activation of recharge controller
For recharge algorithm, PERIOD is the initial period when entering powerdown mode. The adaptive recharge algorithm will not change this register
PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent:
This field sets the Mantissa of the Period.
PERIOD=(PER_M*16+15)*2^PER_E

RW

0x00

2:0

PER_E

Number of 32 KHz clocks between activation of recharge controller
For recharge algorithm, PERIOD is the initial period when entering powerdown mode. The adaptive recharge algorithm will not change this register
PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent:
This field sets the Exponent of the Period.
PERIOD=(PER_M*16+15)*2^PER_E

RW

0x0



TOP:AON_WUC:RECHARGESTAT

Address offset

0x0000 0034

Physical address

0x4009 1034

Instance

AON_WUC

Description

Recharge Controller Status

This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug.

Type

RW

Bits

Field Name

Description

Type

Reset

31:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

19:16

VDDR_SMPLS

The last 4 VDDR samples, bit 0 being the newest.

The register is being updated in every recharge period with a shift left, and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be shifted in.

RO

0x0

15:0

MAX_USED_PER

The maximum value of recharge period seen with VDDR>threshold.

The VDDR voltage is compared against the threshold voltage at just before each recharge. If VDDR is above threshold, MAX_USED_PER is updated with max ( current recharge peride; MAX_USED_PER ) This way MAX_USED_PER can track the recharge period where VDDR is decharged to the threshold value. We can therefore use the value as an indication of the leakage current during recharge.

This bitfield is cleared to 0 when writing this register.

RW

0x0000



TOP:AON_WUC:OSCCFG

Address offset

0x0000 0038

Physical address

0x4009 1038

Instance

AON_WUC

Description

Oscillator Configuration

This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode.

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:3

PER_M

Number of 32 KHz clocks between oscillator amplitude calibrations.
When this counter expires, an oscillator amplitude compensation is triggered immediately in Active mode. When this counter expires in Powerdown mode an internal flag is set such that the amplitude compensation is postponed until the next recharge occurs.

The Period will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent
PERIOD=(PER_M*16+15)*2^PER_E
This field sets the mantissa
Note: Oscillator amplitude calibration is turned of when both this bitfield and PER_E are set to 0

RW

0x00

2:0

PER_E

Number of 32 KHz clocks between oscillator amplitude calibrations.
When this counter expires, an oscillator amplitude compensation is triggered immediately in Active mode. When this counter expires in Powerdown mode an internal flag is set such that the amplitude compensation is postponed until the next recharge occurs.
The Period will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent
PERIOD=(PER_M*16+15)*2^PER_E
This field sets the exponent
Note: Oscillator amplitude calibration is turned of when both PER_M and this bitfield are set to 0

RW

0x0



TOP:AON_WUC:JTAGCFG

Address offset

0x0000 0040

Physical address

0x4009 1040

Instance

AON_WUC

Description

JTAG Configuration

This register contains control for configuration of the JTAG domain,- hereunder access permissions for each TAP.

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8

JTAG_PD_FORCE_ON

Controls JTAG PowerDomain power state:

0: Controlled exclusively by debug subsystem. (JTAG Powerdomain will be powered off unless a debugger is attached)
1: JTAG Power Domain is forced on, independent of debug subsystem.

NB: The reset value causes JTAG Power Domain to be powered on by default. Software must clear this bit to turn off the JTAG Power Domain

RW

1

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

6

PBIST2_TAP

Internal field controlled by TI provided startup code

RW

0

5

PBIST1_TAP

Internal field controlled by TI provided startup code

RW

0

4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

3

TEST_TAP

Internal field controlled by TI provided startup code

RW

0

2

WUC_TAP

Internal field controlled by TI provided startup code

RW

0

1

PRCM_TAP

Internal field controlled by TI provided startup code

RW

0

0

CPU_DAP

Internal field controlled by TI provided startup code

RW

0



TOP:AON_WUC:JTAGUSERCODE

Address offset

0x0000 0044

Physical address

0x4009 1044

Instance

AON_WUC

Description

JTAG USERCODE

Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem.

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

USER_CODE

Internal field controlled by TI provided startup code

RW

0x0B99 A02F