AON_SYSCTL

Instance: AON_SYSCTL
Component: AON_SYSCTL
Base address: 0x40090000

 

This component controls AON_SYSCTL, which is the device's system controller.

Note: This module is only supporting 32 bit ReadWrite access from MCU

 

TOP:AON_SYSCTL Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

PWRCTL

RW

32

0x0000 0000

0x0000 0000

0x4009 0000

RESETCTL

RW

32

0x0000 00E0

0x0000 0004

0x4009 0004

SLEEPCTL

RW

32

0x0000 0000

0x0000 0008

0x4009 0008

TOP:AON_SYSCTL Register Descriptions

TOP:AON_SYSCTL:PWRCTL

Address offset

0x0000 0000

Physical address

0x4009 0000

Instance

AON_SYSCTL

Description

Power Management

This register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled.

Type

RW

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

11

VDDS3_IOSEG_EN_SET

VDDS3 I/O segment enable

0: No effect
1: Enable VDDS3 I/O Segment

WO

0

10

VDDS2_IOSEG_EN_SET

VDDS2 I/O segment enable

0: No effect
1: Enable VDDS2 I/O Segment

WO

0

9

VDDS3_IOSEG_EN_CLR

VDDS3 I/O segment disable

0: No effect
1: Disable VDDS3 I/O Segment

WO

0

8

VDDS2_IOSEG_EN_CLR

VDDS2 I/O segment disable

0: No effect
1: Disable VDDS2 I/O Segment

WO

0

7:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

2

DCDC_ACTIVE

Select to use DCDC regulator for VDDR in active mode

0: Use GLDO for regulation of VDDRin active mode.
1: Use DCDC for regulation of VDDRin active mode.

RW

0

1

EXT_REG_MODE

Status of source for VDDRsupply:

0: DCDC/GLDO are generating VDDR
1: DCDC/GLDO are bypassed, external regulator supplies VDDR

RO

0

0

DCDC_EN

Select to use DCDC regulator during recharge of VDDR

0: Use GLDO for recharge of VDDR
1: Use DCDC for recharge of VDDR

Note: This bitfield should be set to the same as DCDC_ACTIVE

RW

0



TOP:AON_SYSCTL:RESETCTL

Address offset

0x0000 0004

Physical address

0x4009 0004

Instance

AON_SYSCTL

Description

Reset Management

This register contains bitfields releated to system reset such as reset source and reset request and control of brown out resets.

Type

RW

Bits

Field Name

Description

Type

Reset

31

SYSRESET

Cold reset register. Writing 1 to this bitfield will reset the entire chip and cause boot code to run again.

0: No effect
1: Generate system reset. Appears as SYSRESET in RESET_SRC.

WO

0

30:26

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

25

BOOT_DET_1_CLR

Clear of debug flag 1 BOOT_DET_1 . Takes immediate effect as signal is not synchronized to SCLK_LF Clock

0 : No effect
1 : Clear BOOT_DET_1

Note: BOOT_DET_1 will get undefined if BOOT_DET_1_SET is set together with this bitfield.

RW

0

24

BOOT_DET_0_CLR

Clear of debug flag 0 BOOT_DET_0. Takes immediate effect as signal is not synchronized to SCLK_LF Clock

0 : No effect
1 : Clear BOOT_DET_0

Note: BOOT_DET_0 will get undefined if BOOT_DET_0_SET is set together with this bitfield.

RW

0

23:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

17

BOOT_DET_1_SET

Set of debug flag 1 BOOT_DET_1 . Takes immediate effect as signal is not synchronized to SCLK_LF Clock

0 : No effect
1 : Set BOOT_DET_1.

Note: BOOT_DET_1 will get undefined if BOOT_DET_1_CLR is set together with this bitfield.

RW

0

16

BOOT_DET_0_SET

Set of debug flag 0 BOOT_DET_0. Takes immediate effect as signal is not synchronized to SCLK_LF Clock

0 : No effect
1 : Set BOOT_DET_0.

Note: BOOT_DET_0 will get undefined if BOOT_DET_0_CLR is set together with this bitfield.

RW

0

15

WU_FROM_SD

A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin being forced low)

Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup sources.

0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC
1: A wakeup has occurred from SHUTDOWN

Note: This flag can not be cleared and will therefor remain valid untill poweroff/reset

RO

0

14

GPIO_WU_FROM_SD

A wakeup from SHUTDOWN on an IO event has occurred

Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup sources.

0: The wakeup did not occur from SHUTDOWN on an IO event
1: A wakeup from SHUTDOWN occurred from an IO event

The case where WU_FROM_SD is asserted but this bitfield is not asserted will only occur in a debug session. The boot code will not proceed with wakeup from SHUTDOWN procedure until this bitfield is asserted as well.

Note: This flag can not be cleared and will therefor remain valid untill poweroff/reset

RO

0

13

BOOT_DET_1

Boot Debug flag which has retention throughout a system reset. This flag may be used by software to trace an undesired system reset.
This bitfield returns boot debug flag #1, which physically is located in the VDDS domain. The flag is modified by the bitfields BOOT_DET_1_SET and BOOT_DET_1_CLR

RO

0

12

BOOT_DET_0

Boot Debug flag which has retention throughout a system reset. This flag may be used by software to trace an undesired system reset.
This bitfield returns boot debug flag #0, which physically is located in the VDDS domain. The flag is modified by the bitfields BOOT_DET_0_SET and BOOT_DET_0_CLR

RO

0

11

VDDS_LOSS_EN_OVR

Internal field controlled by TI provided startup code

RW

0

10

VDDR_LOSS_EN_OVR

Internal field controlled by TI provided startup code

RW

0

9

VDD_LOSS_EN_OVR

Internal field controlled by TI provided startup code

RW

0

8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

7

VDDS_LOSS_EN

Controls reset generation in case VDDS is lost

0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1
1: Brown out detect of VDDS generates system reset

RW

1

6

VDDR_LOSS_EN

Controls reset generation in case VDDR is lost

0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1
1: Brown out detect of VDDR generates system reset

RW

1

5

VDD_LOSS_EN

Controls reset generation in case VDD is lost

0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1
1: Brown out detect of VDD generates system reset

RW

1

4

CLK_LOSS_EN

Controls reset generation in case SCLK_LF is lost. (provided that clock loss detection is enabled by DDI_0_OSC:CTL0.CLK_LOSS_EN)

Note: Clock loss reset generation must be disabled before SCLK_LF clock source is changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain disabled untill the change is confirmed in DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do so may result in a spurious system reset. Clock loss reset generation can be disabled through this bitfield or by clearing DDI_0_OSC:CTL0.CLK_LOSS_EN

0: Clock loss is ignored
1: Clock loss generates system reset

RW

0

3:1

RESET_SRC

Shows the source of the last system reset:

Value

ENUM name

Description

0x0

PWR_ON

Power on reset

0x1

PIN_RESET

Reset pin

0x2

VDDS_LOSS

Brown out detect on VDDS

0x3

VDD_LOSS

Brown out detect on VDD

0x4

VDDR_LOSS

Brown out detect on VDDR

0x5

CLK_LOSS

Clock loss detect

0x6

SYSRESET

Software reset via SYSRESET register

0x7

WARMRESET

Software reset via PRCM warm reset request

RO

0x0

0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0



TOP:AON_SYSCTL:SLEEPCTL

Address offset

0x0000 0008

Physical address

0x4009 0008

Instance

AON_SYSCTL

Description

Sleep Mode Register

This register is used to unfreeze the IO pad ring after waking up from SHUTDOWN

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

IO_PAD_SLEEP_DIS

Controls the I/O pad sleep mode. The boot code will set this bitfield automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set ).

0: I/O pad sleep mode is enabled, ie all pads are latched and can not toggle.
1: I/O pad sleep mode is disabled

Application software may want to reconfigure the state for all IO's before setting this bitfield upon waking up from a SHUTDOWN.

RW

0