CPU_ROM_TABLE

Instance: CPU_ROM_TABLE
Component: CPU_ROM_TABLE
Base address: 0xe00ff000

 

Cortex-M's ROM table

 

TOP:CPU_ROM_TABLE Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SCS

RO

32

0xFFF0 F003

0x0000 0000

0xE00F F000

DWT

RO

32

0xFFF0 2003

0x0000 0004

0xE00F F004

FPB

RO

32

0xFFF0 3003

0x0000 0008

0xE00F F008

ITM

RO

32

0xFFF0 1003

0x0000 000C

0xE00F F00C

TPIU

RO

32

0xFFF4 1003

0x0000 0010

0xE00F F010

ETM

RO

32

0xFFF4 2002

0x0000 0014

0xE00F F014

END

RO

32

0x0000 0000

0x0000 0018

0xE00F F018

SYSTEM_ACCESS

RO

32

0x0000 0001

0x0000 0FCC

0xE00F FFCC

TOP:CPU_ROM_TABLE Register Descriptions

TOP:CPU_ROM_TABLE:SCS

Address offset

0x0000 0000

Physical address

0xE00F F000

Instance

CPU_ROM_TABLE

Description

System Control Space Component

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

SCS

Points to the SCS at 0xE000E000.
(SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000.

RO

0xFFF0 F003



TOP:CPU_ROM_TABLE:DWT

Address offset

0x0000 0004

Physical address

0xE00F F004

Instance

CPU_ROM_TABLE

Description

Data Watchpoint and Trace Component
Points to the Data Watchpoint and Trace block at 0xE0001000. Value has bit [0] set if DWT is present.

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

DWT

Points to the Data Watchpoint and Trace block at 0xE0001000.
(2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000.

RO

0x7FF8 1001

0

DWT_PRESENT

0: DWT is not present
1: DWT is present.

RO

1



TOP:CPU_ROM_TABLE:FPB

Address offset

0x0000 0008

Physical address

0xE00F F008

Instance

CPU_ROM_TABLE

Description

Flash Patch and Breakpoint Component
Points to the Flash Patch and Breakpoint block at 0xE0002000. Value has bit [0] set to 1 if FPB is present.

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

FPB

Points to the Flash Patch and Breakpoint block at 0xE0002000.
(2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000.

RO

0x7FF8 1801

0

FPB_PRESENT

0: FPB is not present
1: FPB is present.

RO

1



TOP:CPU_ROM_TABLE:ITM

Address offset

0x0000 000C

Physical address

0xE00F F00C

Instance

CPU_ROM_TABLE

Description

Instrumentation Trace Component
Points to the Instrumentation Trace block at 0xE0000000. Value has bit [0] set if ITM is present.

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

ITM

Points to the Instrumentation Trace block at 0xE0000000.
(2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000.

RO

0x7FF8 0801

0

ITM_PRESENT

0: ITM is not present
1: ITM is present.

RO

1



TOP:CPU_ROM_TABLE:TPIU

Address offset

0x0000 0010

Physical address

0xE00F F010

Instance

CPU_ROM_TABLE

Description

Trace Port Interface Component
Points to the TPIU. Value has bit [0] set to 1 if TPIU is present. TPIU is at 0xE0040000.

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

TPIU

Points to the TPIU. TPIU is at 0xE0040000.
(2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000.

RO

0x7FFA 0801

0

TPIU_PRESENT

0: TPIU is not present
1: TPIU is present.

RO

1



TOP:CPU_ROM_TABLE:ETM

Address offset

0x0000 0014

Physical address

0xE00F F014

Instance

CPU_ROM_TABLE

Description

Enhanced Trace Component
Points to the ETM. Value has bit [0] set to 1 if ETM is present. ETM is at 0xE0041000.

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

ETM

Points to the ETM. ETM is at 0xE0041000.
(2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000.

RO

0x7FFA 1001

0

ETM_PRESENT

0: ETM is not present
1: ETM is present.

RO

0



TOP:CPU_ROM_TABLE:END

Address offset

0x0000 0018

Physical address

0xE00F F018

Instance

CPU_ROM_TABLE

Description

End Marker
Marks the end of the ROM table. If CoreSight components are added, they are added starting from this location and the End marker is moved to the next location after the additional components.

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

END

End of the ROM table

RO

0x0000 0000



TOP:CPU_ROM_TABLE:SYSTEM_ACCESS

Address offset

0x0000 0FCC

Physical address

0xE00F FFCC

Instance

CPU_ROM_TABLE

Description

System Memory Map Access for DAP

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

RESERVED1

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RO

0x0000 0000

0

SYSTEM_ACCESS

1: The system memory map is accessible using the DAP
0: Only debug resources are accessible using the DAP

RO

1