TRNG

Instance: TRNG
Component: TRNG
Base address: 0x40028000

 

True Random Number Generator

 

TOP:TRNG Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

OUT0

RO

32

0x0000 0000

0x0000 0000

0x4002 8000

OUT1

RO

32

0x0000 0000

0x0000 0004

0x4002 8004

IRQFLAGSTAT

RO

32

0x0000 0000

0x0000 0008

0x4002 8008

IRQFLAGMASK

RW

32

0x0000 0000

0x0000 000C

0x4002 800C

IRQFLAGCLR

WO

32

0x0000 0000

0x0000 0010

0x4002 8010

CTL

RW

32

0x0000 0000

0x0000 0014

0x4002 8014

CFG0

RW

32

0x0000 0000

0x0000 0018

0x4002 8018

ALARMCNT

RW

32

0x0000 00FF

0x0000 001C

0x4002 801C

FROEN

RW

32

0x00FF FFFF

0x0000 0020

0x4002 8020

FRODETUNE

RW

32

0x0000 0000

0x0000 0024

0x4002 8024

ALARMMASK

RW

32

0x0000 0000

0x0000 0028

0x4002 8028

ALARMSTOP

RW

32

0x0000 0000

0x0000 002C

0x4002 802C

LFSR0

RW

32

0x0000 0000

0x0000 0030

0x4002 8030

LFSR1

RW

32

0x0000 0000

0x0000 0034

0x4002 8034

LFSR2

RW

32

0x0000 0000

0x0000 0038

0x4002 8038

HWOPT

RO

32

0x0000 0600

0x0000 0078

0x4002 8078

HWVER0

RO

32

0x0200 B44B

0x0000 007C

0x4002 807C

IRQSTATMASK

RO

32

0x0000 0000

0x0000 1FD8

0x4002 9FD8

HWVER1

RO

32

0x0000 0020

0x0000 1FE0

0x4002 9FE0

IRQSET

RW

32

0x0000 0000

0x0000 1FEC

0x4002 9FEC

SWRESET

RW

32

0x0000 0000

0x0000 1FF0

0x4002 9FF0

IRQSTAT

RO

32

0x0000 0000

0x0000 1FF8

0x4002 9FF8

TOP:TRNG Register Descriptions

TOP:TRNG:OUT0

Address offset

0x0000 0000

Physical address

0x4002 8000

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

VALUE_31_0

Internal

RO

0x0000 0000



TOP:TRNG:OUT1

Address offset

0x0000 0004

Physical address

0x4002 8004

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

VALUE_63_32

Internal

RO

0x0000 0000



TOP:TRNG:IRQFLAGSTAT

Address offset

0x0000 0008

Physical address

0x4002 8008

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31

NEED_CLOCK

Internal

RO

0

30:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

SHUTDOWN_OVF

Internal

RO

0

0

RDY

Internal

RO

0



TOP:TRNG:IRQFLAGMASK

Address offset

0x0000 000C

Physical address

0x4002 800C

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

SHUTDOWN_OVF

Internal

RW

0

0

RDY

Internal

RW

0



TOP:TRNG:IRQFLAGCLR

Address offset

0x0000 0010

Physical address

0x4002 8010

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

WO

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0x0000 0000

1

SHUTDOWN_OVF

Internal

WO

0

0

RDY

Internal

WO

0



TOP:TRNG:CTL

Address offset

0x0000 0014

Physical address

0x4002 8014

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

STARTUP_CYCLES

Internal

RW

0x0000

15:11

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

10

TRNG_EN

Internal

RW

0

9:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

2

NO_LFSR_FB

Internal

RW

0

1

TEST_MODE

Internal

RW

0

0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0



TOP:TRNG:CFG0

Address offset

0x0000 0018

Physical address

0x4002 8018

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

MAX_REFILL_CYCLES

Internal

RW

0x0000

15:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

11:8

SMPL_DIV

Internal

RW

0x0

7:0

MIN_REFILL_CYCLES

Internal

RW

0x00



TOP:TRNG:ALARMCNT

Address offset

0x0000 001C

Physical address

0x4002 801C

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

29:24

SHUTDOWN_CNT

Internal

RW

0x00

23:21

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

20:16

SHUTDOWN_THR

Internal

RW

0x00

15:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

7:0

ALARM_THR

Internal

RW

0xFF



TOP:TRNG:FROEN

Address offset

0x0000 0020

Physical address

0x4002 8020

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:0

FRO_MASK

Internal

RW

0xFF FFFF



TOP:TRNG:FRODETUNE

Address offset

0x0000 0024

Physical address

0x4002 8024

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:0

FRO_MASK

Internal

RW

0x00 0000



TOP:TRNG:ALARMMASK

Address offset

0x0000 0028

Physical address

0x4002 8028

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x00

23:0

FRO_MASK

Internal

RW

0x00 0000



TOP:TRNG:ALARMSTOP

Address offset

0x0000 002C

Physical address

0x4002 802C

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:0

FRO_FLAGS

Internal

RW

0x00 0000



TOP:TRNG:LFSR0

Address offset

0x0000 0030

Physical address

0x4002 8030

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR_31_0

Internal

RW

0x0000 0000



TOP:TRNG:LFSR1

Address offset

0x0000 0034

Physical address

0x4002 8034

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR_63_32

Internal

RW

0x0000 0000



TOP:TRNG:LFSR2

Address offset

0x0000 0038

Physical address

0x4002 8038

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0000

16:0

LFSR_80_64

Internal

RW

0x0 0000



TOP:TRNG:HWOPT

Address offset

0x0000 0078

Physical address

0x4002 8078

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

11:6

NR_OF_FROS

Internal

RO

0x18

5:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00



TOP:TRNG:HWVER0

Address offset

0x0000 007C

Physical address

0x4002 807C

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

27:24

HW_MAJOR_VER

Internal

RO

0x2

23:20

HW_MINOR_VER

Internal

RO

0x0

19:16

HW_PATCH_LVL

Internal

RO

0x0

15:8

EIP_NUM_COMPL

Internal

RO

0xB4

7:0

EIP_NUM

Internal

RO

0x4B



TOP:TRNG:IRQSTATMASK

Address offset

0x0000 1FD8

Physical address

0x4002 9FD8

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

SHUTDOWN_OVF

Internal

RO

0

0

RDY

Internal

RO

0



TOP:TRNG:HWVER1

Address offset

0x0000 1FE0

Physical address

0x4002 9FE0

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

REV

Internal

RO

0x20



TOP:TRNG:IRQSET

Address offset

0x0000 1FEC

Physical address

0x4002 9FEC

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0000 0000

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0

0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0



TOP:TRNG:SWRESET

Address offset

0x0000 1FF0

Physical address

0x4002 9FF0

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

RESET

Internal

RW

0



TOP:TRNG:IRQSTAT

Address offset

0x0000 1FF8

Physical address

0x4002 9FF8

Instance

TRNG

Description

Internal Register. Customers can control this through TI provided API

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

STAT

Internal

RO

0