GPT0

Instance: GPT0
Component: GPT
Base address: 0x40010000

 

General Purpose Timer.

 

TOP:GPT0 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CFG

RW

32

0x0000 0000

0x0000 0000

0x4001 0000

TAMR

RW

32

0x0000 0000

0x0000 0004

0x4001 0004

TBMR

RW

32

0x0000 0000

0x0000 0008

0x4001 0008

CTL

RW

32

0x0000 0000

0x0000 000C

0x4001 000C

SYNC

RW

32

0x0000 0000

0x0000 0010

0x4001 0010

IMR

RW

32

0x0000 0000

0x0000 0018

0x4001 0018

RIS

RO

32

0x0000 0000

0x0000 001C

0x4001 001C

MIS

RO

32

0x0000 0000

0x0000 0020

0x4001 0020

ICLR

RW

32

0x0000 0000

0x0000 0024

0x4001 0024

TAILR

RW

32

0xFFFF FFFF

0x0000 0028

0x4001 0028

TBILR

RW

32

0x0000 FFFF

0x0000 002C

0x4001 002C

TAMATCHR

RW

32

0xFFFF FFFF

0x0000 0030

0x4001 0030

TBMATCHR

RW

32

0x0000 FFFF

0x0000 0034

0x4001 0034

TAPR

RW

32

0x0000 0000

0x0000 0038

0x4001 0038

TBPR

RW

32

0x0000 0000

0x0000 003C

0x4001 003C

TAPMR

RW

32

0x0000 0000

0x0000 0040

0x4001 0040

TBPMR

RW

32

0x0000 0000

0x0000 0044

0x4001 0044

TAR

RO

32

0xFFFF FFFF

0x0000 0048

0x4001 0048

TBR

RO

32

0x0000 FFFF

0x0000 004C

0x4001 004C

TAV

RW

32

0xFFFF FFFF

0x0000 0050

0x4001 0050

TBV

RW

32

0x0000 FFFF

0x0000 0054

0x4001 0054

RTCPD

RO

32

0x0000 7FFF

0x0000 0058

0x4001 0058

TAPS

RO

32

0x0000 0000

0x0000 005C

0x4001 005C

TBPS

RO

32

0x0000 0000

0x0000 0060

0x4001 0060

TAPV

RO

32

0x0000 0000

0x0000 0064

0x4001 0064

TBPV

RO

32

0x0000 0000

0x0000 0068

0x4001 0068

DMAEV

RW

32

0x0000 0000

0x0000 006C

0x4001 006C

ADCEV

RW

32

0x0000 0000

0x0000 0070

0x4001 0070

VERSION

RO

32

0x0000 0400

0x0000 0FB0

0x4001 0FB0

ANDCCP

RW

32

0x0000 0000

0x0000 0FB4

0x4001 0FB4

TOP:GPT0 Register Descriptions

TOP:GPT:CFG

Address offset

0x0000 0000

Physical address

0x4001 0000

Instance

GPT0

Description

GPT Configuration

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

CFG

GPT Configuration
0x2- 0x3 - Reserved
0x5- 0x7 - Reserved

Value

ENUM name

Description

0x0

32BIT_TIMER

32-bit timer configuration

0x1

REALTIME_CLOCK

32-bit real-time clock

0x4

16BIT_TIMER

16-bit timer configuration.
Configure for two 16-bit timers.
Also see TAMR.TAMR and TBMR.TBMR.

RW

0x0



TOP:GPT:TAMR

Address offset

0x0000 0004

Physical address

0x4001 0004

Instance

GPT0

Description

GPT Timer A Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:13

TCACT

Timer Compare Action Select

Value

ENUM name

Description

0x0

DIS_CMP

Disable compare operations

0x1

TOG_ON_TO

Toggle State on Time-Out

0x2

CLR_ON_TO

Clear CCP output pin on Time-Out

0x3

SET_ON_TO

Set CCP output pin on Time-Out

0x4

SETTOG_ON_TO

Set CCP output pin immediately and toggle on Time-Out

0x5

CLRTOG_ON_TO

Clear CCP output pin immediately and toggle on Time-Out

0x6

SETCLR_ON_TO

Set CCP output pin immediately and clear on Time-Out

0x7

CLRSET_ON_TO

Clear CCP output pin immediately and set on Time-Out

RW

0x0

12

TACINTD

One-Shot/Periodic Interrupt Disable

Value

ENUM name

Description

0

EN_TO_INTR

Time-out interrupt function as normal

1

DIS_TO_INTR

Time-out interrupt are disabled

RW

0

11

TAPLO

Legacy PWM operation

Value

ENUM name

Description

0

LEGACY

Legacy operation

1

CCP_ON_TO

CCP output pin is set to 1 on time-out

RW

0

10

TAMRSU

Timer A Match Register Update mode

If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL is set), TAMATCHR and TAPR are updated according to the configuration of this bit.

Value

ENUM name

Description

0

CYCLEUPDATE

Update TAMATCHR and TAPR, if used, on the next cycle.

1

TOUPDATE

Update TAMATCHR and TAPR, if used, on the next time-out.

RW

0

9

TAPWMIE

GPT Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output.

Value

ENUM name

Description

0

DIS

Interrupt is disabled.

1

EN

Interrupt is enabled. This bit is only valid in PWM mode.

RW

0

8

TAILD

GPT Timer A PWM Interval Load Write

Value

ENUM name

Description

0

CYCLEUPDATE

Update the TAR register with the value in the TAILR register on the next clock cycle. If the pre-scaler is used, update the TAPS register with the value in the TAPR register on the next clock cycle.

1

TOUPDATE

Update the TAR register with the value in the TAILR register on the next timeout. If the prescaler is used, update the TAPS register with the value in the TAPR register on the next timeout.

RW

0

7

TASNAPS

GPT Timer A Snap-Shot Mode

Value

ENUM name

Description

0

DIS

Snap-shot mode is disabled.

1

EN

If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPT Timer A (TAR) register.

RW

0

6

TAWOT

GPT Timer A Wait-On-Trigger

Value

ENUM name

Description

0

NOWAIT

Timer A begins counting as soon as it is enabled.

1

WAIT

If Timer A is enabled (CTL.TAEN = 1), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This bit must be clear for GPT Module 0, Timer A

RW

0

5

TAMIE

GPT Timer A Match Interrupt Enable

Value

ENUM name

Description

0

DIS

The match interrupt is disabled.

1

EN

An interrupt is generated when the match value in TAMATCHR is reached in the one-shot and periodic modes.

RW

0

4

TACDIR

GPT Timer A Count Direction

Value

ENUM name

Description

0

DOWN

The timer counts down.

1

UP

The timer counts up. When counting up, the timer starts from a value of 0x0.

RW

0

3

TAAMS

GPT Timer A Alternate Mode

Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2.

Value

ENUM name

Description

0

CAP_COMP

Capture/Compare mode is enabled.

1

PWM

PWM mode is enabled

RW

0

2

TACM

GPT Timer A Capture Mode

Value

ENUM name

Description

0

EDGCNT

Edge-Count mode

1

EDGTIME

Edge-Time mode

RW

0

1:0

TAMR

GPT Timer A Mode

The Timer mode is based on the timer configuration defined by CFG

Value

ENUM name

Description

0x1

ONE_SHOT

One-Shot Timer mode

0x2

PERIODIC

Periodic Timer mode

0x3

CAPTURE

Capture mode

RW

0x0



TOP:GPT:TBMR

Address offset

0x0000 0008

Physical address

0x4001 0008

Instance

GPT0

Description

GPT Timer B Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:13

TCACT

Timer Compare Action Select

Value

ENUM name

Description

0x0

DIS_CMP

Disable compare operations

0x1

TOG_ON_TO

Toggle State on Time-Out

0x2

CLR_ON_TO

Clear CCP output pin on Time-Out

0x3

SET_ON_TO

Set CCP output pin on Time-Out

0x4

SETTOG_ON_TO

Set CCP output pin immediately and toggle on Time-Out

0x5

CLRTOG_ON_TO

Clear CCP output pin immediately and toggle on Time-Out

0x6

SETCLR_ON_TO

Set CCP output pin immediately and clear on Time-Out

0x7

CLRSET_ON_TO

Clear CCP output pin immediately and set on Time-Out

RW

0x0

12

TBCINTD

One-Shot/Periodic Interrupt Mode

Value

ENUM name

Description

0

EN_TO_INTR

Normal Time-Out Interrupt

1

DIS_TO_INTR

Mask Time-Out Interrupt

RW

0

11

TBPLO

Legacy PWM operation

Value

ENUM name

Description

0

LEGACY

Legacy operation

1

CCP_ON_TO

CCP output pin is set to 1 on time-out

RW

0

10

TBMRSU

Timer B Match Register Update mode

If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled. If the timer is stalled (CTL.TBSTALL is set), TBMATCHR and TBPR are updated according to the configuration of this bit.

Value

ENUM name

Description

0

CYCLEUPDATE

Update TBMATCHR and TBPR, if used on the next cycle.

1

TOUPDATE

Update the TBMATCHR and the TBPR, if used on the next time-out.

RW

0

9

TBPWMIE

GPT Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output

Value

ENUM name

Description

0

DIS

Interrupt is disabled.

1

EN

Interrupt is enabled. This bit is only valid in PWM mode.

RW

0

8

TBILD

GPT Timer B PWM Interval Load Write

Value

ENUM name

Description

0

CYCLEUPDATE

Update the TBR register with the value in the TBILR register on the next clock cycle. If the pre-scaler is used, update the TBPS register with the value in the TBPR register on the next clock cycle.

1

TOUPDATE

Update the TBR register with the value in the TBILR register on the next timeout. If the prescaler is used, update the TBPS register with the value in the TBPR register on the next timeout.

RW

0

7

TBSNAPS

GPT Timer B Snap-Shot Mode

Value

ENUM name

Description

0

DIS

Snap-shot mode is disabled.

1

EN

If Timer B is configured in the periodic mode

RW

0

6

TBWOT

GPT Timer B Wait-On-Trigger

Value

ENUM name

Description

0

NOWAIT

Timer B begins counting as soon as it is enabled.

1

WAIT

If Timer B is enabled (CTL.TBEN is set), Timer B does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain.

RW

0

5

TBMIE

GPT Timer B Match Interrupt Enable.

Value

ENUM name

Description

0

DIS

The match interrupt is disabled.

1

EN

An interrupt is generated when the match value in the TBMATCHR register is reached in the one-shot and periodic modes.

RW

0

4

TBCDIR

GPT Timer B Count Direction

Value

ENUM name

Description

0

DOWN

The timer counts down.

1

UP

The timer counts up. When counting up, the timer starts from a value of 0x0.

RW

0

3

TBAMS

GPT Timer B Alternate Mode

Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2.

Value

ENUM name

Description

0

CAP_COMP

Capture/Compare mode is enabled.

1

PWM

PWM mode is enabled

RW

0

2

TBCM

GPT Timer B Capture Mode

Value

ENUM name

Description

0

EDGCNT

Edge-Count mode

1

EDGTIME

Edge-Time mode

RW

0

1:0

TBMR

GPT Timer B Mode

The Timer mode is based on the timer configuration defined by CFG.CFG

Value

ENUM name

Description

0x1

ONE_SHOT

One-Shot Timer mode

0x2

PERIODIC

Periodic Timer mode

0x3

CAPTURE

Capture mode

RW

0x0



TOP:GPT:CTL

Address offset

0x0000 000C

Physical address

0x4001 000C

Instance

GPT0

Description

GPT Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:15

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

14

TBPWML

GPT Timer B PWM Output Level

0: Output is unaffected.
1: Output is inverted.

Value

ENUM name

Description

0

NORMAL

Not inverted

1

INVERTED

Inverted

RW

0

13

TBOTE

GPT Timer B Output Trigger Enable

Value

ENUM name

Description

0

DIS

The output Timer B ADC trigger is disabled.

1

EN

The output Timer B ADC trigger is enabled.

RW

0

12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

11:10

TBEVENT

GPT Timer B Event Mode

Value

ENUM name

Description

0x0

POS

Positive edge

0x1

NEG

Negative edge

0x3

BOTH

Both edges

RW

0x0

9

TBSTALL

GPT Timer B Stall Enable

Value

ENUM name

Description

0

DIS

Timer B continues counting while the processor is halted by the debugger.

1

EN

Timer B freezes counting while the processor is halted by the debugger.

RW

0

8

TBEN

GPT Timer B Enable

Value

ENUM name

Description

0

DIS

Timer B is disabled.

1

EN

Timer B is enabled and begins counting or the capture logic is enabled based on CFG register.

RW

0

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

6

TAPWML

GPT Timer A PWM Output Level

Value

ENUM name

Description

0

NORMAL

Not inverted

1

INVERTED

Inverted

RW

0

5

TAOTE

GPT Timer A Output Trigger Enable

Value

ENUM name

Description

0

DIS

The output Timer A ADC trigger is disabled.

1

EN

The output Timer A ADC trigger is enabled.

RW

0

4

RTCEN

GPT RTC Enable

Value

ENUM name

Description

0

DIS

RTC counting is disabled.

1

EN

RTC counting is enabled.

RW

0

3:2

TAEVENT

GPT Timer A Event Mode

Value

ENUM name

Description

0x0

POS

Positive edge

0x1

NEG

Negative edge

0x3

BOTH

Both edges

RW

0x0

1

TASTALL

GPT Timer A Stall Enable

Value

ENUM name

Description

0

DIS

Timer A continues counting while the processor is halted by the debugger.

1

EN

Timer A freezes counting while the processor is halted by the debugger.

RW

0

0

TAEN

GPT Timer A Enable

Value

ENUM name

Description

0

DIS

Timer A is disabled.

1

EN

Timer A is enabled and begins counting or the capture logic is enabled based on the CFG register.

RW

0



TOP:GPT:SYNC

Address offset

0x0000 0010

Physical address

0x4001 0010

Instance

GPT0

Description

GPT Synch Register

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:6

SYNC3

Synchronize GPT Timer 3.

Value

ENUM name

Description

0x0

NOSYNC

No Sync. GPT3 is not affected.

0x1

TIMERA

A timeout event for Timer A of GPT3 is triggered

0x2

TIMERB

A timeout event for Timer B of GPT3 is triggered

0x3

BOTH

A timeout event for both Timer A and Timer B of GPT3 is triggered

WO

0x0

5:4

SYNC2

Synchronize GPT Timer 2.

Value

ENUM name

Description

0x0

NOSYNC

No Sync. GPT2 is not affected.

0x1

TIMERA

A timeout event for Timer A of GPT2 is triggered

0x2

TIMERB

A timeout event for Timer B of GPT2 is triggered

0x3

BOTH

A timeout event for both Timer A and Timer B of GPT2 is triggered

WO

0x0

3:2

SYNC1

Synchronize GPT Timer 1

Value

ENUM name

Description

0x0

NOSYNC

No Sync. GPT1 is not affected.

0x1

TIMERA

A timeout event for Timer A of GPT1 is triggered

0x2

TIMERB

A timeout event for Timer B of GPT1 is triggered

0x3

BOTH

A timeout event for both Timer A and Timer B of GPT1 is triggered

WO

0x0

1:0

SYNC0

Synchronize GPT Timer 0

Value

ENUM name

Description

0x0

NOSYNC

No Sync. GPT0 is not affected.

0x1

TIMERA

A timeout event for Timer A of GPT0 is triggered

0x2

TIMERB

A timeout event for Timer B of GPT0 is triggered

0x3

BOTH

A timeout event for both Timer A and Timer B of GPT0 is triggered

WO

0x0



TOP:GPT:IMR

Address offset

0x0000 0018

Physical address

0x4001 0018

Instance

GPT0

Description

GPT Interrupt Mask
This register is used to enable the interrupts.
Associated registers:
RIS, MIS, ICLR

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

16

WUMIS

Enabling this bit will make the RIS.WURIS interrupt propagate to MIS.WUMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

15:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

13

DMABIM

Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

11

TBMIM

Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

10

CBEIM

Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

9

CBMIM

Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

8

TBTOIM

Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

7:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

5

DMAAIM

Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

4

TAMIM

Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

3

RTCIM

Enabling this bit will make the RIS.RTCRIS interrupt propagate to MIS.RTCMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

2

CAEIM

Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

1

CAMIM

Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0

0

TATOIM

Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS

Value

ENUM name

Description

0

DIS

Disable Interrupt

1

EN

Enable Interrupt

RW

0



TOP:GPT:RIS

Address offset

0x0000 001C

Physical address

0x4001 001C

Instance

GPT0

Description

GPT Raw Interrupt Status
Associated registers:
IMR, MIS, ICLR

Type

RO

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

16

WURIS

GPT Write Update Error Raw Interrupt

0: No error.
1: Either Timer A or B was written twice in a Row or Timer A was written before the corresponding Timer B was written.

RO

0

15:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

13

DMABRIS

GPT Timer B DMA Done Raw Interrupt Status

0: Transfer has not completed
1: Transfer has completed

RO

0

12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

11

TBMRIS

GPT Timer B Match Raw Interrupt

0: The match value has not been reached
1: The match value is reached.

TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode.

RO

0

10

CBERIS

GPT Timer B Capture Mode Event Raw Interrupt

0: The event has not occured.
1: The event has occured.

This interrupt asserts when the subtimer is configured in Input Edge-Time mode

RO

0

9

CBMRIS

GPT Timer B Capture Mode Match Raw Interrupt

0: Match for Timer B has not occured
1: Match for Timer B has occurred.

This interrupt asserts when the values in the TBR and TBPR match values in the TBMATCHR and TBPMR, and when configured in Input Edge-Time mode (reg-ref instead!!)

RO

0

8

TBTORIS

GPT Timer B Time-out Raw Interrupt

0: Timer B has not timed out
1: Timer B has timed out.

This interrupt is asserted when a one-shot or periodic mode timer reaches it's count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction.

RO

0

7:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

5

DMAARIS

GPT Timer A DMA Done Raw Interrupt Status

0: Transfer has not completed
1: Transfer has completed

RO

0

4

TAMRIS

**GPT **Timer A Match Raw Interrupt

0: The match value has not been reached
1: The match value is reached.

TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode.

RO

0

3

RTCRIS

GPT RTC Raw Interrupt

0: The RTC event has not occured
1: The RTC event has occured

RO

0

2

CAERIS

GPT Timer A Capture Mode Event Raw Interrupt

0: The event has not occured.
1: The event has occured.

This interrupt asserts when the subtimer is configured in Input Edge-Time mode

RO

0

1

CAMRIS

GPT Timer A Capture Mode Match Raw Interrupt

0: Match for Timer A has not occured
1: Match for Timer A has occurred

This interrupt asserts when the values in the TAR and TAPR match values in the TAMATCHR and TAPMR, and when configured in Input Edge-Time mode (reg-ref instead!!)

RO

0

0

TATORIS

GPT Timer A Time-out Raw Interrupt

0: Timer A has not timed out
1: Timer A has timed out.

This interrupt is asserted when a one-shot or periodic mode timer reaches it's count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction.

RO

0



TOP:GPT:MIS

Address offset

0x0000 0020

Physical address

0x4001 0020

Instance

GPT0

Description

GPT Masked Interrupt Status
Values are result of bitwise AND operation between RIS and IMR
Assosciated clear register: ICLR

Type

RO

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

16

WUMIS

0: No interrupt or interrupt not enabled
1: RIS.WURIS = 1 && IMR.WUMIS = 1

RO

0

15:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

13

DMABMIS

0: No interrupt or interrupt not enabled
1: RIS.DMABRIS = 1 && IMR.DMABIM = 1

RO

0

12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

11

TBMMIS

0: No interrupt or interrupt not enabled
1: RIS.TBMRIS = 1 && IMR.TBMIM = 1

RO

0

10

CBEMIS

0: No interrupt or interrupt not enabled
1: RIS.CBERIS = 1 && IMR.CBEIM = 1

RO

0

9

CBMMIS

0: No interrupt or interrupt not enabled
1: RIS.CBMRIS = 1 && IMR.CBMIM = 1

RO

0

8

TBTOMIS

0: No interrupt or interrupt not enabled
1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1

RO

0

7:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

5

DMAAMIS

0: No interrupt or interrupt not enabled
1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1

RO

0

4

TAMMIS

0: No interrupt or interrupt not enabled
1: RIS.TAMRIS = 1 && IMR.TAMIM = 1

RO

0

3

RTCMIS

0: No interrupt or interrupt not enabled
1: RIS.RTCRIS = 1 && IMR.RTCIM = 1

RO

0

2

CAEMIS

0: No interrupt or interrupt not enabled
1: RIS.CAERIS = 1 && IMR.CAEIM = 1

RO

0

1

CAMMIS

0: No interrupt or interrupt not enabled
1: RIS.CAMRIS = 1 && IMR.CAMIM = 1

RO

0

0

TATOMIS

0: No interrupt or interrupt not enabled
1: RIS.TATORIS = 1 && IMR.TATOIM = 1

RO

0



TOP:GPT:ICLR

Address offset

0x0000 0024

Physical address

0x4001 0024

Instance

GPT0

Description

GPT Interrupt Clear
This register is used to clear status bits in the RIS and MIS registers

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

16

WUECINT

0: Do nothing.
1: Clear RIS.WURIS and MIS.WUMIS

RW

0

15:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

13

DMABINT

0: Do nothing.
1: Clear RIS.DMABRIS and MIS.DMABMIS

RW

0

12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

11

TBMCINT

0: Do nothing.
1: Clear RIS.TBMRIS and MIS.TBMMIS

RW

0

10

CBECINT

0: Do nothing.
1: Clear RIS.CBERIS and MIS.CBEMIS

RW

0

9

CBMCINT

0: Do nothing.
1: Clear RIS.CBMRIS and MIS.CBMMIS

RW

0

8

TBTOCINT

0: Do nothing.
1: Clear RIS.TBTORIS and MIS.TBTOMIS

RW

0

7:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

5

DMAAINT

0: Do nothing.
1: Clear RIS.DMAARIS and MIS.DMAAMIS

RW

0

4

TAMCINT

0: Do nothing.
1: Clear RIS.TAMRIS and MIS.TAMMIS

RW

0

3

RTCCINT

0: Do nothing.
1: Clear RIS.RTCRIS and MIS.RTCMIS

RW

0

2

CAECINT

0: Do nothing.
1: Clear RIS.CAERIS and MIS.CAEMIS

RW

0

1

CAMCINT

0: Do nothing.
1: Clear RIS.CAMRIS and MIS.CAMMIS

RW

0

0

TATOCINT

0: Do nothing.
1: Clear RIS.TATORIS and MIS.TATOMIS

RW

0



TOP:GPT:TAILR

Address offset

0x0000 0028

Physical address

0x4001 0028

Instance

GPT0

Description

GPT Timer A Interval Load Register

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

TAILR

GPT Timer A Interval Load Register

RW

0xFFFF FFFF



TOP:GPT:TBILR

Address offset

0x0000 002C

Physical address

0x4001 002C

Instance

GPT0

Description

GPT Timer B Interval Load Register

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

TBILR

GPT Timer B Interval Load Register

RW

0x0000 FFFF



TOP:GPT:TAMATCHR

Address offset

0x0000 0030

Physical address

0x4001 0030

Instance

GPT0

Description

GPT Timer A Match Register

This register is loaded with a match value. Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode.

In Edge-Count mode, this register along with TAILR, determines how many edge events are counted.
The total number of edge events counted is equal to the value in TAILR minus this value.

Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and TAMATCHR.

In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal.

When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR).

In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR.

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

TAMATCHR

GPT Timer A Match Register

RW

0xFFFF FFFF



TOP:GPT:TBMATCHR

Address offset

0x0000 0034

Physical address

0x4001 0034

Instance

GPT0

Description

GPT Timer B Match Register

When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR.
Reads from this register return the current match value of Timer B and writes are ignored.
In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases.

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

TBMATCHR

GPT Timer B Match Register

RW

0x0000 FFFF



TOP:GPT:TAPR

Address offset

0x0000 0038

Physical address

0x4001 0038

Instance

GPT0

Description

GPT Timer A Pre-scale
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter.
When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented.
In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

TAPSR

Timer A Pre-scale.

Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, ie:

0: Prescaler ratio = 1
1: Prescaler ratio = 2
2: Prescaler ratio = 3
...
255: Prescaler ratio = 256

RW

0x00



TOP:GPT:TBPR

Address offset

0x0000 003C

Physical address

0x4001 003C

Instance

GPT0

Description

GPT Timer B Pre-scale
This register allows software to extend the range of the timers when they are used individually.
When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter.
When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented.
In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

TBPSR

Timer B Pre-scale.

Prescale ratio in one-shot and periodic count mode is TBPSR + 1, ie:


0: Prescaler ratio = 1
1: Prescaler ratio = 2
2: Prescaler ratio = 3
...
255: Prescaler ratio = 256

RW

0x00



TOP:GPT:TAPMR

Address offset

0x0000 0040

Physical address

0x4001 0040

Instance

GPT0

Description

GPT Timer A Pre-scale Match
This register allows software to extend the range of the TAMATCHR when used individually.

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

TAPSMR

GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16.

RW

0x00



TOP:GPT:TBPMR

Address offset

0x0000 0044

Physical address

0x4001 0044

Instance

GPT0

Description

GPT Timer B Pre-scale Match
This register allows software to extend the range of the TBMATCHR when used individually.

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

TBPSMR

GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16.

RW

0x00



TOP:GPT:TAR

Address offset

0x0000 0048

Physical address

0x4001 0048

Instance

GPT0

Description

GPT Timer A Register

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

TAR

GPT Timer A Register

A read returns the current value of the Timer A Count Register, in all cases except for Input Edge count and Timer modes.
In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place.

RO

0xFFFF FFFF



TOP:GPT:TBR

Address offset

0x0000 004C

Physical address

0x4001 004C

Instance

GPT0

Description

GPT Timer B Register

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

TBR

GPT Timer B Register

A read returns the current value of the Timer B Count Register, in all cases except for Input Edge count and Timer modes.
In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place.

RO

0x0000 FFFF



TOP:GPT:TAV

Address offset

0x0000 0050

Physical address

0x4001 0050

Instance

GPT0

Description

GPT Timer A Value
This register shows the current value of the free running 16-bit Timer A. In the 32-bit mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

TAV

GPT Timer A Register

RW

0xFFFF FFFF



TOP:GPT:TBV

Address offset

0x0000 0054

Physical address

0x4001 0054

Instance

GPT0

Description

GPT Timer B Value
This register shows the current value of the free running 16-bit Timer B. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count 1.

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

TBV

GPT Timer B Register

RW

0x0000 FFFF



TOP:GPT:RTCPD

Address offset

0x0000 0058

Physical address

0x4001 0058

Instance

GPT0

Description

GPT RTC Pre-divide Value
This register shows the current value of the RTC pre-divider in RTC mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count -1.

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

RTCPD

GPT RTC Pre-divider

RO

0x7FFF



TOP:GPT:TAPS

Address offset

0x0000 005C

Physical address

0x4001 005C

Instance

GPT0

Description

GPT Timer A Pre-scale Snap-shot
This register shows the current value of the Timer A pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count -1.

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

PSS

GPT Timer A Pre-scaler

RO

0x0000



TOP:GPT:TBPS

Address offset

0x0000 0060

Physical address

0x4001 0060

Instance

GPT0

Description

GPT Timer A Pre-scale Snap-shot
This register shows the current value of the Timer B pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count -1.

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

PSS

GPT Timer B Pre-scaler

RO

0x0000



TOP:GPT:TAPV

Address offset

0x0000 0064

Physical address

0x4001 0064

Instance

GPT0

Description

GPT Timer A Pre-scale Value
This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count 1.

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

PSV

GPT Timer A Pre-scaler Value

RO

0x0000



TOP:GPT:TBPV

Address offset

0x0000 0068

Physical address

0x4001 0068

Instance

GPT0

Description

GPT Timer B Pre-scale Value
This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled; a read of a timer value will return the current count-1.

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

PSV

GPT Timer B Pre-scaler Value

RO

0x0000



TOP:GPT:DMAEV

Address offset

0x0000 006C

Physical address

0x4001 006C

Instance

GPT0

Description

GPT DMA Event
This register allows software to enable/disable GPT DMA trigger events.

Type

RW

Bits

Field Name

Description

Type

Reset

31:12

RESERVED12

Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior.

RO

0x0 0000

11

TBMDMAEN

GPT Timer B Match DMA Trigger Enable

RW

0

10

CBEDMAEN

GPT Timer B Capture Event DMA Trigger Enable

RW

0

9

CBMDMAEN

GPT Timer B Capture Match DMA Trigger Enable

RW

0

8

TBTODMAEN

GPT Timer B Time-Out DMA Trigger Enable

RW

0

7:5

RESERVED5

Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior.

RW

0x0

4

TAMDMAEN

GPT Timer A Match DMA Trigger Enable

RW

0

3

RTCDMAEN

GPT RTC Match DMA Trigger Enable

RW

0

2

CAEDMAEN

GPT Timer A Capture Event DMA Trigger Enable

RW

0

1

CAMDMAEN

GPT Timer A Capture Match DMA Trigger Enable

RW

0

0

TATODMAEN

GPT Timer A Time-Out DMA Trigger Enable

RW

0



TOP:GPT:ADCEV

Address offset

0x0000 0070

Physical address

0x4001 0070

Instance

GPT0

Description

GPT ADC Event
This register allows software to enable/disable GPT ADC trigger events.

Type

RW

Bits

Field Name

Description

Type

Reset

31:12

RESERVED12

Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior.

RO

0x0 0000

11

TBMADCEN

GPT Timer B Match ADC Trigger Enable

RW

0

10

CBEADCEN

GPT Timer B Capture Event ADC Trigger Enable

RW

0

9

CBMADCEN

GPT Timer B Capture Match ADC Trigger Enable

RW

0

8

TBTOADCEN

GPT Timer B Time-Out ADC Trigger Enable

RW

0

7:5

RESERVED5

Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior.

RW

0x0

4

TAMADCEN

GPT Timer A Match ADC Trigger Enable

RW

0

3

RTCADCEN

GPT RTC Match ADC Trigger Enable

RW

0

2

CAEADCEN

GPT Timer A Capture Event ADC Trigger Enable

RW

0

1

CAMADCEN

GPT Timer A Capture Match ADC Trigger Enable

RW

0

0

TATOADCEN

GPT Timer A Time-Out ADC Trigger Enable

RW

0



TOP:GPT:VERSION

Address offset

0x0000 0FB0

Physical address

0x4001 0FB0

Instance

GPT0

Description

GPT Peripheral Version
This register provides information regarding the GPT version

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

VERSION

Timer Revision.

RO

0x0000 0400



TOP:GPT:ANDCCP

Address offset

0x0000 0FB4

Physical address

0x4001 0FB4

Instance

GPT0

Description

GPT Combined CCP Output
This register is used to logically AND CCP output pairs for each timer

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

CCP_AND_EN

Enables anding of the CCP outputs for timers A and B

RW

0