ADI_3_REFSYS

Instance: ADI_3_REFSYS
Component: ADI_3_REFSYS
Base address: 0x40086200

 

ADI for REFSYS modules.
Registers Fields should be considered static unless otherwise noted (as dynamic)

 

TOP:ADI_3_REFSYS Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

ATESTCTL0

RW

8

0x0000 0000

0x0000 0000

0x4008 6200

SPARE0

RW

8

0x0000 0000

0x0000 0001

0x4008 6201

REFSYSCTL0

RW

8

0x0000 0000

0x0000 0002

0x4008 6202

REFSYSCTL1

RW

8

0x0000 0000

0x0000 0003

0x4008 6203

REFSYSCTL2

RW

8

0x0000 0000

0x0000 0004

0x4008 6204

REFSYSCTL3

RW

8

0x0000 0000

0x0000 0005

0x4008 6205

DCDCCTL0

RW

8

0x0000 0000

0x0000 0006

0x4008 6206

DCDCCTL1

RW

8

0x0000 0000

0x0000 0007

0x4008 6207

DCDCCTL2

RW

8

0x0000 0000

0x0000 0008

0x4008 6208

DCDCCTL3

RW

8

0x0000 0000

0x0000 0009

0x4008 6209

DCDCCTL4

RW

8

0x0000 0000

0x0000 000A

0x4008 620A

DCDCCTL5

RW

8

0x0000 0000

0x0000 000B

0x4008 620B

TOP:ADI_3_REFSYS Register Descriptions

TOP:ADI_3_REFSYS:ATESTCTL0

Address offset

0x0000 0000

Physical address

0x4008 6200

Instance

ADI_3_REFSYS

Description

Analog Test Control 0
Note ATEST bits must be set in the correct order!

Type

RW

Bits

Field Name

Description

Type

Reset

7:4

SPARE4

RSVD, not used at this time.

RW

0x0

3:0

TEST_CTL

ATEST muxing:

Value

ENUM name

Description

0x0

NC

No signal connected to ATEST outputs

0x1

DIGLDOV_A1

DIGLDO_V on ATEST1

0x2

REFSYSP_A1

REFSYSP on ATEST1

0x4

DIGLDOI_A0

DIGLDO_I on ATEST0

0x8

DCDC_A0

DCDC on ATEST0

RW

0x0



TOP:ADI_3_REFSYS:SPARE0

Address offset

0x0000 0001

Physical address

0x4008 6201

Instance

ADI_3_REFSYS

Description

Analog Test Control

Type

RW

Bits

Field Name

Description

Type

Reset

7:0

SPARE0

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0x00



TOP:ADI_3_REFSYS:REFSYSCTL0

Address offset

0x0000 0002

Physical address

0x4008 6202

Instance

ADI_3_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7:0

TESTCTL

Internal

Value

ENUM name

Description

0x00

NC

Internal

0x01

IPTAT2U

Internal

0x02

IVREF4U

Internal

0x04

IREF4U

Internal

0x08

VBG

Internal

0x10

VBGUNBUFF

Internal

0x20

VREF0P8V

Internal

0x40

VTEMP

Internal

0x80

BMCOMPOUT

Internal

RW

0x00



TOP:ADI_3_REFSYS:REFSYSCTL1

Address offset

0x0000 0003

Physical address

0x4008 6203

Instance

ADI_3_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7:3

TRIM_VDDS_BOD

Internal

Value

ENUM name

Description

0x00

POS_4

Internal

0x01

POS_5

Internal

0x02

POS_6

Internal

0x03

POS_7

Internal

0x04

POS_0

Internal

0x05

POS_1

Internal

0x06

POS_2

Internal

0x07

POS_3

Internal

0x08

POS_12

Internal

0x09

POS_13

Internal

0x0A

POS_14

Internal

0x0B

POS_15

Internal

0x0C

POS_8

Internal

0x0D

POS_9

Internal

0x0E

POS_10

Internal

0x0F

POS_11

Internal

0x10

POS_20

Internal

0x11

POS_21

Internal

0x12

POS_22

Internal

0x13

POS_23

Internal

0x14

POS_16

Internal

0x15

POS_17

Internal

0x16

POS_18

Internal

0x17

POS_19

Internal

0x18

POS_28

Internal

0x19

POS_29

Internal

0x1A

POS_30

Internal

0x1B

POS_31

Internal

0x1C

POS_24

Internal

0x1D

POS_25

Internal

0x1E

POS_26

Internal

0x1F

POS_27

Internal

RW

0x00

2

BATMON_COMP_TEST_EN

Internal

Value

ENUM name

Description

0

DIS

Internal

1

EN

Internal

RW

0

1:0

TESTCTL

Internal

Value

ENUM name

Description

0x0

NC

Internal

0x1

BMCOMPIN

Internal

0x2

IPTAT1U

Internal

RW

0x0



TOP:ADI_3_REFSYS:REFSYSCTL2

Address offset

0x0000 0004

Physical address

0x4008 6204

Instance

ADI_3_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7:4

TRIM_VREF

Internal

RW

0x0

3:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0

1:0

TRIM_TSENSE

Internal

RW

0x0



TOP:ADI_3_REFSYS:REFSYSCTL3

Address offset

0x0000 0005

Physical address

0x4008 6205

Instance

ADI_3_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7

BOD_BG_TRIM_EN

Internal

RW

0

6

VTEMP_EN

Internal

Value

ENUM name

Description

0

DIS

Internal

1

EN

Internal

RW

0

5:0

TRIM_VBG

Internal

RW

0x00



TOP:ADI_3_REFSYS:DCDCCTL0

Address offset

0x0000 0006

Physical address

0x4008 6206

Instance

ADI_3_REFSYS

Description

DCDC Control Register 0

Type

RW

Bits

Field Name

Description

Type

Reset

7:5

GLDO_ISRC

Set charge and re-charge current level.
2's complement encoding.

0x0: Default 11mA.
0x3: Max 15mA.
0x4: Max 5mA

RW

0x0

4:0

VDDR_TRIM

Set the VDDR voltage.
Proprietary encoding.

Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15.
Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16.
Step size = 16mV

0x00: Default, about 1.63V.
0x05: Typical voltage after trim voltage 1.71V.
0x15: Max voltage 1.96V.
0x16: Min voltage 1.47V.

RW

0x00



TOP:ADI_3_REFSYS:DCDCCTL1

Address offset

0x0000 0007

Physical address

0x4008 6207

Instance

ADI_3_REFSYS

Description

DCDC Control Register 1

Type

RW

Bits

Field Name

Description

Type

Reset

7:6

IPTAT_TRIM

Trim GLDO bias current.
Proprietary encoding.

0x0: Default
0x1: Increase GLDO bias by 1.3x.
0x2: Increase GLDO bias by 1.6x.
0x3: Decrease GLDO bias by 0.7x.

RW

0x0

5

VDDR_OK_HYST

Increase the hysteresis for when VDDR is considered ok.

0: Hysteresis = 60mV
1: Hysteresis = 70mV

RW

0

4:0

VDDR_TRIM_SLEEP

Set the min VDDR voltage threshold during sleep mode.
Proprietary encoding.

Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15.
Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16.
Step size = 16mV

0x00: Default, about 1.63V.
0x19: Typical voltage after trim voltage 1.52V.
0x15: Max voltage 1.96V.
0x16: Min voltage 1.47V.

RW

0x00



TOP:ADI_3_REFSYS:DCDCCTL2

Address offset

0x0000 0008

Physical address

0x4008 6208

Instance

ADI_3_REFSYS

Description

DCDC Control Register 2

Type

RW

Bits

Field Name

Description

Type

Reset

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

6

TURNON_EA_SW

Turn on erroramp switch

0: Erroramp Off (Default)
1: Erroramp On. Turns on GLDO error amp switch.

RW

0

5

TEST_VDDR

Connect VDDR to ATEST bus

0: Not connected.
1: Connected

Set TESTSEL = 0x0 first before setting this bit.

RW

0

4

BIAS_DIS

Disable dummy bias current.

0: Dummy bias current on (Default)
1: Dummy bias current off

RW

0

3:0

TESTSEL

Select signal for test bus, one hot.

Value

ENUM name

Description

0x0

NC

No signal connected to test bus.

0x1

ERRAMP_OUT

Error amp output voltage connected to test bus.

0x2

PASSGATE

Pass transistor gate voltage connected to test bus.

0x4

IB1U

1uA bias current connected to test bus.

0x8

VDDROK

VDDR_OK connected to test bus.

RW

0x0



TOP:ADI_3_REFSYS:DCDCCTL3

Address offset

0x0000 0009

Physical address

0x4008 6209

Instance

ADI_3_REFSYS

Description

DCDC Control Register 3

Type

RW

Bits

Field Name

Description

Type

Reset

7:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x00



TOP:ADI_3_REFSYS:DCDCCTL4

Address offset

0x0000 000A

Physical address

0x4008 620A

Instance

ADI_3_REFSYS

Description

DCDC Control Register 5

Type

RW

Bits

Field Name

Description

Type

Reset

7:6

DEADTIME_TRIM

Adjust the supply voltage threshold below which the non overlap delay of the switch driver block decreases.
Unsigned encoding.

0x0: Min 2.24v. Default.
0x3: Max 2.78v.

RW

0x0

5:3

LOW_EN_SEL

Control NMOS switch strength in linear steps.
Unsigned encoding.

0x0: Switches are off. Dcdc will not operate.
0x1: Minimum switch strength.
0x7: Maximum switch strength. Typical setting.

RW

0x0

2:0

HIGH_EN_SEL

Control PMOS switch strength in linear steps.
Unsigned encoding.

0x0: Switches are off. Dcdc will not operate.
0x1: Minimum switch strength.
0x7: Maximum switch strength. Typical setting.

RW

0x0



TOP:ADI_3_REFSYS:DCDCCTL5

Address offset

0x0000 000B

Physical address

0x4008 620B

Instance

ADI_3_REFSYS

Description

DCDC Control Register 6

Type

RW

Bits

Field Name

Description

Type

Reset

7:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0

5

TESTN

Buck converter NMOS switch is turned on.

0: Default

When TESTP = TESTN = 0 then the inductor shunt switch is turned on and PMOS and NMOS switches are off.

RW

0

4

TESTP

Buck converter PMOS switch is turned on.

0: Default

When TESTP = TESTN = 0 then the inductor shunt switch is turned on and PMOS and NMOS switches are off.

RW

0

3

DITHER_EN

Enable switching frequency randomizer

Value

ENUM name

Description

0

DIS

Disable

1

EN

Enable

RW

0

2:0

IPEAK

Set inductor peak current.
Unsigned encoding.

0x0: Min 31mA
0x4: Typical 47mA
0x7: Max 59mA

RW

0x0