Instance: WDT
Component: WDT
Base address: 0x40080000
Watchdog Timer
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0xFFFF FFFF |
0x0000 0000 |
0x4008 0000 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0004 |
0x4008 0004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4008 0008 |
|
WO |
32 |
0x0000 0000 |
0x0000 000C |
0x4008 000C |
|
RO |
32 |
0x0000 0000 |
0x0000 0010 |
0x4008 0010 |
|
RO |
32 |
0x0000 0000 |
0x0000 0014 |
0x4008 0014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0418 |
0x4008 0418 |
|
RO |
32 |
0x0000 0000 |
0x0000 041C |
0x4008 041C |
|
RW |
32 |
0x0000 0000 |
0x0000 0C00 |
0x4008 0C00 |
|
RO |
32 |
0x0000 0000 |
0x0000 0FD0 |
0x4008 0FD0 |
|
RO |
32 |
0x0000 0000 |
0x0000 0FD4 |
0x4008 0FD4 |
|
RO |
32 |
0x0000 0000 |
0x0000 0FD8 |
0x4008 0FD8 |
|
RO |
32 |
0x0000 0000 |
0x0000 0FDC |
0x4008 0FDC |
|
RO |
32 |
0x0000 0005 |
0x0000 0FE0 |
0x4008 0FE0 |
|
RO |
32 |
0x0000 0018 |
0x0000 0FE4 |
0x4008 0FE4 |
|
RO |
32 |
0x0000 0018 |
0x0000 0FE8 |
0x4008 0FE8 |
|
RO |
32 |
0x0000 0001 |
0x0000 0FEC |
0x4008 0FEC |
|
RO |
32 |
0x0000 000D |
0x0000 0FF0 |
0x4008 0FF0 |
|
RO |
32 |
0x0000 00F0 |
0x0000 0FF4 |
0x4008 0FF4 |
|
RO |
32 |
0x0000 0006 |
0x0000 0FF8 |
0x4008 0FF8 |
|
RO |
32 |
0x0000 00B1 |
0x0000 0FFC |
0x4008 0FFC |
Address offset |
0x0000 0000 |
||
Physical address |
0x4008 0000 |
Instance |
WDT |
Description |
WDT Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
WDTLOAD |
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter is restarted to count down from the new value. If this register is loaded with 0x0000.0000, an interrupt is immediately generated. |
RW |
0xFFFF FFFF |
Address offset |
0x0000 0004 |
||
Physical address |
0x4008 0004 |
Instance |
WDT |
Description |
WDT Current Count Value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
WDTVALUE |
This register contains the current count value of the timer. |
RO |
0xFFFF FFFF |
Address offset |
0x0000 0008 |
||
Physical address |
0x4008 0008 |
Instance |
WDT |
Description |
WDT Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||
2 |
INTTYPE |
WDT Interrupt Type
|
RW |
0 |
|||||||||||||
1 |
RESEN |
WDT Reset Enable. Defines the function of the WDT reset source (see PRCM:WARMRESET.WDT_STAT if enabled)
|
RW |
0 |
|||||||||||||
0 |
INTEN |
WDT Interrupt Enable
|
RW |
0 |
Address offset |
0x0000 000C |
||
Physical address |
0x4008 000C |
Instance |
WDT |
Description |
WDT Interrupt Clear |
||
Type |
WO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
WDTICR |
This register is the interrupt clear register. A write of any value to this register clears the WDT interrupt and reloads the 32-bit counter from the LOAD register. |
WO |
0x0000 0000 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4008 0010 |
Instance |
WDT |
Description |
WDT Raw Interrupt Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
WDTRIS |
This register is the raw interrupt status register. WDT interrupt events can be monitored via this register if the controller interrupt is masked. |
RO |
0 |
Address offset |
0x0000 0014 |
||
Physical address |
0x4008 0014 |
Instance |
WDT |
Description |
WDT Masked Interrupt Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
WDTMIS |
This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the WDT interrupt enable bit CTL.INTEN. |
RO |
0 |
Address offset |
0x0000 0418 |
||
Physical address |
0x4008 0418 |
Instance |
WDT |
Description |
WDT Test Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:9 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||
8 |
STALL |
WDT Stall Enable
|
RW |
0 |
|||||||||||||
7:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
|||||||||||||
0 |
TEST_EN |
The test enable bit
|
RW |
0 |
Address offset |
0x0000 041C |
||
Physical address |
0x4008 041C |
Instance |
WDT |
Description |
WDT Interrupt Cause Test Mode |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
CAUSE_RESET |
Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). |
RO |
0 |
||
0 |
CAUSE_INTR |
Replica of RIS.WDTRIS |
RO |
0 |
Address offset |
0x0000 0C00 |
||
Physical address |
0x4008 0C00 |
Instance |
WDT |
Description |
WDT Lock Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
WDTLOCK |
WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates (NOTE: TEST.TEST_EN bit is not lockable). |
RW |
0x0000 0000 |
Address offset |
0x0000 0FD0 |
||
Physical address |
0x4008 0FD0 |
Instance |
WDT |
Description |
WDT Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
PID4 |
RO |
0x00 |
Address offset |
0x0000 0FD4 |
||
Physical address |
0x4008 0FD4 |
Instance |
WDT |
Description |
WDT Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
PID5 |
RO |
0x00 |
Address offset |
0x0000 0FD8 |
||
Physical address |
0x4008 0FD8 |
Instance |
WDT |
Description |
WDT Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
PID6 |
RO |
0x00 |
Address offset |
0x0000 0FDC |
||
Physical address |
0x4008 0FDC |
Instance |
WDT |
Description |
WDT Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
PID7 |
RO |
0x00 |
Address offset |
0x0000 0FE0 |
||
Physical address |
0x4008 0FE0 |
Instance |
WDT |
Description |
WDT Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
PID0 |
RO |
0x05 |
Address offset |
0x0000 0FE4 |
||
Physical address |
0x4008 0FE4 |
Instance |
WDT |
Description |
WDT Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
PID1 |
RO |
0x18 |
Address offset |
0x0000 0FE8 |
||
Physical address |
0x4008 0FE8 |
Instance |
WDT |
Description |
WDT Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
PID2 |
RO |
0x18 |
Address offset |
0x0000 0FEC |
||
Physical address |
0x4008 0FEC |
Instance |
WDT |
Description |
WDT Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
PID3 |
RO |
0x01 |
Address offset |
0x0000 0FF0 |
||
Physical address |
0x4008 0FF0 |
Instance |
WDT |
Description |
WDT Cell Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
CID0 |
RO |
0x0D |
Address offset |
0x0000 0FF4 |
||
Physical address |
0x4008 0FF4 |
Instance |
WDT |
Description |
WDT Cell Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
CID1 |
RO |
0xF0 |
Address offset |
0x0000 0FF8 |
||
Physical address |
0x4008 0FF8 |
Instance |
WDT |
Description |
WDT Cell Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
CID2 |
RO |
0x06 |
Address offset |
0x0000 0FFC |
||
Physical address |
0x4008 0FFC |
Instance |
WDT |
Description |
WDT Cell Identity |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
CID3 |
RO |
0xB1 |
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