FCFG1

Instance: FCFG1
Component: FCFG1
Base address: 0x50001000

 

Factory configuration area (FCFG1)

 

TOP:FCFG1 Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

CONFIG_RF_FRONTEND_DIV5

RW

32

0x0000 3F80

0x0000 00C4

0x5000 10C4

CONFIG_RF_FRONTEND_DIV6

RW

32

0x0000 3F80

0x0000 00C8

0x5000 10C8

CONFIG_RF_FRONTEND_DIV10

RW

32

0x0000 3F80

0x0000 00CC

0x5000 10CC

CONFIG_RF_FRONTEND_DIV12

RW

32

0x0000 3F80

0x0000 00D0

0x5000 10D0

CONFIG_RF_FRONTEND_DIV15

RW

32

0x0000 3F80

0x0000 00D4

0x5000 10D4

CONFIG_RF_FRONTEND_DIV30

RW

32

0x0000 3F80

0x0000 00D8

0x5000 10D8

CONFIG_SYNTH_DIV5

RW

32

0xF800 0000

0x0000 00DC

0x5000 10DC

CONFIG_SYNTH_DIV6

RW

32

0xF800 0000

0x0000 00E0

0x5000 10E0

CONFIG_SYNTH_DIV10

RW

32

0xF800 0000

0x0000 00E4

0x5000 10E4

CONFIG_SYNTH_DIV12

RW

32

0xF800 0000

0x0000 00E8

0x5000 10E8

CONFIG_SYNTH_DIV15

RW

32

0xF800 0000

0x0000 00EC

0x5000 10EC

CONFIG_SYNTH_DIV30

RW

32

0xF800 0000

0x0000 00F0

0x5000 10F0

CONFIG_MISC_ADC_DIV5

RW

32

0xFFFE 0000

0x0000 00F4

0x5000 10F4

CONFIG_MISC_ADC_DIV6

RW

32

0xFFFE 0000

0x0000 00F8

0x5000 10F8

CONFIG_MISC_ADC_DIV10

RW

32

0xFFFE 0000

0x0000 00FC

0x5000 10FC

CONFIG_MISC_ADC_DIV12

RW

32

0xFFFE 0000

0x0000 0100

0x5000 1100

CONFIG_MISC_ADC_DIV15

RW

32

0xFFFE 0000

0x0000 0104

0x5000 1104

CONFIG_MISC_ADC_DIV30

RW

32

0xFFFE 0000

0x0000 0108

0x5000 1108

SHDW_EFUSE_CONTROL

RW

32

0x0000 0000

0x0000 010C

0x5000 110C

SHDW_REDUNDANT0

RW

32

0x0000 0000

0x0000 0110

0x5000 1110

SHDW_REDUNDANT1

RW

32

0x0000 0000

0x0000 0114

0x5000 1114

SHDW_DIE_ID_0

RW

32

0x0000 0000

0x0000 0118

0x5000 1118

SHDW_DIE_ID_1

RW

32

0x0000 0000

0x0000 011C

0x5000 111C

SHDW_DIE_ID_2

RW

32

0x0000 0000

0x0000 0120

0x5000 1120

SHDW_DIE_ID_3

RW

32

0x0000 0000

0x0000 0124

0x5000 1124

SHDW_SCAN_DATA0

RW

32

0x0000 0000

0x0000 0128

0x5000 1128

SHDW_SCAN_DATA1

RW

32

0x0000 0000

0x0000 012C

0x5000 112C

SHDW_SCAN_DATA2_BOOT

RW

32

0x0000 0000

0x0000 0130

0x5000 1130

SHDW_BANK_TRIM_BOOT

RW

32

0x0000 0000

0x0000 0134

0x5000 1134

SHDW_OSC_BIAS_LDO_TRIM

RW

32

0x0000 0000

0x0000 0138

0x5000 1138

SHDW_ANA_TRIM

RW

32

0x0000 0000

0x0000 013C

0x5000 113C

FLASH_E_P

RW

32

0x1616 1919

0x0000 0170

0x5000 1170

FLASH_C_E_P_R

RW

32

0x0205 2000

0x0000 0174

0x5000 1174

FLASH_P_R_PV

RW

32

0x095A 0100

0x0000 0178

0x5000 1178

FLASH_EH_SEQ

RW

32

0x5800 3000

0x0000 017C

0x5000 117C

FLASH_VHV_E

RW

32

0x0004 0001

0x0000 0180

0x5000 1180

FLASH_PP

RW

32

0x00XX 0006

0x0000 0184

0x5000 1184

FLASH_PROG_EP

RW

32

0x0020 000B

0x0000 0188

0x5000 1188

FLASH_ERA_PW

RW

32

0x0000 1740

0x0000 018C

0x5000 118C

FLASH_VHV

RW

32

0xFXFX FXF4

0x0000 0190

0x5000 1190

FLASH_VHV_PV

RW

32

0xFXF0 XX00

0x0000 0194

0x5000 1194

FLASH_V

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 0198

0x5000 1198

USER_ID

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 0294

0x5000 1294

FLASH_OTP_DATA1

RW

32

0x0003 E703

0x0000 02A8

0x5000 12A8

FLASH_OTP_DATA2

RW

32

0x2F2F 2FF3

0x0000 02AC

0x5000 12AC

FLASH_OTP_DATA3

RW

32

0x0310 XX03

0x0000 02B0

0x5000 12B0

MAC_BLE_0

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 02E8

0x5000 12E8

MAC_BLE_1

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 02EC

0x5000 12EC

MAC_15_4_0

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 02F0

0x5000 12F0

MAC_15_4_1

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 02F4

0x5000 12F4

FLASH_OTP_DATA4

RW

32

0x1818 0000

0x0000 0308

0x5000 1308

MISC_TRIM

RW

32

0xFFFF FF33

0x0000 030C

0x5000 130C

RCOSC_HF_TEMPCOMP

RW

32

0x0000 0003

0x0000 0310

0x5000 1310

TRIM_CAL_REVISION

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 0314

0x5000 1314

ICEPICK_DEVICE_ID

RW

32

0x8B99 A02F

0x0000 0318

0x5000 1318

FCFG1_REVISION

RW

32

0x0000 0000

0x0000 031C

0x5000 131C

MISC_OTP_DATA

RW

32

0xFFF0 C5XX

0x0000 0320

0x5000 1320

IOCONF

RW

32

0b1111_1111_1111_1111_1111_1111_1XXX_XXXX

0x0000 0344

0x5000 1344

CONFIG_IF_ADC

RW

32

0b0000_0000_0000_0000_0000_00XX_XXXX_XXXX

0x0000 034C

0x5000 134C

CONFIG_OSC_TOP

RW

32

0b1100_0000_0000_0000_0000_00XX_XXXX_XX00

0x0000 0350

0x5000 1350

CONFIG_RF_FRONTEND

RW

32

0b0000_XXXX_0000_0XXX_XXX1_1111_1XXX_XXXX

0x0000 0354

0x5000 1354

CONFIG_SYNTH

RW

32

0xF800 0XXX

0x0000 0358

0x5000 1358

SOC_ADC_ABS_GAIN

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 035C

0x5000 135C

SOC_ADC_REL_GAIN

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 0360

0x5000 1360

SOC_ADC_EXT_GAIN

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 0364

0x5000 1364

SOC_ADC_OFFSET_INT

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 0368

0x5000 1368

SOC_ADC_REF_TRIM_AND_OFFSET_EXT

RW

32

0b00XX_XXXX_00XX_XXXX_0000_0000_0000_0000

0x0000 036C

0x5000 136C

AMPCOMP_TH1

RW

32

0xFF6B 76A4

0x0000 0370

0x5000 1370

AMPCOMP_TH2

RW

32

0x6B8B 0303

0x0000 0374

0x5000 1374

AMPCOMP_CTRL1

RW

32

0xFF71 3F27

0x0000 0378

0x5000 1378

ANABYPASS_VALUE2

RW

32

0xFFFF C3FF

0x0000 037C

0x5000 137C

CONFIG_MISC_ADC

RW

32

0b1111_1111_1111_11XX_XXXX_XXX0_0000_0000

0x0000 0380

0x5000 1380

TEST_TEMPS

RW

32

0x0000 0000

0x0000 0384

0x5000 1384

VOLT_TRIM

RW

32

0b1111_1111_1111_1111_1111_1111_111X_XXXX

0x0000 0388

0x5000 1388

OSC_CONF

RW

32

0b1111_0000_0000_0XXX_XXXX_XXXX_XXXX_XXXX

0x0000 038C

0x5000 138C

FREQ_OFFSET

RW

32

0bX000_0000_0000_0000_0000_0000_0000_0000

0x0000 0390

0x5000 1390

CAP_TRIM

RW

32

0xFFFF FFFF

0x0000 0394

0x5000 1394

MISC_OTP_DATA_1

RW

32

0xE004 03F4

0x0000 0398

0x5000 1398

PWD_CURR_20C

RW

32

0xFFFF FFFF

0x0000 039C

0x5000 139C

PWD_CURR_35C

RW

32

0xFFFF FFFF

0x0000 03A0

0x5000 13A0

PWD_CURR_50C

RW

32

0xFFFF FFFF

0x0000 03A4

0x5000 13A4

PWD_CURR_65C

RW

32

0xFFFF FFFF

0x0000 03A8

0x5000 13A8

PWD_CURR_80C

RW

32

0xFFFF FFFF

0x0000 03AC

0x5000 13AC

PWD_CURR_95C

RW

32

0xFFFF FFFF

0x0000 03B0

0x5000 13B0

PWD_CURR_110C

RW

32

0xFFFF FFFF

0x0000 03B4

0x5000 13B4

PWD_CURR_125C

RW

32

0xFFFF FFFF

0x0000 03B8

0x5000 13B8

TOP:FCFG1 Register Descriptions

TOP:FCFG1:CONFIG_RF_FRONTEND_DIV5

Address offset

0x0000 00C4

Physical address

0x5000 10C4

Instance

FCFG1

Description

Configuration of RF Frontend in Divide-by-5 Mode
Divide-by-5 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

IFAMP_IB

Trim value used for ADI_0_RF:IFAMPCTL3.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

27:24

LNA_IB

Trim value for ADI_0_RF:LNACTL2.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

23:19

IFAMP_TRIM

Trim value for ADI_0_RF:IFAMPCTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

18:14

CTL_PA0_TRIM

Trim value for ADI_0_RF:PACTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

13:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7F

6:0

RFLDO_TRIM_OUTPUT

Trim value for ADI_0_RF:RFLDO1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_RF_FRONTEND_DIV6

Address offset

0x0000 00C8

Physical address

0x5000 10C8

Instance

FCFG1

Description

Configuration of RF Frontend in Divide-by-6 Mode
Divide-by-6 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

IFAMP_IB

Trim value used for ADI_0_RF:IFAMPCTL3.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

27:24

LNA_IB

Trim value for ADI_0_RF:LNACTL2.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

23:19

IFAMP_TRIM

Trim value for ADI_0_RF:IFAMPCTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

18:14

CTL_PA0_TRIM

Trim value for ADI_0_RF:PACTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

13:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7F

6:0

RFLDO_TRIM_OUTPUT

Trim value for ADI_0_RF:RFLDO1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_RF_FRONTEND_DIV10

Address offset

0x0000 00CC

Physical address

0x5000 10CC

Instance

FCFG1

Description

Configuration of RF Frontend in Divide-by-10 Mode
Divide-by-10 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

IFAMP_IB

Trim value used for ADI_0_RF:IFAMPCTL3.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

27:24

LNA_IB

Trim value for ADI_0_RF:LNACTL2.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

23:19

IFAMP_TRIM

Trim value for ADI_0_RF:IFAMPCTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

18:14

CTL_PA0_TRIM

Trim value for ADI_0_RF:PACTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

13:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7F

6:0

RFLDO_TRIM_OUTPUT

Trim value for ADI_0_RF:RFLDO1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_RF_FRONTEND_DIV12

Address offset

0x0000 00D0

Physical address

0x5000 10D0

Instance

FCFG1

Description

Configuration of RF Frontend in Divide-by-12 Mode
Divide-by-12 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

IFAMP_IB

Trim value used for ADI_0_RF:IFAMPCTL3.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

27:24

LNA_IB

Trim value for ADI_0_RF:LNACTL2.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

23:19

IFAMP_TRIM

Trim value for ADI_0_RF:IFAMPCTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

18:14

CTL_PA0_TRIM

Trim value for ADI_0_RF:PACTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

13:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7F

6:0

RFLDO_TRIM_OUTPUT

Trim value for ADI_0_RF:RFLDO1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_RF_FRONTEND_DIV15

Address offset

0x0000 00D4

Physical address

0x5000 10D4

Instance

FCFG1

Description

Configuration of RF Frontend in Divide-by-15 Mode
Divide-by-15 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

IFAMP_IB

Trim value used for ADI_0_RF:IFAMPCTL3.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

27:24

LNA_IB

Trim value for ADI_0_RF:LNACTL2.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

23:19

IFAMP_TRIM

Trim value for ADI_0_RF:IFAMPCTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

18:14

CTL_PA0_TRIM

Trim value for ADI_0_RF:PACTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

13:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7F

6:0

RFLDO_TRIM_OUTPUT

Trim value for ADI_0_RF:RFLDO1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_RF_FRONTEND_DIV30

Address offset

0x0000 00D8

Physical address

0x5000 10D8

Instance

FCFG1

Description

Configuration of RF Frontend in Divide-by-30 Mode
Divide-by-30 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

IFAMP_IB

Trim value used for ADI_0_RF:IFAMPCTL3.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

27:24

LNA_IB

Trim value for ADI_0_RF:LNACTL2.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

23:19

IFAMP_TRIM

Trim value for ADI_0_RF:IFAMPCTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

18:14

CTL_PA0_TRIM

Trim value for ADI_0_RF:PACTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

13:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7F

6:0

RFLDO_TRIM_OUTPUT

Trim value for ADI_0_RF:RFLDO1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_SYNTH_DIV5

Address offset

0x0000 00DC

Physical address

0x5000 10DC

Instance

FCFG1

Description

Configuration of Synthesizer in Divide-by-5 Mode
Divide-by-5 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

27:12

RFC_MDM_DEMIQMC0

Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x8000

11:6

LDOVCO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

5:0

SLDO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_SYNTH_DIV6

Address offset

0x0000 00E0

Physical address

0x5000 10E0

Instance

FCFG1

Description

Configuration of Synthesizer in Divide-by-6 Mode
Divide-by-6 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

27:12

RFC_MDM_DEMIQMC0

Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x8000

11:6

LDOVCO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

5:0

SLDO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_SYNTH_DIV10

Address offset

0x0000 00E4

Physical address

0x5000 10E4

Instance

FCFG1

Description

Configuration of Synthesizer in Divide-by-10 Mode
Divide-by-10 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

27:12

RFC_MDM_DEMIQMC0

Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x8000

11:6

LDOVCO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

5:0

SLDO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_SYNTH_DIV12

Address offset

0x0000 00E8

Physical address

0x5000 10E8

Instance

FCFG1

Description

Configuration of Synthesizer in Divide-by-12 Mode
Divide-by-12 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

27:12

RFC_MDM_DEMIQMC0

Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x8000

11:6

LDOVCO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

5:0

SLDO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_SYNTH_DIV15

Address offset

0x0000 00EC

Physical address

0x5000 10EC

Instance

FCFG1

Description

Configuration of Synthesizer in Divide-by-15 Mode
Divide-by-15 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

27:12

RFC_MDM_DEMIQMC0

Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x8000

11:6

LDOVCO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

5:0

SLDO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_SYNTH_DIV30

Address offset

0x0000 00F0

Physical address

0x5000 10F0

Instance

FCFG1

Description

Configuration of Synthesizer in Divide-by-30 Mode
Divide-by-30 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

27:12

RFC_MDM_DEMIQMC0

Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x8000

11:6

LDOVCO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

5:0

SLDO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_MISC_ADC_DIV5

Address offset

0x0000 00F4

Physical address

0x5000 10F4

Instance

FCFG1

Description

Configuration of IFADC in Divide-by-5 Mode
Divide-by-5 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7FFF

16:9

RSSI_OFFSET

Value for RSSI measured in production test.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

8:6

QUANTCTLTHRES

Trim value for ADI_0_RF:IFADCQUANT0.TH.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

5:0

DACTRIM

Trim value for ADI_0_RF:IFADCDAC.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_MISC_ADC_DIV6

Address offset

0x0000 00F8

Physical address

0x5000 10F8

Instance

FCFG1

Description

Configuration of IFADC in Divide-by-6 Mode
Divide-by-6 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7FFF

16:9

RSSI_OFFSET

Value for RSSI measured in production test.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

8:6

QUANTCTLTHRES

Trim value for ADI_0_RF:IFADCQUANT0.TH.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

5:0

DACTRIM

Trim value for ADI_0_RF:IFADCDAC.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_MISC_ADC_DIV10

Address offset

0x0000 00FC

Physical address

0x5000 10FC

Instance

FCFG1

Description

Configuration of IFADC in Divide-by-10 Mode
Divide-by-10 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7FFF

16:9

RSSI_OFFSET

Value for RSSI measured in production test.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

8:6

QUANTCTLTHRES

Trim value for ADI_0_RF:IFADCQUANT0.TH.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

5:0

DACTRIM

Trim value for ADI_0_RF:IFADCDAC.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_MISC_ADC_DIV12

Address offset

0x0000 0100

Physical address

0x5000 1100

Instance

FCFG1

Description

Configuration of IFADC in Divide-by-12 Mode
Divide-by-12 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7FFF

16:9

RSSI_OFFSET

Value for RSSI measured in production test.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

8:6

QUANTCTLTHRES

Trim value for ADI_0_RF:IFADCQUANT0.TH.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

5:0

DACTRIM

Trim value for ADI_0_RF:IFADCDAC.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_MISC_ADC_DIV15

Address offset

0x0000 0104

Physical address

0x5000 1104

Instance

FCFG1

Description

Configuration of IFADC in Divide-by-15 Mode
Divide-by-15 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7FFF

16:9

RSSI_OFFSET

Value for RSSI measured in production test.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

8:6

QUANTCTLTHRES

Trim value for ADI_0_RF:IFADCQUANT0.TH.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

5:0

DACTRIM

Trim value for ADI_0_RF:IFADCDAC.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:CONFIG_MISC_ADC_DIV30

Address offset

0x0000 0108

Physical address

0x5000 1108

Instance

FCFG1

Description

Configuration of IFADC in Divide-by-30 Mode
Divide-by-30 mode is only available for CC13xx.

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7FFF

16:9

RSSI_OFFSET

Value for RSSI measured in production test.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

8:6

QUANTCTLTHRES

Trim value for ADI_0_RF:IFADCQUANT0.TH.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

5:0

DACTRIM

Trim value for ADI_0_RF:IFADCDAC.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:SHDW_EFUSE_CONTROL

Address offset

0x0000 010C

Physical address

0x5000 110C

Instance

FCFG1

Description

Shadow of Efuse row 0

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0000 0000



TOP:FCFG1:SHDW_REDUNDANT0

Address offset

0x0000 0110

Physical address

0x5000 1110

Instance

FCFG1

Description

Shadow of Efuse row 1

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0000 0000



TOP:FCFG1:SHDW_REDUNDANT1

Address offset

0x0000 0114

Physical address

0x5000 1114

Instance

FCFG1

Description

Shadow of Efuse row 2

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0000 0000



TOP:FCFG1:SHDW_DIE_ID_0

Address offset

0x0000 0118

Physical address

0x5000 1118

Instance

FCFG1

Description

Shadow of EFUSE:DIE_ID_0

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

ID_31_0

Shadow of EFUSE:DIE_ID_0, ie efuse row number 3

RW

0x0000 0000



TOP:FCFG1:SHDW_DIE_ID_1

Address offset

0x0000 011C

Physical address

0x5000 111C

Instance

FCFG1

Description

Shadow of EFUSE:DIE_ID_1

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

ID_63_32

Shadow of EFUSE:DIE_ID_1, ie efuse row number 4

RW

0x0000 0000



TOP:FCFG1:SHDW_DIE_ID_2

Address offset

0x0000 0120

Physical address

0x5000 1120

Instance

FCFG1

Description

Shadow of EFUSE:DIE_ID_2

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

ID_95_64

Shadow of EFUSE:DIE_ID_2, ie efuse row number 5

RW

0x0000 0000



TOP:FCFG1:SHDW_DIE_ID_3

Address offset

0x0000 0124

Physical address

0x5000 1124

Instance

FCFG1

Description

Shadow of EFUSE:DIE_ID_3

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

ID_127_96

Shadow of EFUSE:DIE_ID_3, ie efuse row number 6

RW

0x0000 0000



TOP:FCFG1:SHDW_SCAN_DATA0

Address offset

0x0000 0128

Physical address

0x5000 1128

Instance

FCFG1

Description

Shadow of EFUSE:SCAN_DATA0

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

ULL_MCU_RAM1_REP

Shadow of EFUSE:SCAN_DATA0.ULL_MCU_RAM1_REP, ie in efuse row number 7

RW

0x0

28:19

ULL_MCU_RAM2_REP

Shadow of EFUSE:SCAN_DATA0.ULL_MCU_RAM2_REP, ie in efuse row number 7

RW

0x000

18:9

ULL_MCU_RAM3_REP

Shadow of EFUSE:SCAN_DATA0.ULL_MCU_RAM3_REP, ie in efuse row number 7

RW

0x000

8:1

ULL_AUX_RAM_REP

Shadow of EFUSE:SCAN_DATA0.ULL_AUX_RAM_REP, ie in efuse row number 7

RW

0x00

0

TAP_DAP_LOCK

Shadow of EFUSE:SCAN_DATA0.TAP_DAP_LOCK, ie in efuse row number 7

RW

0



TOP:FCFG1:SHDW_SCAN_DATA1

Address offset

0x0000 012C

Physical address

0x5000 112C

Instance

FCFG1

Description

Shadow of EFUSE:SCAN_DATA1

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0000

16:7

ULL_MCU_RAM0_REP

Shadow of EFUSE:SCAN_DATA1.ULL_MCU_RAM0_REP, ie in efuse row number 8

RW

0x000

6:0

ULL_MCU_RAM1_REP

Shadow of EFUSE:SCAN_DATA1.ULL_MCU_RAM1_REP, ie in efuse row number 8

RW

0x00



TOP:FCFG1:SHDW_SCAN_DATA2_BOOT

Address offset

0x0000 0130

Physical address

0x5000 1130

Instance

FCFG1

Description

Shadow of EFUSE:SCAN_DATA2_BOOT

Type

RW

Bits

Field Name

Description

Type

Reset

31

FLASH_RDY

Shadow of EFUSE:SCAN_DATA2_BOOT.FLASH_RDY, ie in efuse row number 9

RW

0

30

STANDBY_MODE_SEL_INT

Shadow of EFUSE:SCAN_DATA2_BOOT.STANDBY_MODE_SEL_INT, ie in efuse row number 9

RW

0

29:28

STANDBY_PW_SEL_INT

Shadow of EFUSE:SCAN_DATA2_BOOT.STANDBY_PW_SEL_INT, ie in efuse row number 9

RW

0x0

27

DIS_STANDBY_INT

Shadow of EFUSE:SCAN_DATA2_BOOT.DIS_STANDBY_INT, ie in efuse row number 9

RW

0

26:24

VIN_AT_X_INT

Shadow of EFUSE:SCAN_DATA2_BOOT.VIN_AT_X_INT, ie in efuse row number 9

RW

0x0

23

STANDBY_MODE_SEL_EXT

Shadow of EFUSE:SCAN_DATA2_BOOT.STANDBY_MODE_SEL_EXT, ie in efuse row number 9

RW

0

22:21

STANDBY_PW_SEL_EXT

Shadow of EFUSE:SCAN_DATA2_BOOT.STANDBY_PW_SEL_EXT, ie in efuse row number 9

RW

0x0

20

DIS_STANDBY_EXT

Shadow of EFUSE:SCAN_DATA2_BOOT.DIS_STANDBY_EXT, ie in efuse row number 9

RW

0

19:17

VIN_AT_X_EXT

Shadow of EFUSE:SCAN_DATA2_BOOT.VIN_AT_X_EXT, ie in efuse row number 9

RW

0x0

16:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x00

8:1

CRC

Shadow of EFUSE:SCAN_DATA2_BOOT.CRC, ie in efuse row number 9

RW

0x00

0

TAP_DAP_LOCK_N

Shadow of EFUSE:SCAN_DATA2_BOOT.TAP_DAP_LOCK_N, ie in efuse row number 9

RW

0



TOP:FCFG1:SHDW_BANK_TRIM_BOOT

Address offset

0x0000 0134

Physical address

0x5000 1134

Instance

FCFG1

Description

Shadow of EFUSE:BANK_TRIM_BOOT

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0

29

ROM_BOOT

Shadow of EFUSE:BANK_TRIM_BOOT.ROM_BOOT, ie in efuse row number 10

RW

0

28:25

TRIM3P4

Shadow of EFUSE:BANK_TRIM_BOOT.TRIM3P4, ie in efuse row number 10

RW

0x0

24:21

VCG2P5CT

Shadow of EFUSE:BANK_TRIM_BOOT.VCG2P5CT, ie in efuse row number 10

RW

0x0

20:17

VREADCT

Shadow of EFUSE:BANK_TRIM_BOOT.VREADCT, ie in efuse row number 10

RW

0x0

16:13

TRIM_0P8

Shadow of EFUSE:BANK_TRIM_BOOT.TRIM_0P8, ie in efuse row number 10

RW

0x0

12:0

TRIM

Shadow of EFUSE:BANK_TRIM_BOOT.TRIM_SADLY, EFUSE:BANK_TRIM_BOOT.TRIM_NMOS, and EFUSE:BANK_TRIM_BOOT.TRIM_PMOS, ie in efuse row number 10

RW

0x0000



TOP:FCFG1:SHDW_OSC_BIAS_LDO_TRIM

Address offset

0x0000 0138

Physical address

0x5000 1138

Instance

FCFG1

Description

Shadow of EFUSE:OSC_BIAS_LDO_TRIM

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0

28:27

SET_RCOSC_HF_COARSE_RESISTOR

Shadow of EFUSE:OSC_BIAS_LDO_TRIM.SET_RCOSC_HF_COARSE_RESISTOR, ie in efuse row number 11

RW

0x0

26:23

TRIMMAG

Shadow of EFUSE:OSC_BIAS_LDO_TRIM.TRIMMAG, ie in efuse row number 11

RW

0x0

22:18

TRIMIREF

Shadow of EFUSE:OSC_BIAS_LDO_TRIM.TRIMIREF, ie in efuse row number 11

RW

0x00

17:16

ITRIM_DIG_LDO

Shadow of EFUSE:OSC_BIAS_LDO_TRIM.ITRIM_DIG_LDO, ie in efuse row number 11

RW

0x0

15:12

VTRIM_DIG

Shadow of EFUSE:OSC_BIAS_LDO_TRIM.VTRIM_DIG, ie in efuse row number 11

RW

0x0

11:8

VTRIM_COARSE

Shadow of EFUSE:OSC_BIAS_LDO_TRIM.VTRIM_COARSE, ie in efuse row number 11

RW

0x0

7:0

RCOSCHF_CTRIM

Shadow of EFUSE:OSC_BIAS_LDO_TRIM.RCOSCHF_CTRIM, ie in efuse row number 11

RW

0x00



TOP:FCFG1:SHDW_ANA_TRIM

Address offset

0x0000 013C

Physical address

0x5000 113C

Instance

FCFG1

Description

Shadow of EFUSE:ANA_TRIM

Type

RW

Bits

Field Name

Description

Type

Reset

31:27

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x00

26:25

BOD_BANDGAP_TRIM_CNF

Shadow of EFUSE:ANA_TRIM.BOD_BANDGAP_TRIM_CNF, ie in efuse row number 12

RW

0x0

24

VDDR_ENABLE_PG1

Shadow of EFUSE:ANA_TRIM.VDDR_ENABLE_PG1, ie in efuse row number 12

RW

0

23

VDDR_OK_HYS

Shadow of EFUSE:ANA_TRIM.VDDR_OK_HYS, ie in efuse row number 12

RW

0

22:21

IPTAT_TRIM

Shadow of EFUSE:ANA_TRIM.IPTAT_TRIM, ie in efuse row number 12

RW

0x0

20:16

VDDR_TRIM

Shadow of EFUSE:ANA_TRIM.VDDR_TRIM, ie in efuse row number 12

RW

0x00

15:11

TRIMBOD_INTMODE

Shadow of EFUSE:ANA_TRIM.TRIMBOD_INTMODE, ie in efuse row number 12

RW

0x00

10:6

TRIMBOD_EXTMODE

Shadow of EFUSE:ANA_TRIM.TRIMBOD_EXTMODE, ie in efuse row number 12

RW

0x00

5:0

TRIMTEMP

Shadow of EFUSE:ANA_TRIM.TRIMTEMP, ie in efuse row number 12

RW

0x00



TOP:FCFG1:FLASH_E_P

Address offset

0x0000 0170

Physical address

0x5000 1170

Instance

FCFG1

Description

Flash Erase and Program Setup Time

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

PSU

Program setup time in cycles. Value will be written to FLASH:FSM_PE_OSU.PGM_OSU by the flash device driver when an erase/program operation is initiated.

RW

0x16

23:16

ESU

Erase setup time in cycles. Value will be written to FLASH:FSM_PE_OSU.ERA_OSU by the flash device driver when an erase/program operation is initiated.

RW

0x16

15:8

PVSU

Program verify setup time in cycles. Value will be written to FLASH:FSM_PE_VSU.PGM_VSU by the flash device driver when an erase/program operation is initiated.

RW

0x19

7:0

EVSU

Erase verify setup time in cycles. Value will be written to FLASH:FSM_PE_VSU.ERA_VSU by the flash device driver when an erase/program operation is initiated.

RW

0x19



TOP:FCFG1:FLASH_C_E_P_R

Address offset

0x0000 0174

Physical address

0x5000 1174

Instance

FCFG1

Description

Flash Compaction, Execute, Program and Read

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

RVSU

Repeat verify setup time in cycles. Used for repeated verifies during program and erase. Value will be written to FLASH:FSM_EX_VAL.REP_VSU by the flash device driver when an erase/program operation is initiated.

RW

0x02

23:16

PV_ACCESS

Program verify EXECUTEZ->data valid time in half-microseconds. Value will be converted to number of FCLK cycles by by flash device driver and the converted value is written to FLASH:FSM_EX_VAL.EXE_VALD when an erase/program operation is initiated..

RW

0x05

15:12

A_EXEZ_SETUP

Address->EXECUTEZ setup time in cycles. Value will be written to FLASH:FSM_CMP_VSU.ADD_EXZ by the flash device driver when an erase/program operation is initiated..

RW

0x2

11:0

CVSU

Compaction verify setup time in cycles.

RW

0x000



TOP:FCFG1:FLASH_P_R_PV

Address offset

0x0000 0178

Physical address

0x5000 1178

Instance

FCFG1

Description

Flash Program, Read, and Program Verify

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

PH

Program hold time in half-microseconds after SAFELV goes low. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_P_OH.PGM_OH when an erase/program operation is initiated.

RW

0x09

23:16

RH

Read hold/mode transition time in cycles. Value will be written to the RD_H field bits[7:0] of the FSM_RD_H register in the flash module by the flash device driver when an erase/program operation is initiated.

RW

0x5A

15:8

PVH

Program verify hold time in half-microseconds after SAFELV goes low. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_PE_VH.PGM_VH when an erase/program operation is initiated.

RW

0x01

7:0

PVH2

Program verify row switch time in half-microseconds.

RW

0x00



TOP:FCFG1:FLASH_EH_SEQ

Address offset

0x0000 017C

Physical address

0x5000 117C

Instance

FCFG1

Description

Flash Erase Hold and Sequence

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

EH

Erase hold time in half-microseconds after SAFELV goes low. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_ERA_OH.ERA_OH when an erase/program operation is initiated.

RW

0x58

23:16

SEQ

Pump sequence control.

RW

0x00

15:12

VSTAT

Max number of HCLK cycles allowed for pump brown-out. Value will be written to FLASH:FSM_VSTAT.VSTAT_CNT when an erase/program operation is initiated.

RW

0x3

11:0

SM_FREQUENCY

Max FCLK frequency allowed for program, erase, and verify reads.

RW

0x000



TOP:FCFG1:FLASH_VHV_E

Address offset

0x0000 0180

Physical address

0x5000 1180

Instance

FCFG1

Description

Flash VHV Erase

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

VHV_E_START

Starting VHV-Erase CT for stairstep erase. Value will be written to FLASH:FSM_PRG_PUL.BEG_EC_LEVEL when an erase/program operation is initiated.

RW

0x0004

15:0

VHV_E_STEP_HIGHT

Number of VHV CTs to step after each erase pulse (up to the max). The actual FMC register value should be one less than this since the FMC starts counting from zero. Value will be written to FLASH:FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT when an erase/program operation is initiated.

RW

0x0001



TOP:FCFG1:FLASH_PP

Address offset

0x0000 0184

Physical address

0x5000 1184

Instance

FCFG1

Description

Flash Program Pulse

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

PUMP_SU

Pump read->non-read mode transition time in half-microseconds (mainly for FPES).

RW

0x00

23:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xXX

15:0

MAX_PP

Max program pulse limit per program operation. Value will be written to FLASH:FSM_PRG_PUL.MAX_PRG_PUL when an erase/program operation is initiated.

RW

0x0006



TOP:FCFG1:FLASH_PROG_EP

Address offset

0x0000 0188

Physical address

0x5000 1188

Instance

FCFG1

Description

Flash Program and Erase Pulse

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

MAX_EP

Max erase pulse limit per erase operation. Value will be written to FLASH:FSM_ERA_PUL.MAX_ERA_PUL when an erase/program operation is initiated.

RW

0x0020

15:0

PROGRAM_PW

Program pulse width in half-microseconds. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_PRG_PW.PROG_PUL_WIDTH when a erase/program operation is initiated.

RW

0x000B



TOP:FCFG1:FLASH_ERA_PW

Address offset

0x0000 018C

Physical address

0x5000 118C

Instance

FCFG1

Description

Flash Erase Pulse Width

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

ERASE_PW

Erase pulse width in half-microseconds. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_ERA_PW.FSM_ERA_PW when a erase/program operation is initiated.

RW

0x0000 1740



TOP:FCFG1:FLASH_VHV

Address offset

0x0000 0190

Physical address

0x5000 1190

Instance

FCFG1

Description

Flash VHV

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

27:24

TRIM13_P

Value will be written to FLASH:FVHVCT2.TRIM13_P by the flash device driver when an erase/program operation is initiated.

RW

0xX

23:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

19:16

VHV_P

Value will be written to FLASH:FVHVCT2.VHVCT_P by the flash device driver when an erase/program operation is initiated.

RW

0xX

15:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

11:8

TRIM13_E

Value will be written to FLASH:FVHVCT1.TRIM13_E by the flash device driver when an erase/program operation is initiated.

RW

0xX

7:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

3:0

VHV_E

Value will be written to FLASH:FVHVCT1.VHVCT_E by the flash device driver when an erase/program operation is initiated

RW

0x4



TOP:FCFG1:FLASH_VHV_PV

Address offset

0x0000 0194

Physical address

0x5000 1194

Instance

FCFG1

Description

Flash VHV Program Verify

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

27:24

TRIM13_PV

Value will be written to FLASH:FVHVCT1.TRIM13_PV by the flash device driver when an erase/program operation is initiated.

RW

0xX

23:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

19:16

VHV_PV

Value will be written to FLASH:FVHVCT1.VHVCT_PV by the flash device driver when an erase/program operation is initiated.

RW

0x0

15:8

VCG2P5

Control gate voltage during read, read margin, and erase verify. Value will be written to FLASH:FVNVCT.VCG2P5CT by the flash device driver when an erase/program operation is initiated.

RW

0xXX

7:0

VINH

Inhibit voltage applied to unselected columns during programming.

RW

0x00



TOP:FCFG1:FLASH_V

Address offset

0x0000 0198

Physical address

0x5000 1198

Instance

FCFG1

Description

Flash Voltages

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

VSL_P

Sourceline voltage applied to the selected block during programming. Value will be written to FLASH:FVSLP.VSL_P by the flash device driver when an erase/program operation is initiated.

RW

0xXX

23:16

VWL_P

Wordline voltage applied to the selected half-row during programming. Value will be written to FLASH:FVWLCT.VWLCT_P by the flash device driver when an erase/program operation is initiated.

RW

0xXX

15:8

V_READ

Wordline voltage applied to the selected block during reads and verifies. Value will be written to FLASH:FVREADCT.VREADCT by the flash device driver when an erase/program operation is initiated.

RW

0xXX

7:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xXX



TOP:FCFG1:USER_ID

Address offset

0x0000 0294

Physical address

0x5000 1294

Instance

FCFG1

Description

User Identification
The value of this register will be written to AON_WUC:JTAGUSERCODE by boot FW while in safezone.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

PG_REV

PG revision number:

RW

0xX

27:26

VER

Version number.

0x0: Bits [25:12] of this register has the stated meaning.

Any other setting indicate a different encoding of these bits.

RW

0xX

25

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

X

24

BAW

0: No BAW installed
1: Device uses BAW resonator

RW

X

23

ANT

0: Does not support ANT
1: Supports ANT

RW

X

22:19

SEQUENCE

Sequence.

Used to differentiate between marketing/orderable product where other fields of USER_ID is the same (temp range, flash size, voltage range etc)

RW

0xX

18:16

PKG

Package type.

0x0: 4x4mm
0x1: 5x5mm
0x2: 7x7mm

Others values are reserved for future use.

RW

0xX

15:12

PROTOCOL

Protocols supported.

0x1: BLE
0x2: RF4CE
0x4: Zigbee/6lowpan
0x8: Proprietary

More than one protocol can be supported on same device - values above are then combined.

RW

0xX

11:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xXXX



TOP:FCFG1:FLASH_OTP_DATA1

Address offset

0x0000 02A8

Physical address

0x5000 12A8

Instance

FCFG1

Description

Flash OTP Data 1

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

SAMPLE_PERIODE

Value will be written to FLASH:SAMPLE_PERIOD.SAMPLE_PERIOD by boot FW while in safezone.

RW

0x00 03E7

7:0

WAITSTATES

Value will be written to FLASH:WAITSTATES.WAITSTATES by boot FW while in safezone.

RW

0x03



TOP:FCFG1:FLASH_OTP_DATA2

Address offset

0x0000 02AC

Physical address

0x5000 12AC

Instance

FCFG1

Description

Flash OTP Data 2

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

PRE_SAMPLE

Value will be written to FLASH:PRE_SAMPLE.PRE_SAMPLE by boot FW while in safezone.

RW

0x2F

23:16

SAMHOLD_SA

Value will be written to FLASH:SAMHOLD_SA.SAMHOLD_SA by boot FW while in safezone.

RW

0x2F

15:8

SAMHOLD_SU

Value will be written to FLASH:SAMHOLD_SU.SAMHOLD_SU by boot FW while in safezone.

RW

0x2F

7:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

3

ENABLE_SWINTF

Value will be written to FLASH:CFG.ENABLE_SWINTF by boot FW while in safezone.

RW

0

2

PROTECTCFG_N

Value is inverted and written to FLASH:CFG.PROTECTCFG by boot FW while in safezone.
0: The FCFG1 area given by FLASH:PCFGSTART and FLASH:PCFGEND will be readprotected.
1: No area within the FCFG1 will be readprotected.

RW

0

1:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3



TOP:FCFG1:FLASH_OTP_DATA3

Address offset

0x0000 02B0

Physical address

0x5000 12B0

Instance

FCFG1

Description

Flash OTP Data 3

Type

RW

Bits

Field Name

Description

Type

Reset

31:23

EC_STEP_SIZE

Value will be written to FLASH:FSM_STEP_SIZE.EC_STEP_SIZE by the flash device driver when a erase/program operation is initiated.

RW

0x006

22

DO_PRECOND

Value will be written to FLASH:FSM_ST_MACHINE.DO_PRECOND by the flash device driver when a erase/program operation is initiated.

Note that during a Total Erase operation the flash bank will always be erased with Precondition enabled independent of the value of this FCFG1 bit field.

RW

0

21:18

MAX_EC_LEVEL

Value will be written to FLASH:FSM_ERA_PUL.MAX_EC_LEVEL by the flash device driver when a erase/program operation is initiated.

RW

0x4

17:16

TRIM_1P7

Value will be written to FLASH:FSEQPMP.TRIM_1P7 by the flash device driver when a erase/program operation is initiated.

RW

0x0

15:8

FLASH_SIZE

Value will be written to FLASH:FLASH_SIZE.SECTORS by the boot FW while in safe zone.

This register will be write protected by the boot FW by setting FLASH:CFG.CONFIGURED.

RW

0xXX

7:0

WAIT_SYSCODE

Value will be written to FLASH:WAIT_SYSCODE.WAIT_SYSCODE by boot FW code while in safezone.

RW

0x03



TOP:FCFG1:MAC_BLE_0

Address offset

0x0000 02E8

Physical address

0x5000 12E8

Instance

FCFG1

Description

MAC BLE Address 0

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

ADDR_0_31

The first 32-bits of the 64-bit MAC BLE address

RW

0xXXXX XXXX



TOP:FCFG1:MAC_BLE_1

Address offset

0x0000 02EC

Physical address

0x5000 12EC

Instance

FCFG1

Description

MAC BLE Address 1

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

ADDR_32_63

The last 32-bits of the 64-bit MAC BLE address

RW

0xXXXX XXXX



TOP:FCFG1:MAC_15_4_0

Address offset

0x0000 02F0

Physical address

0x5000 12F0

Instance

FCFG1

Description

MAC IEEE 802.15.4 Address 0

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

ADDR_0_31

The first 32-bits of the 64-bit MAC 15.4 address

RW

0xXXXX XXXX



TOP:FCFG1:MAC_15_4_1

Address offset

0x0000 02F4

Physical address

0x5000 12F4

Instance

FCFG1

Description

MAC IEEE 802.15.4 Address 1

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

ADDR_32_63

The last 32-bits of the 64-bit MAC 15.4 address

RW

0xXXXX XXXX



TOP:FCFG1:FLASH_OTP_DATA4

Address offset

0x0000 0308

Physical address

0x5000 1308

Instance

FCFG1

Description

Flash OTP Data 4

Type

RW

Bits

Field Name

Description

Type

Reset

31

STANDBY_MODE_SEL_INT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write operation is initiated.

RW

0

30:29

STANDBY_PW_SEL_INT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write operation is initiated.

RW

0x0

28

DIS_STANDBY_INT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation is initiated.

RW

1

27

DIS_IDLE_INT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is initiated.

RW

1

26:24

VIN_AT_X_INT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write operation is initiated.

RW

0x0

23

STANDBY_MODE_SEL_EXT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write operation is initiated.

RW

0

22:21

STANDBY_PW_SEL_EXT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write operation is initiated.

RW

0x0

20

DIS_STANDBY_EXT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation is initiated.

RW

1

19

DIS_IDLE_EXT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is initiated.

RW

1

18:16

VIN_AT_X_EXT_WRT

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write operation is initiated.

RW

0x0

15

STANDBY_MODE_SEL_INT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0

14:13

STANDBY_PW_SEL_INT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0x0

12

DIS_STANDBY_INT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0

11

DIS_IDLE_INT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0

10:8

VIN_AT_X_INT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0x0

7

STANDBY_MODE_SEL_EXT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0

6:5

STANDBY_PW_SEL_EXT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0x0

4

DIS_STANDBY_EXT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0

3

DIS_IDLE_EXT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0

2:0

VIN_AT_X_EXT_RD

If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation.

RW

0x0



TOP:FCFG1:MISC_TRIM

Address offset

0x0000 030C

Physical address

0x5000 130C

Instance

FCFG1

Description

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xFF FFFF

7:0

TEMPVSLOPE

Signed byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits.

RW

0x33



TOP:FCFG1:RCOSC_HF_TEMPCOMP

Address offset

0x0000 0310

Physical address

0x5000 1310

Instance

FCFG1

Description

RCOSC HF Temperature Compensation

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

FINE_RESISTOR

Change in FINE_RESISTOR trim

RW

0x00

23:16

CTRIM

Change in CTRIM trim

RW

0x00

15:8

CTRIMFRACT_QUAD

Temp compensation quadratic CTRIMFRACT

RW

0x00

7:0

CTRIMFRACT_SLOPE

Number of CTRIMFRACT codes per 20 degrees C from default temperature

RW

0x03



TOP:FCFG1:TRIM_CAL_REVISION

Address offset

0x0000 0314

Physical address

0x5000 1314

Instance

FCFG1

Description

Production Test Trim and Calibration Revision

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

FT1

The revision of the ATE Trim&Calc document used in FT1 in production

RW

0xXXXX

15:0

MP1

The revision of the ATE Trim&Calc document used in MP1 in production

RW

0xXXXX



TOP:FCFG1:ICEPICK_DEVICE_ID

Address offset

0x0000 0318

Physical address

0x5000 1318

Instance

FCFG1

Description

IcePick Device Identification
This register shall hold a value that equals the value of the IcePick DEVICE_ID register.

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

PG_REV

Field used to distinguish between different silicon revisions of the device.

RW

0x8

27:12

WAFER_ID

Field used to identify silicon die.

RW

0xB99A

11:0

MANUFACTURER_ID

Manufacturer code.

0x02F: Texas Instruments

RW

0x02F



TOP:FCFG1:FCFG1_REVISION

Address offset

0x0000 031C

Physical address

0x5000 131C

Instance

FCFG1

Description

Factory Configuration (FCFG1) Revision

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

REV

The revision number of the FCFG1 layout. This value will be read by application SW in order to determine which FCFG1 parameters that have valid values. This revision number must be incremented by 1 before any devices are to be produced if the FCFG1 layout has changed since the previous production of devices.

RW

0x0000 0000



TOP:FCFG1:MISC_OTP_DATA

Address offset

0x0000 0320

Physical address

0x5000 1320

Instance

FCFG1

Description

Misc OTP Data

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

RCOSC_HF_ITUNE

Trim value that migth become into use for cc26xx PG2.2 and cc13xx PG2.0. Trim value for DDI_0_OSC:RCOSCHFCTL.RCOSCHF_ITUNE_TRIM.

RW

0xF

27:20

RCOSC_HF_CRIM

Trim value that migth become into use for cc26xx PG2.2 and cc13xx PG2.0. Trim value for DDI_0_OSC:RCOSCHFCTL.RCOSCHF_CTRIM.

RW

0xFF

19:15

PER_M

Trim value for AON_WUC:OSCCFG.PER_M.

RW

0x01

14:12

PER_E

Trim value for AON_WUC:OSCCFG.PER_E.

RW

0x4

11:8

PO_TAIL_RES_TRIM

Trim value for DLO_DTX:PLLCTL1.PO_TAIL_RES_TRIM.

RW

0x5

7:0

TEST_PROGRAM_REV

The revision of the test program used in the production process when FCFG1 was programmed.

RW

0xXX



TOP:FCFG1:IOCONF

Address offset

0x0000 0344

Physical address

0x5000 1344

Instance

FCFG1

Description

IO Configuration

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xFF FFFF

7

PADLOCK_N

This value is read by boot FW while in safezone and it determines if the pad configuration will be locked or not.

0: Pad configuration is locked by setting IOC:CFG.LOCK = 1
1: Pad configuration is not locked.

RW

1

6:0

GPIO_CNT

This value is written to IOC:CFG.GPIO_CNT by boot FW while in safezone.

RW

0xXX



TOP:FCFG1:CONFIG_IF_ADC

Address offset

0x0000 034C

Physical address

0x5000 134C

Instance

FCFG1

Description

Configuration of IF_ADC

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

FF2ADJ

Trim value for ADI_0_RF:IFADCLFCFG1.FF2ADJ.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

27:24

FF3ADJ

Trim value for ADI_0_RF:IFADCLFCFG1.FF3ADJ.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

23:20

INT3ADJ

Trim value for ADI_0_RF:IFADCLFCFG0.INT3ADJ.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

19:16

FF1ADJ

Trim value for ADI_0_RF:IFADCLFCFG0.FF1ADJ.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

15:14

AAFCAP

Trim value for ADI_0_RF:IFADCCTL0.AAFCAP.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

13:10

INT2ADJ

Trim value for ADI_0_RF:IFADCCTL0.INT2ADJ.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

9:5

IFDIGLDO_TRIM_OUTPUT

Trim value for ADI_0_RF:IFDLDO2.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0xXX

4:0

IFANALDO_TRIM_OUTPUT

Trim value for ADI_0_RF:IFALDO2.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0xXX



TOP:FCFG1:CONFIG_OSC_TOP

Address offset

0x0000 0350

Physical address

0x5000 1350

Instance

FCFG1

Description

Configuration of OSC

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3

29:26

XOSC_HF_ROW_Q12

Trim value for DDI_0_OSC:ANABYPASSVAL1.XOSC_HF_ROW_Q12.

RW

0x0

25:10

XOSC_HF_COLUMN_Q12

Trim value for DDI_0_OSC:ANABYPASSVAL1.XOSC_HF_COLUMN_Q12.

RW

0x0000

9:2

RCOSCLF_CTUNE_TRIM

Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_CTUNE_TRIM.

RW

0xXX

1:0

RCOSCLF_RTUNE_TRIM

Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_RTUNE_TRIM.

RW

0x0



TOP:FCFG1:CONFIG_RF_FRONTEND

Address offset

0x0000 0354

Physical address

0x5000 1354

Instance

FCFG1

Description

Configuration of RF Frontend in Divide-by-2 Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

IFAMP_IB

Trim value for ADI_0_RF:IFAMPCTL3.IB.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

27:24

LNA_IB

Trim value for [ANATOP_MMAP::ADI_0_RF:LNACTL2:IB].
Value is read by RF Core ROM FW during RF Core initialization.

RW

0xX

23:19

IFAMP_TRIM

Trim value for ADI_0_RF:IFAMPCTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00

18:14

CTL_PA0_TRIM

Trim value for ADI_0_RF:PACTL0.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0xXX

13

PATRIMCOMPLETE_N

Status of PA trim
0: Trimmed
1: Not trimmed

RW

X

12:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3F

6:0

RFLDO_TRIM_OUTPUT

Trim value for ADI_0_RF:RFLDO1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0xXX



TOP:FCFG1:CONFIG_SYNTH

Address offset

0x0000 0358

Physical address

0x5000 1358

Instance

FCFG1

Description

Configuration of Synthesizer in Divide-by-2 Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xF

27:12

RFC_MDM_DEMIQMC0

Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR
Value is read by RF Core ROM FW during RF Core initialization only on cc13xx.

RW

0x8000

11:6

LDOVCO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0xXX

5:0

SLDO_TRIM_OUTPUT

Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0xXX



TOP:FCFG1:SOC_ADC_ABS_GAIN

Address offset

0x0000 035C

Physical address

0x5000 135C

Instance

FCFG1

Description

AUX_ADC Gain in Absolute Reference Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

SOC_ADC_ABS_GAIN_TEMP2

SOC_ADC gain in absolute reference mode at temperature 2 (85C?). Calculated in production test.

RW

0xXXXX

15:0

SOC_ADC_ABS_GAIN_TEMP1

SOC_ADC gain in absolute reference mode at temperature 1 (25C?). Calculated in production test..

RW

0xXXXX



TOP:FCFG1:SOC_ADC_REL_GAIN

Address offset

0x0000 0360

Physical address

0x5000 1360

Instance

FCFG1

Description

AUX_ADC Gain in Relative Reference Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

SOC_ADC_REL_GAIN_TEMP2

SOC_ADC gain in relative reference mode at temperature 2 (85C?). Calculated in production test..

RW

0xXXXX

15:0

SOC_ADC_REL_GAIN_TEMP1

SOC_ADC gain in relative reference mode at temperature 1 (25C?). Calculated in production test..

RW

0xXXXX



TOP:FCFG1:SOC_ADC_EXT_GAIN

Address offset

0x0000 0364

Physical address

0x5000 1364

Instance

FCFG1

Description

AUX_ADC Gain in External Reference Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

SOC_ADC_EXT_GAIN_TEMP2

SOC_ADC gain in external reference mode at temperature 2 (85C?). Calculated in production test..

RW

0xXXXX

15:0

SOC_ADC_EXT_GAIN_TEMP1

SOC_ADC gain in external reference mode at temperature 1 (25C?). Calculated in production test..

RW

0xXXXX



TOP:FCFG1:SOC_ADC_OFFSET_INT

Address offset

0x0000 0368

Physical address

0x5000 1368

Instance

FCFG1

Description

AUX_ADC Temperature Offsets in Absolute Reference Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

SOC_ADC_REL_OFFSET_TEMP2

SOC_ADC offset in relative reference mode at temperature 2 (85C?). Signed 8-bit number. Calculated in production test..

RW

0xXX

23:16

SOC_ADC_REL_OFFSET_TEMP1

SOC_ADC offset in relative reference mode at temperature 1 (25C?). Signed 8-bit number. Calculated in production test..

RW

0xXX

15:8

SOC_ADC_ABS_OFFSET_TEMP2

SOC_ADC offset in absolute reference mode at temperature 2 (85C?). Signed 8-bit number. Calculated in production test..

RW

0xXX

7:0

SOC_ADC_ABS_OFFSET_TEMP1

SOC_ADC offset in absolute reference mode at temperature 1 (25C?). Signed 8-bit number. Calculated in production test..

RW

0xXX



TOP:FCFG1:SOC_ADC_REF_TRIM_AND_OFFSET_EXT

Address offset

0x0000 036C

Physical address

0x5000 136C

Instance

FCFG1

Description

AUX_ADC Reference Trim and Offset for External Reference Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

SOC_ADC_EXT_OFFSET_TEMP2

SOC_ADC offset in external reference mode at temperature 2 (85C?). Signed 8-bit number. Calculated in production test..

RW

0xXX

23:16

SOC_ADC_EXT_OFFSET_TEMP1

SOC_ADC offset in external reference mode at temperature 1 (25C?). Signed 8-bit number. Calculated in production test..

RW

0xXX

15:14

TEST_TEMP_INDEX2

Index of TEST_TEMPS that was used to when the _TEMP2 fields for SOC_ADC were written.

0: TEST_TEMPS.TEST_TEMP1
1: TEST_TEMPS.TEST_TEMP2
2: TEST_TEMPS.TEST_TEMP3
3: TEST_TEMPS.TEST_TEMP4

RW

0x0

13:8

SOC_ADC_REF_VOLTAGE_TRIM_TEMP2

Value to write in ADI_4_AUX:ADCREF1.VTRIM at temperature 2 (85C?).

RW

0xXX

7:6

TEST_TEMP_INDEX1

Index of TEST_TEMPS that was used to when the _TEMP1 fields for SOC_ADC were written. This should always be room temp.

0: TEST_TEMPS.TEST_TEMP1
1: TEST_TEMPS.TEST_TEMP2
2: TEST_TEMPS.TEST_TEMP3
3: TEST_TEMPS.TEST_TEMP4

RW

0x0

5:0

SOC_ADC_REF_VOLTAGE_TRIM_TEMP1

Value to write in ADI_4_AUX:ADCREF1.VTRIM at temperature 1 (25C?).

RW

0xXX



TOP:FCFG1:AMPCOMP_TH1

Address offset

0x0000 0370

Physical address

0x5000 1370

Instance

FCFG1

Description

Ampltude Compensation Threashold 1

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0xFF

23:18

HPMRAMP3_LTH

HPM Ramp3 low amplitude threshhold.
In HPM_RAMP3, if amp > HPMRAMP3_LTH && amp < HPMRAMP3_HTH then move on HPM_UPDATE.

RW

0x1A

17:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3

15:10

HPMRAMP3_HTH

In HPM_RAMP3, if amp > HPMRAMP3_LTH && amp < HPMRAMP3_HTH then move on to HPM_UPDATE.

RW

0x1D

9:6

IBIASCAP_LPTOHP_OL_CNT

During XOSC mode transition, CAP trim and IBIAS trim should be modified by this amount. IBIAS and CAP trim open loop count. CAP_REM is remainder of the CAP that is left to reach the final cap value.

RW

0xA

5:0

HPMRAMP1_TH

During XOSC mode transition, CAP trim and IBIAS trim should be modified by this amount. IBIAS and CAP trim open loop count. CAP_REM is remainder of the CAP that is left to reach the final cap value.

RW

0x24



TOP:FCFG1:AMPCOMP_TH2

Address offset

0x0000 0374

Physical address

0x5000 1374

Instance

FCFG1

Description

Ampltude Compensation Threashold 2

Type

RW

Bits

Field Name

Description

Type

Reset

31:26

LPMUPDATE_LTH

LPM Update low amplitude threshhold.
if amp > LPMUPDATE_LTH && amp < LPMUPDATE_HTH then move on.

RW

0x1A

25:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3

23:18

LPMUPDATE_HTM

LPM Update high amplitude threshhold.
if amp > LPMUPDATE_LTH && amp < LPMUPDATE_HTH then move on.

RW

0x22

17:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3

15:10

ADC_COMP_AMPTH_LPM

When ADC is forced in comparator mode, this value is used as OPAMP's threshold during LPM_UPDATE mode. Actual amplitude is compared against this threshhold to generate 1-bit adc_threshholdmet indicator output.

RW

0x00

9:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3

7:2

ADC_COMP_AMPTH_HPM

When ADC is forced in comparator mode, this value is used as OPAMP's threshold during HPM_UPDATE mode. Actual amplitude is compared against this threshhold to generate 1-bit adc_threshholdmet indicator output.

RW

0x00

1:0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3



TOP:FCFG1:AMPCOMP_CTRL1

Address offset

0x0000 0378

Physical address

0x5000 1378

Instance

FCFG1

Description

Amplitude Compensation Control

Type

RW

Bits

Field Name

Description

Type

Reset

31

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

1

30

AMPCOMP_REQ_MODE

Trim value for DDI_0_OSC:AMPCOMPCTL.AMPCOMP_REQ_MODE.

RW

1

29:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3F

23:20

IBIAS_OFFSET

Offset values of XOSC IBIAS trim. IBIAS trim value would always be greater than or equal to this offset in both HPM and LPM.

RW

0x7

19:16

IBIAS_INIT

Initial value of XOSC IBIAS trim. During ramping up, IBIAS is set to IBIAS_OFFSET + IBIAS_INIT.

RW

0x1

15:8

LPM_IBIAS_WAIT_CNT_FINAL

FSM waits for ddi_lpm_ibias_wait_cnt_final clock cycles in IDAC_DECREMENT_WITH_MEASURE states in order to compensate slow response of the xtal. 8-bits.

RW

0x3F

7:4

CAP_STEP

Step size of XOSC CAP trim (both Q1 and Q2) during XOSC mode transition. Can vary from 6 to 12. Other values are possible but not valid.

RW

0x2

3:0

IBIASCAP_HPTOLP_OL_CNT

During HPM to LPM transition, CAP trim and IBIAS trim should be modified by this amount. IBIAS and CAP trim open loop count. CAP_REM is remainder of the CAP that is left to reach the final cap value. Do not need to program this.
CAP_TRIM = CAP_INIT - CAP_STEP*IBIASCAP_HPTOLP_OL_CNT - CAP_REM;
IBIAS_TRIM = IBIAS_INIT - 1*IBIASCAP_HPTOLP_OL_CNT;
Here, cap_init is decimal conversion of cap_init_col and cap_init_row.

RW

0x7



TOP:FCFG1:ANABYPASS_VALUE2

Address offset

0x0000 037C

Physical address

0x5000 137C

Instance

FCFG1

Description

Analog Bypass Value for OSC

Type

RW

Bits

Field Name

Description

Type

Reset

31:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3 FFFF

13:0

XOSC_HF_IBIASTHERM

Value of xosc_hf_ibiastherm when oscdig is bypassed.

RW

0x03FF



TOP:FCFG1:CONFIG_MISC_ADC

Address offset

0x0000 0380

Physical address

0x5000 1380

Instance

FCFG1

Description

Configuration of IFADC in Divide-by-2 Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3FFF

17

RSSITRIMCOMPLETE_N

Status of RSSI trim
0: Trimmed
1: Not trimmed

RW

X

16:9

RSSI_OFFSET

Value for RSSI measured in production test.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0xXX

8:6

QUANTCTLTHRES

Trim value for ADI_0_RF:IFADCQUANT0.TH.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x0

5:0

DACTRIM

Trim value for ADI_0_RF:IFADCDAC.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.

RW

0x00



TOP:FCFG1:TEST_TEMPS

Address offset

0x0000 0384

Physical address

0x5000 1384

Instance

FCFG1

Description

Test Temperatures

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

TEST_TEMP4

Temperature for the 4. test insertion.
Valid values -40C to 125C. 0xFF means not (yet) run.

RW

0x00

23:16

TEST_TEMP3

Temperature for the 3. test insertion.
Valid values -40C to 125C. 0xFF means not (yet) run.

RW

0x00

15:8

TEST_TEMP2

Temperature for the 2. test insertion.
Valid values -40C to 125C. 0xFF means not (yet) run.

RW

0x00

7:0

TEST_TEMP1

Temperature for the 1. test insertion.
Valid values -40C to 125C. 0xFF means not (yet) run.

RW

0x00



TOP:FCFG1:VOLT_TRIM

Address offset

0x0000 0388

Physical address

0x5000 1388

Instance

FCFG1

Description

Voltage Trim

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7

28:24

VDDR_TRIM_HH

TBD: Trim value for 1.94V VDDR found in production test (for CC13xx high PA output power only).

RW

0x1F

23:21

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7

20:16

VDDR_TRIM_H

Trim value for 1.85V VDDR found in production test (for external VDDR load mode)

RW

0x1F

15:13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7

12:8

VDDR_TRIM_SLEEP_H

Trim value for 1.75V VDDR recharge target found in production test (for external VDDR load mode).

RW

0x1F

7:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7

4:0

TRIMBOD_H

Trim value for 2.0V VDDS BOD target found in production test.
To be applied to ADI_3_REFSYS:REFSYSCTL1.TRIM_VDDS_BOD when 2.0V BOD is needed?

RW

0xXX



TOP:FCFG1:OSC_CONF

Address offset

0x0000 038C

Physical address

0x5000 138C

Instance

FCFG1

Description

OSC Configuration

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x3

29

ADC_SH_VBUF_EN

Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN.

RW

1

28

ADC_SH_MODE_EN

Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN.

RW

1

27

ATESTLF_RCOSCLF_IBIAS_TRIM

Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM.

RW

0

26:25

XOSCLF_REGULATOR_TRIM

Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM.

RW

0x0

24:21

XOSCLF_CMIRRWR_RATIO

Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO.

RW

0x0

20:19

XOSC_HF_FAST_START

Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START.
This trim value is not relevant for PG1 devices.

RW

0x0

18

XOSC_OPTION

0: XOSC_HF unavailable (may not be bonded out)
1: XOSC_HF available (default)

RW

X

17

BAW_OPTION

0: BAW available
1: BAW unavailable (default)

RW

X

16

BAW_FREQ

0: 840MHz
1: 2520MHz (default)

RW

X

15:0

BAW_TRIM

(TBD contents for now, trimmed in production test for BAW devices

RW

0xXXXX



TOP:FCFG1:FREQ_OFFSET

Address offset

0x0000 0390

Physical address

0x5000 1390

Instance

FCFG1

Description

Frequency Offset

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

BAW_COMP_P0

Signed 16-bit value, representing the frequency offset at 27 degrees C.

RW

0xXXXX

15:8

BAW_COMP_P1

Signed 8-bit value, representing the first order frequency offset slope.

RW

0xXX

7:0

BAW_COMP_P2

Signed 8-bit value, representing the second order frequency offset slope. The actual frequency of the clock would be defined as 48MHz*(1+d), where = P0*2^(-22) + P1*(T-27)*2^(-25) + P2*(T-27)^2*2^(-31).

RW

0xXX



TOP:FCFG1:CAP_TRIM

Address offset

0x0000 0394

Physical address

0x5000 1394

Instance

FCFG1

Description

Capasitor Trim

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

FLUX_CAP_0P28_TRIM

Reserved storage of measurement value on 0.28um pitch FLUX CAP (measured in production test)

RW

0xFFFF

15:0

FLUX_CAP_0P4_TRIM

Reserved storage of measurement value on 0.4um pitch FLUX CAP (measured in production test)

RW

0xFFFF



TOP:FCFG1:MISC_OTP_DATA_1

Address offset

0x0000 0398

Physical address

0x5000 1398

Instance

FCFG1

Description

Misc OSC Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x7

28:27

PEAK_DET_ITRIM

Trim value for DDI_0_OSC:XOSCHFCTL.PEAK_DET_ITRIM.

RW

0x0

26:24

HP_BUF_ITRIM

Trim value for DDI_0_OSC:XOSCHFCTL.HP_BUF_ITRIM.

RW

0x0

23:22

LP_BUF_ITRIM

Trim value for DDI_0_OSC:XOSCHFCTL.LP_BUF_ITRIM.

RW

0x0

21:20

DBLR_LOOP_FILTER_RESET_VOLTAGE

Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.DBLR_LOOP_FILTER_RESET_VOLTAGE.

RW

0x0

19:10

HPM_IBIAS_WAIT_CNT

Trim value for DDI_0_OSC:RADCEXTCFG.HPM_IBIAS_WAIT_CNT.

RW

0x100

9:4

LPM_IBIAS_WAIT_CNT

Trim value for DDI_0_OSC:RADCEXTCFG.LPM_IBIAS_WAIT_CNT.

RW

0x3F

3:0

IDAC_STEP

Trim value for DDI_0_OSC:RADCEXTCFG.IDAC_STEP.

RW

0x4



TOP:FCFG1:PWD_CURR_20C

Address offset

0x0000 039C

Physical address

0x5000 139C

Instance

FCFG1

Description

Power Down Current Control 20C

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

RW

0xFF

23:16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

RW

0xFF

15:8

DELTA_XOSC_LPM

Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode

RW

0xFF

7:0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

RW

0xFF



TOP:FCFG1:PWD_CURR_35C

Address offset

0x0000 03A0

Physical address

0x5000 13A0

Instance

FCFG1

Description

Power Down Current Control 35C

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

RW

0xFF

23:16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

RW

0xFF

15:8

DELTA_XOSC_LPM

Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode

RW

0xFF

7:0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

RW

0xFF



TOP:FCFG1:PWD_CURR_50C

Address offset

0x0000 03A4

Physical address

0x5000 13A4

Instance

FCFG1

Description

Power Down Current Control 50C

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

RW

0xFF

23:16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

RW

0xFF

15:8

DELTA_XOSC_LPM

Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode

RW

0xFF

7:0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

RW

0xFF



TOP:FCFG1:PWD_CURR_65C

Address offset

0x0000 03A8

Physical address

0x5000 13A8

Instance

FCFG1

Description

Power Down Current Control 65C

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

RW

0xFF

23:16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

RW

0xFF

15:8

DELTA_XOSC_LPM

Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode

RW

0xFF

7:0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

RW

0xFF



TOP:FCFG1:PWD_CURR_80C

Address offset

0x0000 03AC

Physical address

0x5000 13AC

Instance

FCFG1

Description

Power Down Current Control 80C

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

RW

0xFF

23:16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

RW

0xFF

15:8

DELTA_XOSC_LPM

Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode

RW

0xFF

7:0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

RW

0xFF



TOP:FCFG1:PWD_CURR_95C

Address offset

0x0000 03B0

Physical address

0x5000 13B0

Instance

FCFG1

Description

Power Down Current Control 95C

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

RW

0xFF

23:16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

RW

0xFF

15:8

DELTA_XOSC_LPM

Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode

RW

0xFF

7:0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

RW

0xFF



TOP:FCFG1:PWD_CURR_110C

Address offset

0x0000 03B4

Physical address

0x5000 13B4

Instance

FCFG1

Description

Power Down Current Control 110C

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

RW

0xFF

23:16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

RW

0xFF

15:8

DELTA_XOSC_LPM

Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode

RW

0xFF

7:0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

RW

0xFF



TOP:FCFG1:PWD_CURR_125C

Address offset

0x0000 03B8

Physical address

0x5000 13B8

Instance

FCFG1

Description

Power Down Current Control 125C

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

DELTA_CACHE_REF

Additional maximum current, in units of 1uA, with cache retention

RW

0xFF

23:16

DELTA_RFMEM_RET

Additional maximum current, in 1uA units, with RF memory retention

RW

0xFF

15:8

DELTA_XOSC_LPM

Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode

RW

0xFF

7:0

BASELINE

Worst-case baseline maximum powerdown current, in units of 0.5uA

RW

0xFF