SPIS

Instance: SPIS
Component: SPIS
Base address: 0x40085000

 

SPI Slave block in switchable power domain with interface to SPI block in always-on power domain

 

TOP:SPIS Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

GPFLAGS

RW

32

0x0000 0000

0x0000 0000

0x4008 5000

GPFLAGSSET

WO

32

0x0000 0000

0x0000 0004

0x4008 5004

GPFLAGSMASK

RW

32

0x0000 0000

0x0000 0008

0x4008 5008

CFG

RW

32

0x0000 0000

0x0000 000C

0x4008 500C

TXFFLAGSCLRN

RW

32

0x0000 000E

0x0000 0010

0x4008 5010

TXFFLAGSSET

WO

32

0x0000 0000

0x0000 0014

0x4008 5014

TXFFLAGSMASK

RW

32

0x0000 0000

0x0000 0018

0x4008 5018

TXSTAT

RO

32

0x0000 000E

0x0000 001C

0x4008 501C

TXFEVSRC

RW

32

0x0000 0007

0x0000 0020

0x4008 5020

TXFTHR

RW

32

0x0000 0000

0x0000 0024

0x4008 5024

TXFPUSH

WO

32

0x0000 0000

0x0000 0028

0x4008 5028

TXFFLUSH

WO

32

0x0000 0000

0x0000 002C

0x4008 502C

TXFMEMRDPOS

RO

32

0x0000 0000

0x0000 0040

0x4008 5040

TXMEMWRPOS

RO

32

0x0000 0000

0x0000 0044

0x4008 5044

TXFCNT

RO

32

0x0000 0000

0x0000 0048

0x4008 5048

RXFFLAGSCLRN

RW

32

0x0000 000E

0x0000 004C

0x4008 504C

RXFFLAGSSET

WO

32

0x0000 0000

0x0000 0050

0x4008 5050

RXFFLAGSMASK

RW

32

0x0000 0000

0x0000 0054

0x4008 5054

RXFSTAT

RO

32

0x0000 000E

0x0000 0058

0x4008 5058

RXFEVSRC

RW

32

0x0000 0007

0x0000 005C

0x4008 505C

RXFTHR

RW

32

0x0000 0000

0x0000 0060

0x4008 5060

RXFPOP

RO

32

0x0000 0000

0x0000 0064

0x4008 5064

RXFFLUSH

WO

32

0x0000 0000

0x0000 0068

0x4008 5068

RXFMEMRDPOS

RO

32

0x0000 0000

0x0000 0080

0x4008 5080

RXFMEMWRPOS

RO

32

0x0000 0000

0x0000 0084

0x4008 5084

RXCNT

RO

32

0x0000 0000

0x0000 0088

0x4008 5088

TXFMEM__0-TXFMEM__15

RO

32

0x0000 0000

0x0000 0400-0x0000 043C

0x4008 5400- 0x4008 543C

RXFMEM__0-RXFMEM__15

RO

32

0x0000 0000

0x0000 0800-0x0000 083C

0x4008 5800- 0x4008 583C

TOP:SPIS Register Descriptions

TOP:SPIS:GPFLAGS

Address offset

0x0000 0000

Physical address

0x4008 5000

Instance

SPIS

Description

SPI Slave General Purpose Flags

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3

BYTE_DONE

0

RW

0

2

BYTE_RX_OVF

Parallel receive data overflow event.

0: No overflow condition is detected.
1: An overflow condition of sampled SDI pin data is detected. The SPI Slave is able to buffer one byte of data sampled on the SDI pin.

RW

0

1

BYTE_ABORT

Incomplete SPI transfer event.

0: No SPI incomplete transfer detected.
1: Chip select has been de-asserted during a byte transfer.

RW

0

0

CS

Chip select event.

0: Chip select has not been asserted.
1: Chip select assertion is detected.

RW

0



TOP:SPIS:GPFLAGSSET

Address offset

0x0000 0004

Physical address

0x4008 5004

Instance

SPIS

Description

SPI Slave General Purpose Flags Set
This register is intended for debug only.

Type

WO

Bits

Field Name

Description

Type

Reset

31:4

RESERVED4

Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

WO

0x000 0000

3

BYTE_DONE

0: No effect.
1: Set GPFLAGS.BYTE_DONE high

WO

0

2

BYTE_RX_OVF

0: No effect.
1: Set GPFLAGS.BYTE_RX_OVF high

WO

0

1

BYTE_ABORT

0: No effect.
1: Set GPFLAGS.BYTE_ABORT high

WO

0

0

CS

0: No effect.
1: Set GPFLAGS.CS high

WO

0



TOP:SPIS:GPFLAGSMASK

Address offset

0x0000 0008

Physical address

0x4008 5008

Instance

SPIS

Description

SPI Slave General Purpose Flags Mask

Type

RW

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

5

RX_DMA_DONE

Enable bit for DMA done, DMA channel with RX FIFO as source.

0: Not an event source.
1: Enabled as an event source.

RW

0

4

TX_DMA_DONE

0

RW

0

3

BYTE_DONE

Enable bit for GPFLAGS.BYTE_DONE as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

2

BYTE_RX_OVF

Enable bit for GPFLAGS.BYTE_RX_OVF as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

1

BYTE_ABORT

Enable bit for GPFLAGS.BYTE_ABORT as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

0

CS

Enable bit for GPFLAGS.CS as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0



TOP:SPIS:CFG

Address offset

0x0000 000C

Physical address

0x4008 500C

Instance

SPIS

Description

SPI Slave Configuration

Type

RW

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4

RX_DMA_REQ_TYPE

RX DMA request type select.

0: DMA request is chosen.
1: Single DMA transfer request is chosen.

RW

0

3

TX_DMA_REQ_TYPE

TX DMA request type select.

0: DMA Request is chosen.
1: Single DMA transfer request is chosen.

RW

0

2

RX_BIT_ORDER

MOSI first bit configuration.

0: First bit is LSB.
1: First bit is MSB.

RW

0

1

TX_BIT_ORDER

MISO first bit configuration.

0: First bit is LSB.
1: First bit is MSB.

RW

0

0

POL

SPI clock polarity.

0: CPOL=0 CPHA=0
1: CPOL=1 CPHA=0

RW

0



TOP:SPIS:TXFFLAGSCLRN

Address offset

0x0000 0010

Physical address

0x4008 5010

Instance

SPIS

Description

SPI Slave TX FIFO Flags Clear

Type

RW

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

6

OVF

TX FIFO overflow flag.

0: No TX FIFO overflow.
1: TX FIFO overflow due to writing data into a full TX FIFO.

RW

0

5

UNF

TX FIFO underflow flag.

0: No TX FIFO underflow.
1: TX FIFO underflow due to data request from the SPI Slave while TX FIFO is empty.

RW

0

4

NOT_EMPTY

TX FIFO has one or more bytes.

0: Number of bytes in TX FIFO is zero.
1: Number of bytes in TX FIFO is greater than zero.

RW

0

3

LE_THR

TX FIFO less than or equal TX FIFO threshold count set by TXFTHR.CNT.

0: Number of bytes in TX FIFO is greater than the TX FIFO threshold count.
1: Number of bytes in TX FIFO is equal or less than TX FIFO threshold count.

RW

1

2

GE_THR

TX FIFO greater than or equal to TX FIFO threshold count set by TXFTHR.CNT.

0: Number of bytes in TX FIFO is less than TX FIFO threshold count.
1: Number of bytes in TX FIFO is equal or greater than TX FIFO threshold count.

RW

1

1

EMPTY

TX FIFO empty flag.

0: TX FIFO not empty.
1: TX FIFO is empty. Attempting to clear the flag while the TX FIFO is empty, will result in the flag remaining set.

RW

1

0

FULL

TX FIFO full flag.

0: TX FIFO has not become full.
1: TX FIFO is full. Attempting to clear this flag while the TX FIFO is full, results in the flag remaining set.

RW

0



TOP:SPIS:TXFFLAGSSET

Address offset

0x0000 0014

Physical address

0x4008 5014

Instance

SPIS

Description

TX FIFO Flags Set
Allows setting of events related to TX FIFO flags for debug purposes.
Note that flag status bits are not modified.

Type

WO

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0x000 0000

6

OVF

TX FIFO overflow flag.

1: TX FIFO overflow event is forced to 1

WO

0

5

UNF

TX FIFO underflow flag.

1: TX FIFO underflow event is forced to 1

WO

0

4

NOT_EMPTY

TX FIFO has data flag.

1: TX FIFO has data event is forced to 1

WO

0

3

LE_THR

TX FIFO threshold count event.

1: TX FIFO lower than threshold count event is forced to 1

WO

0

2

GE_THR

TX FIFO GE threshold count event.

1: TX FIFO greater than or equal event is forced to 1

WO

0

1

EMPTY

TX FIFO empty event.

0: No effect
1: TX FIFO empty event is forced to 1

WO

0

0

FULL

TX FIFO full event.

1: TX FIFO full event is forced to 1

WO

0



TOP:SPIS:TXFFLAGSMASK

Address offset

0x0000 0018

Physical address

0x4008 5018

Instance

SPIS

Description

SPI Slave TX FIFO Flags Mask
One or more flags can be enabled as event triggers. This register defines a mask for which of the flags defined in TXFFLAGSCLRN that are to be enabled as flag event sources.

Type

RW

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

6

OVF

Enable bit for TXFFLAGSCLRN.OVF as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

5

UNF

Enable bit for TXFFLAGSCLRN.UNF as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

4

NOT_EMPTY

Enable bit for TXFFLAGSCLRN.NOT_EMPTY as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

3

LE_THR

Enable bit for TXFFLAGSCLRN.LE_THR as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

2

GE_THR

Enable bit for TXFFLAGSCLRN.GE_THR as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

1

EMPTY

Enable bit for TXFFLAGSCLRN.EMPTY as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

0

FULL

Enable bit for TXFFLAGSCLRN.FULL as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0



TOP:SPIS:TXSTAT

Address offset

0x0000 001C

Physical address

0x4008 501C

Instance

SPIS

Description

SPI Slave TX FIFO Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4

NOT_EMPTY

TX FIFO has one or more bytes status.

0: Number of bytes in TX FIFO is zero (empty).
1: Number of bytes in TX FIFO is greater than zero (not empty).

RO

0

3

LE_THR

TX FIFO less than or equal to TX FIFO threshold count set by TXFTHR.CNT.

0: Number of bytes in TX FIFO is greater than TX FIFO threshold count.
1: Number of bytes in TX FIFO is equal to or less than TX FIFO threshold count.

RO

1

2

GE_THR

TX FIFO greater than or equal to TX FIFO threshold count set by TXFTHR.CNT.

0: Number of bytes in TX FIFO is less than TX FIFO threshold count.
1: Number of bytes in TX FIFO is equal to or greater than TX FIFO threshold count.

RO

1

1

EMPTY

TX FIFO empty status.

0: TX FIFO is not empty.
1: TX FIFO is empty.

RO

1

0

FULL

TX FIFO full status.

0: TX FIFO is not full.
1: TX FIFO is full.

RO

0



TOP:SPIS:TXFEVSRC

Address offset

0x0000 0020

Physical address

0x4008 5020

Instance

SPIS

Description

SPI Slave TX FIFO Event Source
This register is used to select one of the status bit fields in [TXSTAT.* ] as source for an event.

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

SEL

TX FIFO Status event source select

Value

ENUM name

Description

0x0

FULL

TXSTAT.FULL FIFO is full

0x1

EMPTY

TXSTAT.EMPTY FIFO is empty

0x2

GE_THR

TXSTAT.GE_THR FIFO has more data than threshold count

0x3

LE_THR

TXSTAT.LE_THR FIFO has less data than threshold count

0x4

NOT_EMPTY

TXSTAT.NOT_EMPTY FIFO has some data

0x5

ONE

None

0x6

RESERVED

None

0x7

ZERO

None

RW

0x7



TOP:SPIS:TXFTHR

Address offset

0x0000 0024

Physical address

0x4008 5024

Instance

SPIS

Description

SPI Slave TX FIFO Threshold Count
Defines the threshold count of the TX FIFO.

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

CNT

TXFIFO count threshold.
TXSTAT.LE_THR and TXSTAT.GE_THR depend on this setting.

0x0: 0 bytes
0x1: 1 bytes
0x2: 2 bytes
...
0xE: 14 bytes
0xF: 15 bytes

RW

0x0



TOP:SPIS:TXFPUSH

Address offset

0x0000 0028

Physical address

0x4008 5028

Instance

SPIS

Description

SPI Slave TX FIFO Push
This register is used to push data into the TX FIFO.

Type

WO

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0x00 0000

7:0

DATA

Data to be pushed into TX FIFO.

WO

0x00



TOP:SPIS:TXFFLUSH

Address offset

0x0000 002C

Physical address

0x4008 502C

Instance

SPIS

Description

SPI Slave TX FIFO Flush
This register is used to flush the contents of the TX FIFO.

Type

WO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0x0000 0000

0

FLUSH

Execute TX FIFO flush command.

0: TX FIFO is not flushed (untouched).
1: TX FIFO is flushed.

WO

0



TOP:SPIS:TXFMEMRDPOS

Address offset

0x0000 0040

Physical address

0x4008 5040

Instance

SPIS

Description

SPI Slave TX FIFO Memory Read Pointer
The read pointer points to the location of the FIFO element which is the next byte that will be read out of the FIFO.

Type

RO

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

POS

Read pointer position.
0x0: FIFO element #0
0x1: FIFO element #1
...
0xE: FIFO element #14
0xF: FIFO element #15

RO

0x0



TOP:SPIS:TXMEMWRPOS

Address offset

0x0000 0044

Physical address

0x4008 5044

Instance

SPIS

Description

SPI Slave TX FIFO Memory Write Pointer
The write pointer points to the location in the FIFO where the next element will be written.

Type

RO

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

POS

Write pointer position.
0x0: FIFO element #0
0x1: FIFO element #1
...
0xE: FIFO element #14
0xF: FIFO element #15

RO

0x0



TOP:SPIS:TXFCNT

Address offset

0x0000 0048

Physical address

0x4008 5048

Instance

SPIS

Description

SPI Slave TX FIFO Count

Type

RO

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4:0

CNT

Number of bytes present in the TX FIFO.

0x00: 0 bytes in FIFO
0x01: 1 bytes in FIFO
...
0x0E: 14 bytes in FIFO
0x0F: 15 bytes in FIFO
0x10: 16 bytes in FIFO
0x11 to 0x1F: Unreachable values

RO

0x00



TOP:SPIS:RXFFLAGSCLRN

Address offset

0x0000 004C

Physical address

0x4008 504C

Instance

SPIS

Description

SPI Slave RX FIFO Flag Clear

Type

RW

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

6

OVF

RX FIFO overflow flag.

0: RX FIFO has no overflow.
1: RX FIFO overflow condition.

RW

0

5

UNF

RX FIFO underflow.

0: RX FIFO has no underflow.
1: RX FIFO underflow condition.

RW

0

4

NOT_EMPTY

RX FIFO has one or more bytes.

0: Number of bytes in RX FIFO equal zero.
1: Number of bytes in RX FIFO greater than zero.

RW

0

3

LE_THR

RX FIFO less than or equal RX FIFO threshold count.

0: Number of bytes in RX FIFO not less than or equal RX FIFO threshold count.
1: Number of bytes in RX FIFO less than or equal RX FIFO threshold count.

RW

1

2

GE_THR

RX FIFO greater than or equal to RX FIFO threshold count .

0: Number of bytes in RX FIFO not greater than or equal RX FIFO threshold count.
1: Number of bytes in RX FIFO greater than or equal RX FIFO threshold count.

RW

1

1

EMPTY

RX FIFO empty flag.
This flag can not be cleared while the RX FIFO remains empty.

0: RX FIFO not empty.
1: RX FIFO is empty.

RW

1

0

FULL

RX FIFO full flag.
This flag can not be cleared while the RX FIFO remains full.

0: RX FIFO not full.
1: RX FIFO is full.

RW

0



TOP:SPIS:RXFFLAGSSET

Address offset

0x0000 0050

Physical address

0x4008 5050

Instance

SPIS

Description

RX FIFO Flags Set
Allows setting of events related to RX FIFO flags for debug purposes.
Note that flag status bits are not modified.

Type

WO

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0x000 0000

6

OVF

RX FIFO overflow flag.
1: RX FIFO overflow event is forced to 1

WO

0

5

UNF

RX FIFO underflow flag.
1: RX FIFO underflow event is forced to 1

WO

0

4

NOT_EMPTY

RX FIFO has data flag.
1: RX FIFO has data event is forced to 1

WO

0

3

LE_THR

RX FIFO threshold count event.
1: RX FIFO lower than threshold count event is forced to 1

WO

0

2

GE_THR

RX FIFO GE threshold count event.
1: RX FIFO greater than or equal event is forced to 1

WO

0

1

EMPTY

RX FIFO empty event.
1: RX FIFO empty event is forced to 1

WO

0

0

FULL

RX FIFO full event.

1: RX FIFO full event is forced to 1

WO

0



TOP:SPIS:RXFFLAGSMASK

Address offset

0x0000 0054

Physical address

0x4008 5054

Instance

SPIS

Description

SPI Slave RX FIFO Flags Mask
This register defines a mask for which of the flags defined in the RXFFLAGSCLRN register that are to be enabled as flag event sources.

Type

RW

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

6

OVF

Enable bit for RXFFLAGSCLRN.OVF as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

5

UNF

Enable bit for RXFFLAGSCLRN.UNF as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

4

NOT_EMPTY

Enable bit for RXFFLAGSCLRN.NOT_EMPTY as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

3

LE_THR

Enable bit for RXFFLAGSCLRN.LE_THR as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

2

GE_THR

Enable bit for RXFFLAGSCLRN.GE_THR as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

1

EMPTY

Enable bit for RXFFLAGSCLRN.EMPTY as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0

0

FULL

Enable bit for RXFFLAGSCLRN.FULL as event signal.

0: Flag is not an event source.
1: Flag is enabled as an event source.

RW

0



TOP:SPIS:RXFSTAT

Address offset

0x0000 0058

Physical address

0x4008 5058

Instance

SPIS

Description

SPI Slave RX FIFO Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4

NOT_EMPTY

RX FIFO has one or more bytes status.

0: Number of bytes in RX FIFO is zero (empty).
1: Number of bytes in RX FIFO is greater than zero (not empty).

RO

0

3

LE_THR

RX FIFO byte count less than or equal to RX FIFO threshold count RXFTHR.CNT.

0: Number of bytes in RX FIFO is greater than RX FIFO threshold count.
1: Number of bytes in RX FIFO is equal to or less than RX FIFO threshold count.

RO

1

2

GE_THR

RX FIFO byte count greater than or equal to RX FIFO threshold count RXFTHR.CNT.

0: Number of bytes in RX FIFO is less than RX FIFO threshold count.
1: Number of bytes in RX FIFO is equal to or greater than RX FIFO threshold count.

RO

1

1

EMPTY

RX FIFO empty status.

0: RX FIFO is not empty.
1: RX FIFO is empty.

RO

1

0

FULL

RX FIFO full status.

0: RX FIFO is not full.
1: RX FIFO is full.

RO

0



TOP:SPIS:RXFEVSRC

Address offset

0x0000 005C

Physical address

0x4008 505C

Instance

SPIS

Description

SPI Slave RX FIFO Event Source
This register is used to select one of the status bit fields in the RXFSTAT register as source for an event.

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

SEL

RX FIFO Status source select

Value

ENUM name

Description

0x0

FULL

RXFSTAT.FULL FIFO is full

0x1

EMPTY

RXFSTAT.EMPTY FIFO is empty

0x2

GE_THR

RXFSTAT.GE_THR FIFO has more data than threshold count

0x3

LE_THR

RXFSTAT.LE_THR FIFO has less data than threshold count

0x4

NOT_EMPTY

RXFSTAT.NOT_EMPTY FIFO not empty

0x5

ONE

None

0x6

RESERVED

None

0x7

ZERO

None

RW

0x7



TOP:SPIS:RXFTHR

Address offset

0x0000 0060

Physical address

0x4008 5060

Instance

SPIS

Description

SPI Slave RX FIFO Threshold
Defines the threshold count of the RX FIFO.

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

CNT

Threshold count.

0x0: 0 bytes
0x1: 1 bytes
0x2: 2 bytes
...
0xE: 14 bytes
0xF: 15 bytes

RW

0x0



TOP:SPIS:RXFPOP

Address offset

0x0000 0064

Physical address

0x4008 5064

Instance

SPIS

Description

SPI Slave RX FIFO Pop
This register is used to read data from the RX FIFO.

Type

RO

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

DATA

Data read from RX FIFO.

RO

0x00



TOP:SPIS:RXFFLUSH

Address offset

0x0000 0068

Physical address

0x4008 5068

Instance

SPIS

Description

SPI Slave RX FIFO Flush
This register is used to empty the contents of the RX FIFO.

Type

WO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0x0000 0000

0

FLUSH

Execute RX FIFO flush command.

0: RX FIFO is not flushed (untouched).
1: RX FIFO is flushed.

WO

0



TOP:SPIS:RXFMEMRDPOS

Address offset

0x0000 0080

Physical address

0x4008 5080

Instance

SPIS

Description

SPI Slave RX FIFO Memory Read Position
This register returns the RX FIFO read pointer value.

Type

RO

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

POS

RX FIFO read pointer value.

0x0: FIFO element #0
0x1: FIFO element #1
...
0xE: Read Pointer at FIFO element #14
0xF: Read Pointer at FIFO element #15

RO

0x0



TOP:SPIS:RXFMEMWRPOS

Address offset

0x0000 0084

Physical address

0x4008 5084

Instance

SPIS

Description

SPI Slave RX FIFO Memory Write Position
This register returns the RX FIFO write pointer value.

Type

RO

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

POS

FIFO write pointer value.
0x0: FIFO element #0
0x1: FIFO element #1
...
0xE: FIFO element #14
0xF: FIFO element #15

RO

0x0



TOP:SPIS:RXCNT

Address offset

0x0000 0088

Physical address

0x4008 5088

Instance

SPIS

Description

SPI Slave RX FIFO Byte Count
This register returns the number of bytes that currently reside in the FIFO.

Type

RO

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4:0

CNT

Number of bytes in present in RX FIFO.

0x00: 0 bytes in FIFO
0x01: 1 bytes in FIFO
...
0x0E: 14 bytes in FIFO
0x0F: 15 bytes in FIFO
0x10: 16 bytes in FIFO
0x11 to 0x1F: Unreachable values

RO

0x00



TOP:SPIS:TXFMEM__0-TXFMEM__15

Address offset

0x0000 0400-0x0000 043C

Physical address

0x4008 5400- 0x4008 543C

Instance

SPIS

Description

SPI Slave TX FIFO Memory
The contents of the TX FIFO can be read by accessing this register.

Type

RO

Bits

Field Name

Description

Type

Reset

31:8

RESERVED8

Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

RO

0x00 0000

7:0

DATA

FIFO data element

RO

0x00



TOP:SPIS:RXFMEM__0-RXFMEM__15

Address offset

0x0000 0800-0x0000 083C

Physical address

0x4008 5800- 0x4008 583C

Instance

SPIS

Description

SPI Slave RX FIFO Data
The contents of the RX FIFO can be read from this register.

Type

RO

Bits

Field Name

Description

Type

Reset

31:8

RESERVED8

Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

RO

0x00 0000

7:0

DATA

FIFO data.

RO

0x00