ADI_2_REFSYS

Instance: ADI_2_REFSYS
Component: ADI_2_REFSYS
Base address: 0x40086000

 

ADI for REFSYS modules.
Registers Fields should be considered static unless otherwise noted (as dynamic)

 

TOP:ADI_2_REFSYS Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

REFSYSCTL0

RW

8

0x0000 0000

0x0000 0000

0x4008 6000

SOCLDOCTL0

RW

8

0x0000 0000

0x0000 0002

0x4008 6002

SOCLDOCTL1

RW

8

0x0000 0000

0x0000 0003

0x4008 6003

SOCLDOCTL2

RW

8

0x0000 0000

0x0000 0004

0x4008 6004

SOCLDOCTL3

RW

8

0x0000 0000

0x0000 0005

0x4008 6005

SOCLDOCTL4

RW

8

0x0000 0000

0x0000 0006

0x4008 6006

SOCLDOCTL5

RW

8

0x0000 0000

0x0000 0007

0x4008 6007

BAWCTL0

RW

8

0x0000 0000

0x0000 000A

0x4008 600A

BAWCTL1

RW

8

0x0000 0000

0x0000 000B

0x4008 600B

BAWCTL2

RW

8

0x0000 0000

0x0000 000C

0x4008 600C

TOP:ADI_2_REFSYS Register Descriptions

TOP:ADI_2_REFSYS:REFSYSCTL0

Address offset

0x0000 0000

Physical address

0x4008 6000

Instance

ADI_2_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0

4:0

TRIM_IREF

Internal

RW

0x00



TOP:ADI_2_REFSYS:SOCLDOCTL0

Address offset

0x0000 0002

Physical address

0x4008 6002

Instance

ADI_2_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7:4

VTRIM_UDIG

Internal

RW

0x0

3:0

VTRIM_BOD

Internal

RW

0x0



TOP:ADI_2_REFSYS:SOCLDOCTL1

Address offset

0x0000 0003

Physical address

0x4008 6003

Instance

ADI_2_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7:4

VTRIM_COARSE

Internal

RW

0x0

3:0

VTRIM_DIG

Internal

RW

0x0



TOP:ADI_2_REFSYS:SOCLDOCTL2

Address offset

0x0000 0004

Physical address

0x4008 6004

Instance

ADI_2_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

2:0

VTRIM_DELTA

Internal

RW

0x0



TOP:ADI_2_REFSYS:SOCLDOCTL3

Address offset

0x0000 0005

Physical address

0x4008 6005

Instance

ADI_2_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7:6

ITRIM_DIGLDO_LOAD

Internal

RW

0x0

5:3

ITRIM_DIGLDO

Internal

Value

ENUM name

Description

0x0

BIAS_60P

Internal

0x3

BIAS_80P

Internal

0x5

BIAS_100P

Internal

0x7

BIAS_120P

Internal

RW

0x0

2:0

ITRIM_UDIGLDO

Internal

RW

0x0



TOP:ADI_2_REFSYS:SOCLDOCTL4

Address offset

0x0000 0006

Physical address

0x4008 6006

Instance

ADI_2_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

6:5

UDIG_ITEST_EN

Internal

RW

0x0

4:2

DIG_ITEST_EN

Internal

RW

0x0

1

BIAS_DIS

Internal

RW

0

0

UDIG_LDO_EN

Internal

Value

ENUM name

Description

0

DIS

Internal

1

EN

Internal

RW

0



TOP:ADI_2_REFSYS:SOCLDOCTL5

Address offset

0x0000 0007

Physical address

0x4008 6007

Instance

ADI_2_REFSYS

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

7:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

3

IMON_ITEST_EN

Internal

RW

0

2:0

TESTSEL

Internal

Value

ENUM name

Description

0x0

NC

Internal

0x1

ITEST

Internal

0x2

VREF_AMP

Internal

0x4

VDD_AON

Internal

RW

0x0



TOP:ADI_2_REFSYS:BAWCTL0

Address offset

0x0000 000A

Physical address

0x4008 600A

Instance

ADI_2_REFSYS

Description

Bulk Acoustic Wave Control 0
Control bits for BAW oscillator in OSC_TOP

Type

RW

Bits

Field Name

Description

Type

Reset

7

FILTER_EN

Enable BAW Bias filter

Enable 1 kHz low pass filter LPF in the BAW bias.

RW

0

6:5

BIAS_RECHARGE_DLY

When BAWCTL2.BIAS_HOLD_MODE_EN = 1, low-power sample and hold mode for BAW bias is enabled. This field sets the recharge delay for this sample and hold mode by counting number of 48 MHz clock edges.

Value

ENUM name

Description

0x0

MIN_DLY_X1

682 us

0x1

MIN_DLY_X2

1365 us

0x2

MIN_DLY_X4

2731 us

0x3

MIN_DLY_X8

5461 us

RW

0x0

4:3

TUNE_CAP

Cap to shift BAW center frequency.

Value

ENUM name

Description

0x0

SHIFT_0

0 ppm shift

0x1

SHIFT_M35

-35 ppm shift

0x2

SHIFT_M70

-70 ppm shift

0x3

SHIFT_M108

-108 ppm shift

RW

0x0

2:1

SERIES_CAP

Cap to set BAW into proper mode. Set 1 time in factory.

00: 1.4 pF Cs1/Cs2
01: 1.1 pF Cs1/Cs2
10: 2.1 pF Cs1/Cs2
11: 1.8 pF Cs1/Cs2

RW

0x0

0

DIV3_BYPASS

Bypass for divide by 3 in divider.

Value

ENUM name

Description

0

BAW_840MHZ

Divide by 52.5 for use with 840 MHz BAW

1

BAW_2520MHZ

Divide by 17.5 for use with 2520 MHz BAW

RW

0



TOP:ADI_2_REFSYS:BAWCTL1

Address offset

0x0000 000B

Physical address

0x4008 600B

Instance

ADI_2_REFSYS

Description

Bulk Acoustic Wave Control 1
Control bits for BAW oscillator in OSC_TOP

Type

RW

Bits

Field Name

Description

Type

Reset

7

SPARE7

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0

6

SET_VREF

Select which VREF is used for BAW: BGAP or VDD.

Value

ENUM name

Description

0

BANDGAP

BANDGAP used for BAW VREF

1

VDD

VDD used for BAW VREF

RW

0

5

BIAS_DIS

Disable dummy bias current.

0: Dummy bias current on (Default)
1: Dummy bias current off

RW

0

4

PWRDET_EN

Enable signal for BAW power detector.

0: BAW power detector disabled.
1: BAW power detector enabled.

When enabled, Power detector VMAX and VMIN referred to in BAWCTL2.ATEST_SEL can be selected.

RW

0

3:0

BIAS_RES_SET

Adjust the BAW bias resistor to set the current in the BAW core. Two's complement encoding.

0x8: Highest resistance, lowest current
0x0: Default
0x7: Lowest resistance, maximum current

RW

0x0



TOP:ADI_2_REFSYS:BAWCTL2

Address offset

0x0000 000C

Physical address

0x4008 600C

Instance

ADI_2_REFSYS

Description

Bulk Acoustic Wave Control 2
Control bits for BAW oscillator in OSC_TOP

Type

RW

Bits

Field Name

Description

Type

Reset

7

BIAS_HOLD_MODE_EN

Enable signal for bias sample and hold mode. Should give some power savings at expense of increased phase noise or spurs.

0: Disabled hold mode
1: Enabled hold mode

RW

0

6

TESTMUX_EN

Enable signal for BAW test mux.

0: BAW test mux disabled.
1: BAW test mux enabled.

RW

0

5:4

ATEST_SEL

ATEST Selection Control

00: Output test bias current
01: Former connction for BAW BGAP. Not currently used.
10: Power detector VMAX
01: Power detector VMIN

Must also set TESTMUX_EN high to get test outputs.

RW

0x0

3:0

CURRMIRR_RATIO

Set current mirror ratio in BAW. Controls amount of current flowing in BAW oscillator core. May need to increase from nominal if nominal setting does not result in oscillation. Two's complement encoding.

0x8: Minimum current (~0 uA)
0x9: 50 uA
0x0: 400 uA
0x7: Maximum current (~750 uA)

RW

0x0