Instance: DDI_0_OSC
Component: DDI_0_OSC
Base address: 0x400ca000
This is the DDI for the digital block that controls all the analog clock oscillators (OSC_DIG) and performs qualification of the clocks generated.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C A000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x400C A004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x400C A008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x400C A00C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C A010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C A014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C A018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x400C A01C |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x400C A020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x400C A024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0x400C A028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x400C A02C |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x400C A030 |
|
RO |
32 |
0x0000 0000 |
0x0000 0034 |
0x400C A034 |
|
RO |
32 |
0x0000 0000 |
0x0000 0038 |
0x400C A038 |
|
RO |
32 |
0x0000 0000 |
0x0000 003C |
0x400C A03C |
Address offset |
0x0000 0000 |
||
Physical address |
0x400C A000 |
Instance |
DDI_0_OSC |
Description |
Control 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31 |
XTAL_IS_24M |
Set based on the accurate high frequency XTAL or BAW.
|
RW |
0 |
|||||||||||||||||||||
30 |
DOUBLER_BYPASS_CTL |
When this bit is set, the XOSC_HF doubler is bypassed - i.e. the XOSC_HF clock is not double but is instead routed to the output of the doubler. |
RW |
0 |
|||||||||||||||||||||
29 |
BYPASS_XOSC_LF_CLK_QUAL |
Bypass XOSC_LF clock gating. Extremely useful not to get glitch on sclk_lf. Should be '1' once sclk_lf source is switched to xosc_lf. |
RW |
0 |
|||||||||||||||||||||
28 |
BYPASS_RCOSC_LF_CLK_QUAL |
Override enable of clock gate that gates RCOSC_LF clock being fed to GF MUX. Extremely useful not to get glitch on sclk_lf. Should be '1' once sclk_lf source is switched to rcosc_lf |
RW |
0 |
|||||||||||||||||||||
27:26 |
DOUBLER_START_DURATION |
Controls the Doubler startup duration. This is the time that determines when the doubler output is good from the start of the doubler enable sequence. The time the doubler has to lock is determined by this bitfield and also DOUBLER_RESET_DURATION. DOUBLER_RESET_DURATION determines when reset ends - i.e. locking can start. This field determines when locking must complete. The allowable lock time is this setting minus the DOUBLER_RESET_DURATION setting. |
RW |
0x0 |
|||||||||||||||||||||
25 |
DOUBLER_RESET_DURATION |
Controls the doubler reset duration - the time that DOULBER_RESET and DOUBLER_EN are both active in the beginning of the doubler startup sequence. |
RW |
0 |
|||||||||||||||||||||
24 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
|||||||||||||||||||||
23 |
Reserved |
RW |
0 |
||||||||||||||||||||||
22 |
FORCE_KICKSTART_EN |
Kickstart the rcosc_hf oscillator if the high-frequency system clock (sclk_hf) is enabled while the OSC_DIG is in the HOLD state (no high frequency oscillator is enabled), and the source of sclk_lf is the xosc_hf. |
RW |
0 |
|||||||||||||||||||||
21 |
Reserved |
RW |
0 |
||||||||||||||||||||||
20 |
Reserved |
RW |
0 |
||||||||||||||||||||||
19 |
Reserved |
RW |
0 |
||||||||||||||||||||||
18 |
Reserved |
RW |
0 |
||||||||||||||||||||||
17 |
Reserved |
RW |
0 |
||||||||||||||||||||||
16 |
ALLOW_SCLK_HF_SWITCHING |
0: Default - Switching of HF clock source is disabled . |
RW |
0 |
|||||||||||||||||||||
15 |
Reserved |
RW |
0 |
||||||||||||||||||||||
14 |
BAW_MODE_EN |
0: Selects dtst_osc_clkin when OSC_DIG is bypassed |
RW |
0 |
|||||||||||||||||||||
13 |
Reserved |
RW |
0 |
||||||||||||||||||||||
12 |
RCOSC_LF_TRIMMED |
Determines the accuracy at which RCOSC_LF_CLK is qualified. The RCOSC_LF_CLK is measured against the oscdig_clk (2MHz). This bit determines the acceptable ratio of oscdig_clk periods per RCOSC_LF period. |
RW |
0 |
|||||||||||||||||||||
11 |
XOSC_HF_POWER_MODE |
XOSC/AMPCOMP mode. |
RW |
0 |
|||||||||||||||||||||
10 |
XOSC_LF_DIG_BYPASS |
Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock.. |
RW |
0 |
|||||||||||||||||||||
9 |
CLK_LOSS_EN |
Enable clock loss circuit and hence the indicators to system controller. Checks both SCLK_HF and SCLK_LF clock loss indicators. |
RW |
0 |
|||||||||||||||||||||
8:7 |
ACLK_TDC_SRC_SEL |
Source select for aclk_tdc. |
RW |
0x0 |
|||||||||||||||||||||
6:5 |
ACLK_REF_SRC_SEL |
Source select for aclk_ref |
RW |
0x0 |
|||||||||||||||||||||
4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
|||||||||||||||||||||
3:2 |
SCLK_LF_SRC_SEL |
Source select for sclk_lf
|
RW |
0x0 |
|||||||||||||||||||||
1 |
SCLK_MF_SRC_SEL |
Source select for sclk_mf
|
RW |
0 |
|||||||||||||||||||||
0 |
SCLK_HF_SRC_SEL |
Source select for sclk_hf
|
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x400C A004 |
Instance |
DDI_0_OSC |
Description |
Comtrol 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:28 |
Reserved |
Internal |
RW |
0x0 |
||
27:24 |
Reserved |
Internal |
RW |
0x0 |
||
23 |
Reserved |
Internal |
RW |
0 |
||
22:18 |
RCOSCHFCTRIMFRACT |
Sets the fractional tuning of the RCOSC_HF capacitor trim. This field only has an effect if RCOSC_HF fractional trim is enabled via RCOSCHFCTRIMFRACT_EN. This field sets the duty cycle of the signal which enables the capacitor for fractional trimming. The field is an unsigned integer value. The duty cycle is RCOSCHFCTRIMFRACT/32. The fractional trim capacitor is 2X the size of the capacitors controlled by RCOSCHFCTL.RCOSCHF_CTRIM. The effective additional capacitance added to the RCOSC_HF is equal to the duty cycle times 2X. E.g. If this field is set to 16, then the duty cycle is 50% so the effective trim adds one capacitor to the RCOSC_HF capacitance. Setting this field to 8 gives a duty cycle of 25% which effectively adds 1/2 of a capacitor. The value of this field is calibrated and set via FW. This field should only be changed when the fractional tuning is disabled or when the RCOSC_HF is off. |
RW |
0x00 |
||
17 |
RCOSCHFCTRIMFRACT_EN |
This field enables the fractional trimming of the RCOSC_HF captrim. |
RW |
0 |
||
16:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 |
||
1:0 |
XOSC_HF_FAST_START |
Set precharge duration of fast startup of the XOSC_HF |
RW |
0x0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x400C A008 |
Instance |
DDI_0_OSC |
Description |
RADC External Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:22 |
HPM_IBIAS_WAIT_CNT |
AMPCOMP FSM waits for this count of OSC_DIG clock cycles in order to compensate the effect of slow crystal response. HPM_IBIAS_WAIT_CNT*0.5 us is absolute wait time and should be close to XTAL's response time towards ibias/cap change |
RW |
0x000 |
||
21:16 |
LPM_IBIAS_WAIT_CNT |
FSM waits for LPM_IBIAS_WAIT_CNT clock cycles in the IBIAS_INCREMENT state in order to compensate slow response of the xtal. Typical values = 64. |
RW |
0x00 |
||
15:12 |
IDAC_STEP |
IDAC step size that will be used in IBIAS_CAP_UPDATE state. xosc_hf_idac is incremented IDAC_STEP times for each iteration of the loop that is performed during IBIAS_CAP_UPDATE. This setting is XTAL dependent and applied by FW. |
RW |
0x0 |
||
11:6 |
RADC_DAC_TH |
RADC threshhold value when in comparator mode. Used when RADC_EXTERNAL_USE_EN = 1. RADC_DAC_TH is an unsigned integer input to the DAC that sets the voltage that goes to the compare input to the RADC comparator. |
RW |
0x00 |
||
5 |
RADC_MODE_IS_SAR |
RADC mode when RADC_EXTERNAL_USE_EN = 1. |
RW |
0 |
||
4 |
RADC_START_CONV |
Start conversion signal when RADC_EXTERNAL_USE_EN = 1. |
RW |
0 |
||
3 |
Reserved |
Internal |
RW |
0 |
||
2 |
Reserved |
Internal |
RW |
0 |
||
1 |
DDI_RADC_CLRZ |
Active low clrz for RADC_DIG. |
RW |
0 |
||
0 |
Reserved |
Internal |
RW |
0 |
Address offset |
0x0000 000C |
||
Physical address |
0x400C A00C |
Instance |
DDI_0_OSC |
Description |
Amplitude Compensation Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
|||||||||||||||||||||
30 |
AMPCOMP_REQ_MODE |
RADC mode during ampcomp_req from AON. FSM forces ADC to be in selected mode during ampcomp request (during amplitude maintainance). |
RW |
0 |
|||||||||||||||||||||
29:28 |
AMPCOMP_FSM_UPDATE_RATE |
Run all XOSC input updates at 2M/1M/500K/250K.
|
RW |
0x0 |
|||||||||||||||||||||
27 |
AMPCOMP_SW_CTRL |
0: OSC_DIG HW controls enabled amplitude compensation. |
RW |
0 |
|||||||||||||||||||||
26 |
AMPCOMP_SW_EN |
0: Default |
RW |
0 |
|||||||||||||||||||||
25 |
XOSC_HF_HP_BUF_SW_CTRL |
This field give SW control of the enabling of the XOSC_HF or BAW clock to the synth. |
RW |
0 |
|||||||||||||||||||||
24 |
XOSC_HF_HP_BUF_SW_EN |
If XOSC_HF_HP_BUF_SW_CTRL = 0, then this bit has no effect. |
RW |
0 |
|||||||||||||||||||||
23:20 |
IBIAS_OFFSET |
Offset (minimum) value of XOSC IBIAS trim. |
RW |
0x0 |
|||||||||||||||||||||
19:16 |
IBIAS_INIT |
Value of XOSC IBIAS trim above the IBIAS_OFFSET for HPM. During ramp-up, IBIAS trim is set initially to the max value and then decreased to IBIAS_OFFSET + IBIAS_INIT on the way to HPM_UPDATE. The value is an unsigned integer. The setting is XTAL dependent and set by FW. |
RW |
0x0 |
|||||||||||||||||||||
15:8 |
LPM_IBIAS_WAIT_CNT_FINAL |
FSM waits for LPM_IBIAS_WAIT_CNT_FINAL clock cycles in the IDAC_DECREMENT_WITH_MEASURE state in order to compensate slow response of the xtal. The value is an unsigned integer. The setting is XTAL dependent and set by FW. |
RW |
0x00 |
|||||||||||||||||||||
7:4 |
CAP_STEP |
Step size of XOSC capasitor trim (both Q1 and Q2) during XOSC mode transition. Can vary from 6 to 12. Other values are possible but not valid. The value is an unsigned integer. The setting is XTAL dependent and set by FW. |
RW |
0x0 |
|||||||||||||||||||||
3:0 |
IBIASCAP_HPTOLP_OL_CNT |
During a HPM to LPM transition a HW loop is entered that modifies cap, ibias and iDAC trims. This field sets the number of loop iterations. In each iteration the cap trim is decremented CAP_STEP times, then the iDAC trim is incremented RADCEXTCFG.IDAC_STEP times, and finally the ibias trim is decremented by 1. After IBIASCAP_HPTOLP_OL_CNT iterations, the cap trim is decremented to 0 (if greater than 0) and the iDAC trim is incremented to 96 (if less than 96). The setting of this field is XTAL dependant and set by FW. |
RW |
0x0 |
Address offset |
0x0000 0010 |
||
Physical address |
0x400C A010 |
Instance |
DDI_0_OSC |
Description |
Amplitude Compensation Threashold 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:26 |
Reserved |
RW |
0x00 |
|||
25:24 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
23:18 |
HPMRAMP3_LTH |
HPM Ramp3 low amplitude threshhold. |
RW |
0x00 |
||
17:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
15:10 |
HPMRAMP3_HTH |
In HPM_RAMP3, if amp < HPMRAMP3_HTH then move to HPM_UPDATE. |
RW |
0x00 |
||
9:6 |
IBIASCAP_LPTOHP_OL_CNT |
During a LPM to HPM transition a HW loop is entered that modifies cap, and ibias trims. This field sets the number of loop iterations. In each iteration the cap trim is incremented AMPCOMPCTL.CAP_STEP times, then the ibias trim is decremented once. After IBIASCAP_LPTOHP_OL_CNT iterations, the cap trim is incremented until the trim is equal to the setting defined by ANABYPASSVAL1.XOSC_HF_ROW_Q12 and ANABYPASSVAL1.XOSC_HF_COLUMN_Q12. |
RW |
0x0 |
||
5:0 |
HPMRAMP1_TH |
HPM Ramp1 amplitude threshhold. |
RW |
0x00 |
Address offset |
0x0000 0014 |
||
Physical address |
0x400C A014 |
Instance |
DDI_0_OSC |
Description |
Amplitude Compensation Threashold 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:26 |
LPMUPDATE_LTH |
LPM Update low amplitude threshhold when RADC is in SAR mode. |
RW |
0x00 |
||
25:24 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
23:18 |
LPMUPDATE_HTH |
LPM update high amplitude threshhold when RADC is in SAR mode. |
RW |
0x00 |
||
17:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
15:10 |
ADC_COMP_AMPTH_LPM |
Low Power Mode Amplitude Threshold for Comparator mode. |
RW |
0x00 |
||
9:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
7:2 |
ADC_COMP_AMPTH_HPM |
High Power Mode Amplitude Threshold for Comparator mode. |
RW |
0x00 |
||
1:0 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
Address offset |
0x0000 0018 |
||
Physical address |
0x400C A018 |
Instance |
DDI_0_OSC |
Description |
Analog Bypass Values 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
Reserved |
Internal |
RW |
0 |
||
30 |
Reserved |
Internal |
RW |
0 |
||
29 |
Reserved |
Internal |
RW |
0 |
||
28 |
Reserved |
Internal |
RW |
0 |
||
27 |
Reserved |
Internal |
RW |
0 |
||
26:20 |
Reserved |
Internal |
RW |
0x00 |
||
19:16 |
XOSC_HF_ROW_Q12 |
This field is used whether or not OSC_DIG is bypassed. |
RW |
0x0 |
||
15:0 |
XOSC_HF_COLUMN_Q12 |
This field is used whether or not OSC_DIG is bypassed. |
RW |
0x0000 |
Address offset |
0x0000 001C |
||
Physical address |
0x400C A01C |
Instance |
DDI_0_OSC |
Description |
Internal Register. Customers can control this through TI provided API |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
Reserved |
Internal |
RW |
0 |
||
30 |
Reserved |
Internal |
RW |
0 |
||
29 |
Reserved |
Internal |
RW |
0 |
||
28 |
Reserved |
Internal |
RW |
0 |
||
27 |
Reserved |
Internal |
RW |
0 |
||
26 |
Reserved |
Internal |
RW |
0 |
||
25:14 |
Reserved |
Internal |
RW |
0x000 |
||
13:0 |
XOSC_HF_IBIASTHERM |
Internal |
RW |
0x0000 |
Address offset |
0x0000 0020 |
||
Physical address |
0x400C A020 |
Instance |
DDI_0_OSC |
Description |
Analog Test Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:30 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
29 |
SCLK_LF_AUX_EN |
Enable 32 kHz clock to SOC_AUX. |
RW |
0 |
||
28:20 |
ATEST_OSC_CTRL |
Select lines for top-level OSC_TOP ATEST mux. There are two outputs (ATEST1 and ATEST0) and each has an independently controlled mux. The muxes use a one-hot encoding. |
RW |
0x000 |
||
19:16 |
ATEST_OSC_HF_SEL |
Selects the source for high frequency oscillator test outputs. Note, does not control muxing of BAW related test signals. These are controled by ATESTLF_OSC_1P2V and ATESTLF_OSC_1P8V. |
RW |
0x0 |
||
15:12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
||
11:10 |
Reserved |
Internal field controlled by TI provided startup code |
RW |
0x0 |
||
9:8 |
Reserved |
Internal field controlled by TI provided startup code |
RW |
0x0 |
||
7 |
ATESTLF_RCOSCLF_IBIAS_TRIM |
Set high to increase the bias current to RCOSC_LF by 25 nA. Nominal value is 50 nA. With this bit enabled current is 75 nA. |
RW |
0 |
||
6 |
ATESTLF_UDIGLDO_IBIAS_TRIM |
Set high to enable an extra 25 nA of bias current to uDIGLDO (100% increase from nominal). |
RW |
0 |
||
5 |
ATESTLF_SOXAUX_IBIAS_TRIM |
Set high to enable extra 25 nA to SOCAUX (100% increase from nominal). |
RW |
0 |
||
4:3 |
ATESTLF_OSC_1P2V |
Select 1.2V output test clock to drive the ATEST1 signal. |
RW |
0x0 |
||
2:1 |
ATESTLF_OSC_1P8V |
Select the 1.8V test output to drive ATEST0. |
RW |
0x0 |
||
0 |
ATESTLF_EN |
Enables the 1p8V test output selected by ATESTLF_OSC_1P8V. |
RW |
0 |
Address offset |
0x0000 0024 |
||
Physical address |
0x400C A024 |
Instance |
DDI_0_OSC |
Description |
ADC Doubler Nanoamp Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
Reserved |
RW |
0 |
|||
30:25 |
Reserved |
RW |
0x00 |
|||
24 |
NANOAMP_BIAS_ENABLE |
Internal field controlled by TI provided startup code |
RW |
0 |
||
23 |
SPARE23 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior |
RW |
0 |
||
22 |
DBLR_ATEST_SELECT |
Analog test select for Doubler |
RW |
0 |
||
21 |
DBLR_ATEST_ENABLE |
Enable ATEST for DBLR. If enabled used DBLR_ATEST_SELECT to set ATEST bit. |
RW |
0 |
||
20 |
DBLR_TOOHI_MODE |
Not used. |
RW |
0 |
||
19 |
DBLR_LOOP_FILTER_CAP |
Loop filter cap |
RW |
0 |
||
18:17 |
DBLR_LOOP_FILTER_RESET_VOLTAGE |
Loop filter reset voltage |
RW |
0x0 |
||
16 |
DOUBLER_BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
||
15:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 |
||
9 |
RADC_BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
||
8:7 |
ADC_ATEST_SRC |
Select ATEST0 muxed output from RADC mux. Mux is enabled by ADC_EN_ATEST. |
RW |
0x0 |
||
6 |
ADC_EN_ATEST |
Enable ATEST0 mux whose output is selected by the ADC_ATEST_SRC bitfield. |
RW |
0 |
||
5 |
ADC_SH_MODE_EN |
Enable S&H Mode |
RW |
0 |
||
4 |
ADC_SH_VBUF_EN |
Enable S&H voltage buffer mode |
RW |
0 |
||
3:2 |
ADC_MUX_SEL |
Select line for 4-to-1 mux that feeds ADC input. Default is '00' Selects OSC_DIG input |
RW |
0x0 |
||
1:0 |
ADC_IREF_CTRL |
Select RADC IBIAS source. |
RW |
0x0 |
Address offset |
0x0000 0028 |
||
Physical address |
0x400C A028 |
Instance |
DDI_0_OSC |
Description |
XOSCHF Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 0000 |
||
11 |
HPBUFF_BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
||
10 |
PEAKDET_BIAS_DIS |
Disable dummy bias current. |
RW |
0 |
||
9:8 |
PEAK_DET_ITRIM |
Adjust Ibias trim of peak detector |
RW |
0x0 |
||
7 |
HP_ALT_BIAS |
Improve phase noise and reduce power consumption at the cost of reduced supply rejection. |
RW |
0 |
||
6 |
BYPASS |
Bypass XOSC_HF core and pass through external clock from X48P. |
RW |
0 |
||
5 |
TESTMUX_EN |
Enable XOSC_HF ATEST Outputs |
RW |
0 |
||
4:2 |
HP_BUF_ITRIM |
Adjust Ibias trim for HP buffer. |
RW |
0x0 |
||
1:0 |
LP_BUF_ITRIM |
Adjust Ibias trim for LP buffer. |
RW |
0x0 |
Address offset |
0x0000 002C |
||
Physical address |
0x400C A02C |
Instance |
DDI_0_OSC |
Description |
Low Frequency Oscillator Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:27 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x00 |
|||||||||||||||||||||
26 |
XOSCLF_BUFFER_TRIM |
Set high to double current mirror ratio in XOSCLF_LPBUFF (from 25 nA to 50 nA). Not normally used. |
RW |
0 |
|||||||||||||||||||||
25 |
XOSCLF_TESTMUX_EN |
This enables ATEST0 and ATEST1 outputs from xosclf. |
RW |
0 |
|||||||||||||||||||||
24 |
Reserved |
RW |
0 |
||||||||||||||||||||||
23:22 |
XOSCLF_REGULATOR_TRIM |
Trims resistor in constant gm bias |
RW |
0x0 |
|||||||||||||||||||||
21:18 |
XOSCLF_CMIRRWR_RATIO |
Adjust current mirror ratio into osc core |
RW |
0x0 |
|||||||||||||||||||||
17 |
XOSCLF_ANA_AMP_CTRL |
Disables analog amplitude control |
RW |
0 |
|||||||||||||||||||||
16 |
XOSCLF_RXTX_MODE |
Enables xosc_lf high-power buffer and disables the low-power-buffer. |
RW |
0 |
|||||||||||||||||||||
15:14 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
|||||||||||||||||||||
13:12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0 |
|||||||||||||||||||||
11 |
RCOSCLF_VDD_LOCAL_TRIM |
Not used. |
RW |
0 |
|||||||||||||||||||||
10 |
RCOSCLF_LOCAL_ATEST_EN |
Enable RCOSC_LF ATEST Outputs |
RW |
0 |
|||||||||||||||||||||
9:8 |
RCOSCLF_RTUNE_TRIM |
Trims the resistance in the RC 32 kHz osc to tune the osc frequency.
|
RW |
0x0 |
|||||||||||||||||||||
7:0 |
RCOSCLF_CTUNE_TRIM |
Internal field controlled by TI provided startup code |
RW |
0x00 |
Address offset |
0x0000 0030 |
||
Physical address |
0x400C A030 |
Instance |
DDI_0_OSC |
Description |
RCOSCHF Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0x0000 |
||
15:8 |
RCOSCHF_CTRIM |
Internal field controlled by TI provided startup code |
RW |
0x00 |
||
7 |
SPARE7 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior |
RW |
0 |
||
6 |
ATEST_VDD_LOCAL_SEL |
Selects source of VDD_LOCAL - before or after the buffer |
RW |
0 |
||
5 |
RCOSCHF_ATEST_EN |
Enables ATEST outputs of RCOSC_HF. |
RW |
0 |
||
4 |
Reserved |
Internal |
RW |
0 |
||
3:0 |
RCOSCHF_ITUNE_TRIM |
Trim bias current used in local inverter in 500nA steps. |
RW |
0x0 |
Address offset |
0x0000 0034 |
||
Physical address |
0x400C A034 |
Instance |
DDI_0_OSC |
Description |
Status 0 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
||
30:29 |
SCLK_LF_SRC |
Indicates source for the sclk_lf |
RO |
0x0 |
||
28 |
SCLK_HF_SRC |
RO |
0 |
|||
27 |
BYPASS_OSCDIG |
indicates that OSC_DIG is bypassed |
RO |
0 |
||
26 |
BGAP_NEEDED |
bgap_needed request from OSC_DIG |
RO |
0 |
||
25 |
BGAP_RDY |
bgap_rdy -- input |
RO |
0 |
||
24 |
GBIAS_NEEDED |
gbias_needed request from OSC_DIG |
RO |
0 |
||
23 |
GBIAS_RDY |
gbias_rdy -- input |
RO |
0 |
||
22 |
RCOSC_HF_EN |
RCOSC_HF_EN |
RO |
0 |
||
21 |
RCOSC_LF_EN |
RCOSC_LF_EN |
RO |
0 |
||
20 |
XOSC_LF_EN |
XOSC_LF_EN |
RO |
0 |
||
19 |
CLK_DCDC_RDY |
CLK_DCDC_RDY |
RO |
0 |
||
18 |
CLK_DCDC_RDY_ACK |
CLK_DCDC_RDY_ACK |
RO |
0 |
||
17 |
SCLK_HF_LOSS |
Indicates sclk_hf is lost |
RO |
0 |
||
16 |
SCLK_LF_LOSS |
Indicates sclk_lf is lost |
RO |
0 |
||
15 |
XOSC_HF_EN |
Indicates that XOSC_HF is enable if not BAW Mode. Else indicates BAW is active. |
RO |
0 |
||
14 |
XOSC_HF_PEAK_DET_EN |
XOSC_HF_PEAK_DET_EN |
RO |
0 |
||
13 |
XB_48M_CLK_EN |
Indicates that the 48MHz clock from the BAW or DOUBLER is enabled. |
RO |
0 |
||
12 |
ADC_EN |
ADC_EN |
RO |
0 |
||
11 |
XOSC_HF_LP_BUF_EN |
XOSC_HF_LP_BUF_EN |
RO |
0 |
||
10 |
XOSC_HF_HP_BUF_EN |
XOSC_HF_HP_BUF_EN |
RO |
0 |
||
9 |
RADC_DIG_CLRZ |
RADC_DIG_CLRZ |
RO |
0 |
||
8 |
ADC_THMET |
ADC_THMET |
RO |
0 |
||
7 |
ADC_DATA_READY |
indicates when adc_data is ready. |
RO |
0 |
||
6:1 |
ADC_DATA |
adc_data |
RO |
0x00 |
||
0 |
PENDINGSCLKHFSWITCHING |
Indicates when sclk_hf is ready to be swtiched |
RO |
0 |
Address offset |
0x0000 0038 |
||
Physical address |
0x400C A038 |
Instance |
DDI_0_OSC |
Description |
Status 1 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:28 |
RAMPSTATE |
|
RO |
0x0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:22 |
HMP_UPDATE_AMP |
OSC amplitude during HPM_UPDATE state. |
RO |
0x00 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
21:16 |
LPM_UPDATE_AMP |
OSC amplitude during LPM_UPDATE state |
RO |
0x00 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15 |
FORCE_RCOSC_HF |
force_rcosc_hf |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14 |
SCLK_HF_EN |
SCLK_HF_EN |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 |
SCLK_MF_EN |
SCLK_MF_EN |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 |
ACLK_ADC_EN |
ACLK_ADC_EN |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 |
ACLK_TDC_EN |
ACLK_TDC_EN |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 |
ACLK_REF_EN |
ACLK_REF_EN |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 |
CLK_CHP_EN |
CLK_CHP_EN |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 |
CLK_DCDC_EN |
CLK_DCDC_EN |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 |
SCLK_HF_GOOD |
SCLK_HF_GOOD |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 |
SCLK_MF_GOOD |
SCLK_MF_GOOD |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 |
SCLK_LF_GOOD |
SCLK_LF_GOOD |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 |
ACLK_ADC_GOOD |
ACLK_ADC_GOOD |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 |
ACLK_TDC_GOOD |
ACLK_TDC_GOOD |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 |
ACLK_REF_GOOD |
ACLK_REF_GOOD |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 |
CLK_CHP_GOOD |
CLK_CHP_GOOD |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 |
CLK_DCDC_GOOD |
CLK_DCDC_GOOD |
RO |
0 |
Address offset |
0x0000 003C |
||
Physical address |
0x400C A03C |
Instance |
DDI_0_OSC |
Description |
Status 2 |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||
31:26 |
ADC_DCBIAS |
DC Bias read by RADC during SAR mode |
RO |
0x00 |
|||||||||||||||||||||||||||||
25 |
HPM_RAMP1_THMET |
Indication of threshhold is met for hpm_ramp1 |
RO |
0 |
|||||||||||||||||||||||||||||
24 |
HPM_RAMP2_THMET |
Indication of threshhold is met for hpm_ramp2 |
RO |
0 |
|||||||||||||||||||||||||||||
23 |
HPM_RAMP3_THMET |
Indication of threshhold is met for hpm_ramp3 |
RO |
0 |
|||||||||||||||||||||||||||||
22 |
IBIAS_DEC_WITH_MEASURE_DONE |
Condition to exit ibias_dec_with_measure is met |
RO |
0 |
|||||||||||||||||||||||||||||
21 |
IBIAS_WAIT_CNTR_DONE |
Condition to exit ibias_wait_cntr is met |
RO |
0 |
|||||||||||||||||||||||||||||
20 |
IDAC_INCREMENT_DONE |
Condition to exit idac_increment is met |
RO |
0 |
|||||||||||||||||||||||||||||
19 |
IBIAS_CAP_UPDATE_DONE |
Condition to exit ibias_cap_updated is met |
RO |
0 |
|||||||||||||||||||||||||||||
18 |
IDAC_DECREMENT_WITH_MEASURE_DONE |
Condition to exit idac_dec_with_measure is met |
RO |
0 |
|||||||||||||||||||||||||||||
17 |
IBIAS_INCREMENT_DONE |
Condition to exit ibias_inc is met |
RO |
0 |
|||||||||||||||||||||||||||||
16 |
RAMP_DOWN_TO_INIT_DONE |
counter for ramp down to initi is done. Use for debug |
RO |
0 |
|||||||||||||||||||||||||||||
15:12 |
RAMPSTATE |
xosc_hf amplitude compensation FSM |
RO |
0x0 |
|||||||||||||||||||||||||||||
11:9 |
ADCSTATE |
ADC FSM State.
|
RO |
0x0 |
|||||||||||||||||||||||||||||
8 |
ADC_COMP_P |
LDO Status in BAW mode and comparator output in regular mode. Should be ignored in regular mode |
RO |
0 |
|||||||||||||||||||||||||||||
7 |
ADC_COMP_M |
BAW_CLKGOOD in BAW mode and not used in regular mode |
RO |
0 |
|||||||||||||||||||||||||||||
6:4 |
AMPCOMP_OF_UF |
overflow and underflow status in FSM |
RO |
0x0 |
|||||||||||||||||||||||||||||
3 |
AMPCOMP_REQ |
ampcomp_req |
RO |
0 |
|||||||||||||||||||||||||||||
2 |
XOSC_HF_AMPGOOD |
amplitude of xosc_hf is within the required threshold (set by DDI). Not used for anything just for debug/status |
RO |
0 |
|||||||||||||||||||||||||||||
1 |
XOSC_HF_FREQGOOD |
frequency of xosc_hf is good to use for the digital clocks |
RO |
0 |
|||||||||||||||||||||||||||||
0 |
XOSC_HF_RF_FREQGOOD |
frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer. |
RO |
0 |
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