PRCM

Instance: PRCM
Component: PRCM
Base address: 0x40082000

 

Power, Reset and Clock Management

 

TOP:PRCM Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

INFRCLKDIVR

RW

32

0x0000 0000

0x0000 0000

0x4008 2000

INFRCLKDIVS

RW

32

0x0000 0000

0x0000 0004

0x4008 2004

INFRCLKDIVDS

RW

32

0x0000 0000

0x0000 0008

0x4008 2008

VDCTL

RW

32

0x0000 0000

0x0000 000C

0x4008 200C

CLKLOADCTL

RW

32

0x0000 0002

0x0000 0028

0x4008 2028

RFCCLKG

RW

32

0x0000 0001

0x0000 002C

0x4008 202C

VIMSCLKG

RW

32

0x0000 0003

0x0000 0030

0x4008 2030

SECDMACLKGR

RW

32

0x0000 0000

0x0000 003C

0x4008 203C

SECDMACLKGS

RW

32

0x0000 0000

0x0000 0040

0x4008 2040

SECDMACLKGDS

RW

32

0x0000 0000

0x0000 0044

0x4008 2044

GPIOCLKGR

RW

32

0x0000 0000

0x0000 0048

0x4008 2048

GPIOCLKGS

RW

32

0x0000 0000

0x0000 004C

0x4008 204C

GPIOCLKGDS

RW

32

0x0000 0000

0x0000 0050

0x4008 2050

GPTCLKGR

RW

32

0x0000 0000

0x0000 0054

0x4008 2054

GPTCLKGS

RW

32

0x0000 0000

0x0000 0058

0x4008 2058

GPTCLKGDS

RW

32

0x0000 0000

0x0000 005C

0x4008 205C

I2CCLKGR

RW

32

0x0000 0000

0x0000 0060

0x4008 2060

I2CCLKGS

RW

32

0x0000 0000

0x0000 0064

0x4008 2064

I2CCLKGDS

RW

32

0x0000 0000

0x0000 0068

0x4008 2068

UARTCLKGR

RW

32

0x0000 0000

0x0000 006C

0x4008 206C

UARTCLKGS

RW

32

0x0000 0000

0x0000 0070

0x4008 2070

UARTCLKGDS

RW

32

0x0000 0000

0x0000 0074

0x4008 2074

SSICLKGR

RW

32

0x0000 0000

0x0000 0078

0x4008 2078

SSICLKGS

RW

32

0x0000 0000

0x0000 007C

0x4008 207C

SSICLKGDS

RW

32

0x0000 0000

0x0000 0080

0x4008 2080

I2SCLKGR

RW

32

0x0000 0000

0x0000 0084

0x4008 2084

I2SCLKGS

RW

32

0x0000 0000

0x0000 0088

0x4008 2088

I2SCLKGDS

RW

32

0x0000 0000

0x0000 008C

0x4008 208C

SYSBUSCLKDIV

RW

32

0x0000 0000

0x0000 00B4

0x4008 20B4

CPUCLKDIV

RW

32

0x0000 0000

0x0000 00B8

0x4008 20B8

PERBUSCPUCLKDIV

RW

32

0x0000 0000

0x0000 00BC

0x4008 20BC

PERDMACLKDIV

RW

32

0x0000 0000

0x0000 00C4

0x4008 20C4

I2SBCLKSEL

RW

32

0x0000 0000

0x0000 00C8

0x4008 20C8

GPTCLKDIV

RW

32

0x0000 0000

0x0000 00CC

0x4008 20CC

I2SCLKCTL

RW

32

0x0000 0000

0x0000 00D0

0x4008 20D0

I2SMCLKDIV

RW

32

0x0000 0000

0x0000 00D4

0x4008 20D4

I2SBCLKDIV

RW

32

0x0000 0000

0x0000 00D8

0x4008 20D8

I2SWCLKDIV

RW

32

0x0000 0000

0x0000 00DC

0x4008 20DC

RESETSECDMA

RW

32

0x0000 0000

0x0000 00F0

0x4008 20F0

RESETGPIO

RW

32

0x0000 0000

0x0000 00F4

0x4008 20F4

RESETGPT

RW

32

0x0000 0000

0x0000 00F8

0x4008 20F8

RESETI2C

RW

32

0x0000 0000

0x0000 00FC

0x4008 20FC

RESETUART

RW

32

0x0000 0000

0x0000 0100

0x4008 2100

RESETSSI

RW

32

0x0000 0000

0x0000 0104

0x4008 2104

RESETI2S

RW

32

0x0000 0000

0x0000 0108

0x4008 2108

SWRESET

RW

32

0x0000 0000

0x0000 010C

0x4008 210C

WARMRESET

RW

32

0x0000 0000

0x0000 0110

0x4008 2110

PDCTL0

RW

32

0x0000 0000

0x0000 012C

0x4008 212C

PDCTL0RFC

RW

32

0x0000 0000

0x0000 0130

0x4008 2130

PDCTL0SERIAL

RW

32

0x0000 0000

0x0000 0134

0x4008 2134

PDCTL0PERIPH

RW

32

0x0000 0000

0x0000 0138

0x4008 2138

PDSTAT0

RO

32

0x0000 0000

0x0000 0140

0x4008 2140

PDSTAT0RFC

RO

32

0x0000 0000

0x0000 0144

0x4008 2144

PDSTAT0SERIAL

RO

32

0x0000 0000

0x0000 0148

0x4008 2148

PDSTAT0PERIPH

RO

32

0x0000 0000

0x0000 014C

0x4008 214C

PDCTL1

RW

32

0x0000 000A

0x0000 017C

0x4008 217C

PDCTL1CPU

RW

32

0x0000 0001

0x0000 0184

0x4008 2184

PDCTL1RFC

RW

32

0x0000 0000

0x0000 0188

0x4008 2188

PDCTL1VIMS

RW

32

0x0000 0001

0x0000 018C

0x4008 218C

PDSTAT1

RO

32

0x0000 001A

0x0000 0194

0x4008 2194

PDSTAT1BUS

RO

32

0x0000 0001

0x0000 0198

0x4008 2198

PDSTAT1RFC

RO

32

0x0000 0000

0x0000 019C

0x4008 219C

PDSTAT1CPU

RO

32

0x0000 0001

0x0000 01A0

0x4008 21A0

PDSTAT1VIMS

RO

32

0x0000 0001

0x0000 01A4

0x4008 21A4

RFCMODESEL

RW

32

0x0000 0000

0x0000 01D0

0x4008 21D0

RAMRETEN

RW

32

0x0000 0003

0x0000 0224

0x4008 2224

PDRETEN

RW

32

0x0000 00E7

0x0000 022C

0x4008 222C

RAMHWOPT

RW

32

0x0000 0003

0x0000 0250

0x4008 2250

TOP:PRCM Register Descriptions

TOP:PRCM:INFRCLKDIVR

Address offset

0x0000 0000

Physical address

0x4008 2000

Instance

PRCM

Description

Infrastructure Clock Division Factor For Run Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

RATIO

Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode. Division ratio affects both infrastructure clock and perbusull clock.

Value

ENUM name

Description

0x0

DIV1

Divide by 1

0x1

DIV2

Divide by 2

0x2

DIV8

Divide by 8

0x3

DIV32

Divide by 32

RW

0x0



TOP:PRCM:INFRCLKDIVS

Address offset

0x0000 0004

Physical address

0x4008 2004

Instance

PRCM

Description

Infrastructure Clock Division Factor For Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

RATIO

Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode. Division ratio affects both infrastructure clock and perbusull clock.

Value

ENUM name

Description

0x0

DIV1

Divide by 1

0x1

DIV2

Divide by 2

0x2

DIV8

Divide by 8

0x3

DIV32

Divide by 32

RW

0x0



TOP:PRCM:INFRCLKDIVDS

Address offset

0x0000 0008

Physical address

0x4008 2008

Instance

PRCM

Description

Infrastructure Clock Division Factor For DeepSleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

RATIO

Division rate for clocks driving modules in the MCU_AON domain when system CPU is in seepsleep mode. Division ratio affects both infrastructure clock and perbusull clock.

Value

ENUM name

Description

0x0

DIV1

Divide by 1

0x1

DIV2

Divide by 2

0x2

DIV8

Divide by 8

0x3

DIV32

Divide by 32

RW

0x0



TOP:PRCM:VDCTL

Address offset

0x0000 000C

Physical address

0x4008 200C

Instance

PRCM

Description

MCU Voltage Domain Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

2

MCU_VD

Request WUC to power down the MCU voltage domain

0: No request
1: Assert request when possible. An asserted power down request will result in a boot of the MCU system when powered up again.

The bit will have no effect before the following requirements are met:
1. PDCTL1.CPU_ON = 0
2. PDCTL1.VIMS_MODE = 0
3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with CLKLOADCTL.LOAD)
4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with CLKLOADCTL.LOAD)
5. RFC do no request access to BUS
6. System CPU in deepsleep

RW

0

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

0

ULDO

Request WUC to switch to uLDO.

0: No request
1: Assert request when possible

The bit will have no effect before the following requirements are met:
1. PDCTL1.CPU_ON = 0
2. PDCTL1.VIMS_MODE = 0
3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be loaded with CLKLOADCTL.LOAD)
4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with CLKLOADCTL.LOAD)
5. RFC do no request access to BUS
6. System CPU in deepsleep

RW

0



TOP:PRCM:CLKLOADCTL

Address offset

0x0000 0028

Physical address

0x4008 2028

Instance

PRCM

Description

Load PRCM Settings To CLKCTRL Power Domain

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

LOAD_DONE

Status of LOAD.
Will be cleared to 0 when any of the registers requiring a LOAD is written to, and be set to 1 when a LOAD is done.
Note that writing no change to a register will result in the LOAD_DONE being cleared.

0 : One or more registers have been write accessed after last LOAD
1 : No registers are write accessed after last LOAD

RO

1

0

LOAD


0: No action
1: Load settings to CLKCTRL. Bit is HW cleared.

Multiple changes to settings may be done before LOAD is written once so all changes takes place at the same time. LOAD can also be done after single setting updates.

Registers that needs to be followed by LOAD before settings being applied are:
- SYSBUSCLKDIV
- CPUCLKDIV
- PERBUSCPUCLKDIV
- PERDMACLKDIV
- PERBUSCPUCLKG
- RFCCLKG
- VIMSCLKG
- SECDMACLKGR
- SECDMACLKGS
- SECDMACLKGDS
- GPIOCLKGR
- GPIOCLKGS
- GPIOCLKGDS
- GPTCLKGR
- GPTCLKGS
- GPTCLKGDS
- GPTCLKDIV
- I2CCLKGR
- I2CCLKGS
- I2CCLKGDS
- SSICLKGR
- SSICLKGS
- SSICLKGDS
- UARTCLKGR
- UARTCLKGS
- UARTCLKGDS
- I2SCLKGR
- I2SCLKGS
- I2SCLKGDS
- I2SBCLKSEL
- I2SCLKCTL
- I2SMCLKDIV
- I2SBCLKDIV
- I2SWCLKDIV
- RAMHWOPT

WO

0



TOP:PRCM:RFCCLKG

Address offset

0x0000 002C

Physical address

0x4008 202C

Instance

PRCM

Description

RFC Clock Gate

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

CLK_EN


0: Disable clock
1: Enable clock if RFC power domain is on

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

1



TOP:PRCM:VIMSCLKG

Address offset

0x0000 0030

Physical address

0x4008 2030

Instance

PRCM

Description

VIMS Clock Gate

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

CLK_EN

00: Disable clock
01: Disable clock when SYSBUS clock is disabled
11: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0x3



TOP:PRCM:SECDMACLKGR

Address offset

0x0000 003C

Physical address

0x4008 203C

Instance

PRCM

Description

SEC (TRNG And CRYPTO) And UDMA Clock Gate For Run Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8

DMA_CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0

7:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

1

TRNG_CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0

0

CRYPTO_CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:SECDMACLKGS

Address offset

0x0000 0040

Physical address

0x4008 2040

Instance

PRCM

Description

SEC (TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8

DMA_CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0

7:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

1

TRNG_CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0

0

CRYPTO_CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:SECDMACLKGDS

Address offset

0x0000 0044

Physical address

0x4008 2044

Instance

PRCM

Description

SEC (TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8

DMA_CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0

7:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

1

TRNG_CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0

0

CRYPTO_CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:GPIOCLKGR

Address offset

0x0000 0048

Physical address

0x4008 2048

Instance

PRCM

Description

GPIO Clock Gate For Run Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:GPIOCLKGS

Address offset

0x0000 004C

Physical address

0x4008 204C

Instance

PRCM

Description

GPIO Clock Gate For Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:GPIOCLKGDS

Address offset

0x0000 0050

Physical address

0x4008 2050

Instance

PRCM

Description

GPIO Clock Gate For Deep Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:GPTCLKGR

Address offset

0x0000 0054

Physical address

0x4008 2054

Instance

PRCM

Description

GPT Clock Gate For Run Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

CLK_EN

Each bit below has the following meaning:

0: Disable clock
1: Enable clock

ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Value

ENUM name

Description

0x1

GPT0

Enable clock for GPT0

0x2

GPT1

Enable clock for GPT1

0x4

GPT2

Enable clock for GPT2

0x8

GPT3

Enable clock for GPT3

RW

0x0



TOP:PRCM:GPTCLKGS

Address offset

0x0000 0058

Physical address

0x4008 2058

Instance

PRCM

Description

GPT Clock Gate For Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

CLK_EN

Each bit below has the following meaning:

0: Disable clock
1: Enable clock

ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Value

ENUM name

Description

0x1

GPT0

Enable clock for GPT0

0x2

GPT1

Enable clock for GPT1

0x4

GPT2

Enable clock for GPT2

0x8

GPT3

Enable clock for GPT3

RW

0x0



TOP:PRCM:GPTCLKGDS

Address offset

0x0000 005C

Physical address

0x4008 205C

Instance

PRCM

Description

GPT Clock Gate For Deep Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

CLK_EN

Each bit below has the following meaning:

0: Disable clock
1: Enable clock

ENUMs can be combined
For changes to take effect, CLKLOADCTL.LOAD needs to be written

Value

ENUM name

Description

0x1

GPT0

Enable clock for GPT0

0x2

GPT1

Enable clock for GPT1

0x4

GPT2

Enable clock for GPT2

0x8

GPT3

Enable clock for GPT3

RW

0x0



TOP:PRCM:I2CCLKGR

Address offset

0x0000 0060

Physical address

0x4008 2060

Instance

PRCM

Description

I2C Clock Gate For Run Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:I2CCLKGS

Address offset

0x0000 0064

Physical address

0x4008 2064

Instance

PRCM

Description

I2C Clock Gate For Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:I2CCLKGDS

Address offset

0x0000 0068

Physical address

0x4008 2068

Instance

PRCM

Description

I2C Clock Gate For Deep Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:UARTCLKGR

Address offset

0x0000 006C

Physical address

0x4008 206C

Instance

PRCM

Description

UART Clock Gate For Run Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:UARTCLKGS

Address offset

0x0000 0070

Physical address

0x4008 2070

Instance

PRCM

Description

UART Clock Gate For Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:UARTCLKGDS

Address offset

0x0000 0074

Physical address

0x4008 2074

Instance

PRCM

Description

UART Clock Gate For Deep Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:SSICLKGR

Address offset

0x0000 0078

Physical address

0x4008 2078

Instance

PRCM

Description

SSI Clock Gate For Run Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

Value

ENUM name

Description

0x1

SSI0

Enable clock for SSI0

0x2

SSI1

Enable clock for SSI1

RW

0x0



TOP:PRCM:SSICLKGS

Address offset

0x0000 007C

Physical address

0x4008 207C

Instance

PRCM

Description

SSI Clock Gate For Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

Value

ENUM name

Description

0x1

SSI0

Enable clock for SSI0

0x2

SSI1

Enable clock for SSI1

RW

0x0



TOP:PRCM:SSICLKGDS

Address offset

0x0000 0080

Physical address

0x4008 2080

Instance

PRCM

Description

SSI Clock Gate For Deep Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

Value

ENUM name

Description

0x1

SSI0

Enable clock for SSI0

0x2

SSI1

Enable clock for SSI1

RW

0x0



TOP:PRCM:I2SCLKGR

Address offset

0x0000 0084

Physical address

0x4008 2084

Instance

PRCM

Description

I2S Clock Gate For Run Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:I2SCLKGS

Address offset

0x0000 0088

Physical address

0x4008 2088

Instance

PRCM

Description

I2S Clock Gate For Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:I2SCLKGDS

Address offset

0x0000 008C

Physical address

0x4008 208C

Instance

PRCM

Description

I2S Clock Gate For Deep Sleep Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

CLK_EN


0: Disable clock
1: Enable clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:SYSBUSCLKDIV

Address offset

0x0000 00B4

Physical address

0x4008 20B4

Instance

PRCM

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

RATIO

Internal

Value

ENUM name

Description

0x0

DIV1

Internal

0x1

DIV2

Internal

0x2

DIV4

Internal

0x3

DIV8

Internal

0x4

DIV16

Internal

0x5

DIV32

Internal

RW

0x0



TOP:PRCM:CPUCLKDIV

Address offset

0x0000 00B8

Physical address

0x4008 20B8

Instance

PRCM

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

RATIO

Internal

Value

ENUM name

Description

0

DIV1

Internal

1

DIV2

Internal

RW

0



TOP:PRCM:PERBUSCPUCLKDIV

Address offset

0x0000 00BC

Physical address

0x4008 20BC

Instance

PRCM

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

RATIO

Internal

Value

ENUM name

Description

0x0

DIV1

Internal

0x1

DIV2

Internal

0x2

DIV4

Internal

0x3

DIV8

Internal

0x4

DIV16

Internal

0x5

DIV32

Internal

0x6

DIV64

Internal

0x7

DIV128

Internal

0x8

DIV256

Internal

RW

0x0



TOP:PRCM:PERDMACLKDIV

Address offset

0x0000 00C4

Physical address

0x4008 20C4

Instance

PRCM

Description

Internal Register. Customers can control this through TI provided API

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

RATIO

Internal

Value

ENUM name

Description

0x0

DIV1

Internal

0x1

DIV2

Internal

0x2

DIV4

Internal

0x3

DIV8

Internal

0x4

DIV16

Internal

0x5

DIV32

Internal

0x6

DIV64

Internal

0x7

DIV128

Internal

0x8

DIV256

Internal

RW

0x0



TOP:PRCM:I2SBCLKSEL

Address offset

0x0000 00C8

Physical address

0x4008 20C8

Instance

PRCM

Description

I2S Clock Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

0x0

0

SRC

BCLK source selector

0: Use external BCLK
1: Use internally generated clock

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:GPTCLKDIV

Address offset

0x0000 00CC

Physical address

0x4008 20CC

Instance

PRCM

Description

GPT Scalar

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

RATIO

Scalar used for GPTs. The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when it is slower than the PERBUSCPUCLKDIV.RATIO setting. When set faster than PERBUSCPUCLKDIV.RATIO setting the PERBUSCPUCLKDIV.RATIO will be used.
Note that the register will contain the written content even though the setting is faster than PERBUSCPUCLKDIV.RATIO setting.

For changes to take effect, CLKLOADCTL.LOAD needs to be written
Other values are not supported.

Value

ENUM name

Description

0x0

DIV1

Divide by 1

0x1

DIV2

Divide by 2

0x2

DIV4

Divide by 4

0x3

DIV8

Divide by 8

0x4

DIV16

Divide by 16

0x5

DIV32

Divide by 32

0x6

DIV64

Divide by 64

0x7

DIV128

Divide by 128

0x8

DIV256

Divide by 256

RW

0x0



TOP:PRCM:I2SCLKCTL

Address offset

0x0000 00D0

Physical address

0x4008 20D0

Instance

PRCM

Description

I2S Clock Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3

SMPL_ON_POSEDGE

On the I2S serial interface, data and WCLK is sampled and clocked out on opposite edges of BCLK.

0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge.
1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge.

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0

2:1

WCLK_PHASE

Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV).

0: Single phase
1: Dual phase
2: User Defined
3: Reserved/Undefined

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0x0

0

EN


0: MCLK, BCLK and **WCLK** will be static low
1: Enables the generation of MCLK, BCLK and WCLK

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0



TOP:PRCM:I2SMCLKDIV

Address offset

0x0000 00D4

Physical address

0x4008 20D4

Instance

PRCM

Description

MCLK Division Ratio

Type

RW

Bits

Field Name

Description

Type

Reset

31:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

9:0

MDIV

An unsigned factor of the division ratio used to generate MCLK [2-1024]:

MCLK = MCUCLK/MDIV[Hz]
MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined by AON_WUC:MCUCLK.PWR_DWN_SRC

A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If MDIV is odd the low phase of the clock is one MCUCLK period longer than the high phase.

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0x000



TOP:PRCM:I2SBCLKDIV

Address offset

0x0000 00D8

Physical address

0x4008 20D8

Instance

PRCM

Description

BCLK Division Ratio

Type

RW

Bits

Field Name

Description

Type

Reset

31:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

9:0

BDIV

An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]:

BCLK = MCUCLK/BDIV[Hz]
MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined by AON_WUC:MCUCLK.PWR_DWN_SRC

A value of 0 is interpreted as 1024.
A value of 1 is invalid.
If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock is one MCUCLK period longer than the high phase.
If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the clock is one MCUCLK period longer than the low phase.

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0x000



TOP:PRCM:I2SWCLKDIV

Address offset

0x0000 00DC

Physical address

0x4008 20DC

Instance

PRCM

Description

WCLK Division Ratio

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

WDIV

If I2SCLKCTL.WCLK_PHASE = 0, Single phase.
WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK periods.

WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]
MCUCLK is 48MHz in normal mode. For powerdown mode the frequency is defined by [AON_WUC:MCUCLK.PWR_DWN_SRC]

If I2SCLKCTL.WCLK_PHASE = 1, Dual phase.
Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK periods.

WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz]

If I2SCLKCTL.WCLK_PHASE = 2, User defined.
WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] (unsigned, [1-255]) BCLK periods.

WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]

For changes to take effect, CLKLOADCTL.LOAD needs to be written

RW

0x0000



TOP:PRCM:RESETSECDMA

Address offset

0x0000 00F0

Physical address

0x4008 20F0

Instance

PRCM

Description

RESET For SEC (TRNG And CRYPTO) And UDMA

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8

DMA

Write 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0

7:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

1

TRNG

Write 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0

0

CRYPTO

Write 1 to reset. HW cleared.
Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0



TOP:PRCM:RESETGPIO

Address offset

0x0000 00F4

Physical address

0x4008 20F4

Instance

PRCM

Description

RESET For GPIO IPs

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

GPIO


0: No action
1: Reset GPIO. HW cleared.

Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0



TOP:PRCM:RESETGPT

Address offset

0x0000 00F8

Physical address

0x4008 20F8

Instance

PRCM

Description

RESET For GPT Ips

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

GPT


0: No action
1: Reset GPT. HW cleared.

Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

Value

ENUM name

Description

0x1

GPT0

Reset GPT0

0x2

GPT1

Reset GPT1

0x4

GPT2

Reset GPT2

0x8

GPT3

Reset GPT3

WO

0x0



TOP:PRCM:RESETI2C

Address offset

0x0000 00FC

Physical address

0x4008 20FC

Instance

PRCM

Description

RESET For I2C IPs

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0

0

I2C


0: No action
1: Reset I2C. HW cleared.

Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0



TOP:PRCM:RESETUART

Address offset

0x0000 0100

Physical address

0x4008 2100

Instance

PRCM

Description

RESET For UART IPs

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(WO std text)

WO

0

0

UART


0: No action
1: Reset UART. HW cleared.

Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0



TOP:PRCM:RESETSSI

Address offset

0x0000 0104

Physical address

0x4008 2104

Instance

PRCM

Description

RESET For SSI IPs

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

SSI

SSI 0:

0: No action
1: Reset SSI. HW cleared.

Acess will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

SSI 1:

0: No action
1: Reset SSI. HW cleared.

Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0x0



TOP:PRCM:RESETI2S

Address offset

0x0000 0108

Physical address

0x4008 2108

Instance

PRCM

Description

RESET For I2S IP

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

I2S


0: No action
1: Reset module. HW cleared.

Acess will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0



TOP:PRCM:SWRESET

Address offset

0x0000 010C

Physical address

0x4008 210C

Instance

PRCM

Description

SW Initiated Resets

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2

MCU


0: No action
1: Generates reset request to WUC to reset the entire MCU voltage domain. Request is cleared by HW.

Everything in MCU voltage domain reset including PRCM itself

WO

0

1

RFC


0: No action
1: Generates reset pulse to the RFC power domain. HW cleared

Acess will only have effect when RFC power domain is on, PDSTAT0.RFC_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0

0

CPU


0: No action
1: Generates reset pulse to the system CPU core (not including the DAP). HW cleared

Acess will only have effect when CPU power domain is on, PDSTAT1.CPU_ON = 1
Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset.

WO

0



TOP:PRCM:WARMRESET

Address offset

0x0000 0110

Physical address

0x4008 2110

Instance

PRCM

Description

WARM Reset Control And Status

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2

WR_TO_PINRESET


0: No action
1: A warm system reset event triggered by the below listed sources will result in an emulated pin reset.

Warm reset sources included:
ICEPick sysreset
System CPU reset request, CM3_SCS:AIRCR.SYSRESETREQ
System CPU Lockup
SYSRESETDBG.TRIG
WDT timeout

An active ICEPick block system reset will gate all sources except ICEPick sysreset

SW can read AON_SYSCTL:RESETCTL.RESET_SRC to find the source of the last reset resulting in a full power up sequence. WARMRESET in this register is set in the scenario that WR_TO_PINRESET=1 and one of the above listed sources is triggered.

RW

0

1

LOCKUP_STAT


0: No registred event
1: A system CPU LOCKUP event has occured since last SW clear of the register.

A read of this register clears both WDT_STAT and LOCKUP_STAT.

RO

0

0

WDT_STAT


0: No registered event
1: A WDT event has occured since last SW clear of the register.

A read of this register clears both WDT_STAT and LOCKUP_STAT.

RO

0



TOP:PRCM:PDCTL0

Address offset

0x0000 012C

Physical address

0x4008 212C

Instance

PRCM

Description

Power Domain Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2

PERIPH_ON

PERIPH Power domain.

0: PERIPH power domain is powered down
1: PERIPH power domain is powered up

RW

0

1

SERIAL_ON

SERIAL Power domain.

0: SERIAL power domain is powered down
1: SERIAL power domain is powered up

RW

0

0

RFC_ON


0: RFC power domain powered off if also PDCTL1.RFC_ON = 0
1: RFC power domain powered on

RW

0



TOP:PRCM:PDCTL0RFC

Address offset

0x0000 0130

Physical address

0x4008 2130

Instance

PRCM

Description

RFC Power Domain Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

Alias for PDCTL0.RFC_ON

RW

0



TOP:PRCM:PDCTL0SERIAL

Address offset

0x0000 0134

Physical address

0x4008 2134

Instance

PRCM

Description

SERIAL Power Domain Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

Alias for PDCTL0.SERIAL_ON

RW

0



TOP:PRCM:PDCTL0PERIPH

Address offset

0x0000 0138

Physical address

0x4008 2138

Instance

PRCM

Description

PERIPH Power Domain Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

Alias for PDCTL0.PERIPH_ON

RW

0



TOP:PRCM:PDSTAT0

Address offset

0x0000 0140

Physical address

0x4008 2140

Instance

PRCM

Description

Power Domain Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2

PERIPH_ON

PERIPH Power domain.

0: Domain may be powered down
1: Domain powered up (guaranteed)

RO

0

1

SERIAL_ON

SERIAL Power domain.

0: Domain may be powered down
1: Domain powered up (guaranteed)

RO

0

0

RFC_ON

RFC Power domain

0: Domain may be powered down
1: Domain powered up (guaranteed)

RO

0



TOP:PRCM:PDSTAT0RFC

Address offset

0x0000 0144

Physical address

0x4008 2144

Instance

PRCM

Description

RFC Power Domain Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

Alias for PDSTAT0.RFC_ON

RO

0



TOP:PRCM:PDSTAT0SERIAL

Address offset

0x0000 0148

Physical address

0x4008 2148

Instance

PRCM

Description

SERIAL Power Domain Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

Alias for PDSTAT0.SERIAL_ON

RO

0



TOP:PRCM:PDSTAT0PERIPH

Address offset

0x0000 014C

Physical address

0x4008 214C

Instance

PRCM

Description

PERIPH Power Domain Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

Alias for PDSTAT0.PERIPH_ON

RO

0



TOP:PRCM:PDCTL1

Address offset

0x0000 017C

Physical address

0x4008 217C

Instance

PRCM

Description

Power Domain Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4

RESERVED4

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

RW

0

3

VIMS_MODE


0: VIMS power domain is only powered when CPU power domain is powered.
1: VIMS power domain is powered whenever the BUS power domain is powered.

RW

1

2

RFC_ON


0: RFC power domain powered off if also PDCTL0.RFC_ON = 0
1: RFC power domain powered on

Bit shall be used by RFC in autonomus mode but there is no HW restrictions fom system CPU to access the bit.

RW

0

1

CPU_ON


0: Causes a power down of the CPU power domain when system CPU indicates it is idle.
1: Initiates power-on of the CPU power domain.

This bit is automatically set by a WIC power-on event.

RW

1

0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0



TOP:PRCM:PDCTL1CPU

Address offset

0x0000 0184

Physical address

0x4008 2184

Instance

PRCM

Description

CPU Power Domain Direct Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

This is an alias for PDCTL1.CPU_ON

RW

1



TOP:PRCM:PDCTL1RFC

Address offset

0x0000 0188

Physical address

0x4008 2188

Instance

PRCM

Description

RFC Power Domain Direct Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

This is an alias for PDCTL1.RFC_ON

RW

0



TOP:PRCM:PDCTL1VIMS

Address offset

0x0000 018C

Physical address

0x4008 218C

Instance

PRCM

Description

VIMS mode Direct Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

This is an alias for PDCTL1.VIMS_MODE

RW

1



TOP:PRCM:PDSTAT1

Address offset

0x0000 0194

Physical address

0x4008 2194

Instance

PRCM

Description

Power Manager Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4

BUS_ON


0: BUS domain not accessible
1: BUS domain is currently accessible

RO

1

3

VIMS_MODE


0: VIMS domain not accessible
1: VIMS domain is currently accessible

RO

1

2

RFC_ON


0: RFC domain not accessible
1: RFC domain is currently accessible

RO

0

1

CPU_ON


0: CPU and BUS domain not accessible
1: CPU and BUS domains are both currently accessible

RO

1

0

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0



TOP:PRCM:PDSTAT1BUS

Address offset

0x0000 0198

Physical address

0x4008 2198

Instance

PRCM

Description

BUS Power Domain Direct Read Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

This is an alias for PDSTAT1.BUS_ON

RO

1



TOP:PRCM:PDSTAT1RFC

Address offset

0x0000 019C

Physical address

0x4008 219C

Instance

PRCM

Description

RFC Power Domain Direct Read Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

This is an alias for PDSTAT1.RFC_ON

RO

0



TOP:PRCM:PDSTAT1CPU

Address offset

0x0000 01A0

Physical address

0x4008 21A0

Instance

PRCM

Description

CPU Power Domain Direct Read Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

This is an alias for PDSTAT1.CPU_ON

RO

1



TOP:PRCM:PDSTAT1VIMS

Address offset

0x0000 01A4

Physical address

0x4008 21A4

Instance

PRCM

Description

VIMS mode Direct Read Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

ON

This is an alias for PDSTAT1.VIMS_MODE

RO

1



TOP:PRCM:RFCMODESEL

Address offset

0x0000 01D0

Physical address

0x4008 21D0

Instance

PRCM

Description

Selected RFC Mode

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

CURR

Written by MCU - Outputs to RFC. Only modes permitted by RFCMODEHWOPT.AVAIL are writeable.

Value

ENUM name

Description

0x0

MODE0

Select Mode 0

0x1

MODE1

Select Mode 1

0x2

MODE2

Select Mode 2

0x3

MODE3

Select Mode 3

0x4

MODE4

Select Mode 4

0x5

MODE5

Select Mode 5

0x6

MODE6

Select Mode 6

0x7

MODE7

Select Mode 7

RW

0x0



TOP:PRCM:RAMRETEN

Address offset

0x0000 0224

Physical address

0x4008 2224

Instance

PRCM

Description

Memory Retention Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2

RFC


0: Retention for RFC SRAM disabled
1: Retention for RFC SRAM enabled

RW

0

1:0

VIMS


0: Memory retention disabled
1: Memory retention enabled

Bit 0: VIMS_TRAM
Bit 1: VIMS_CRAM

Legal modes depend on settings in VIMS:CTL.MODE and PDRETEN.VIMS

PDRETEN.VIMS = 1

00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to CACHE or SPLIT mode after waking up again
01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in GPRAM mode after wake up, alternatively select OFF mode first and then CACHE or SPILT mode.
10: Illegal mode
11: No restrictions

PDRETEN.VIMS = 0

00: Special TI debug mode. Do not use.
All others: Illegal modes.

RW

0x3



TOP:PRCM:PDRETEN

Address offset

0x0000 022C

Physical address

0x4008 222C

Instance

PRCM

Description

Power Domain Retention Control

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text)

RW

1

6

PERIPH


0: Retention disabled
1: Retention enabled

RW

1

5

SERIAL

Domain not designed for retention. Writing this bit will have no effect.

RW

1

4

RFC

Domain not designed for retention. Writing this bit will have no effect.

RW

0

3

BUS

Domain not designed for retention. Writing this bit will have no effect.

RW

0

2

Reserved

Internal field controlled by TI provided startup code

RW

1

1

CPU


0: Retention disabled
1: Retention enabled

Do not use!
If disabled a subsequent cold reset of CPU power domain the boot code will error out and system CPU will be stuck

RW

1

0

CLKCTL

Domain not designed for retention. Writing this bit will have no effect.

RW

1



TOP:PRCM:RAMHWOPT

Address offset

0x0000 0250

Physical address

0x4008 2250

Instance

PRCM

Description

CONFIG SIZE For SRAM

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

SIZE

Internal field controlled by TI provided startup code

Value

ENUM name

Description

0x0

4K

Select 4k RAMSIZE

0x1

10K

Select 10k RAMSIZE

0x2

16K

Select 16k RAMSIZE

0x3

20K

Select 20k RAMSIZE

RW

0x3