Instance: GPT2
Component: GPT
Base address: 0x40012000
General Purpose Timer.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4001 2000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4001 2004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4001 2008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0x4001 200C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x4001 2010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4001 2018 |
|
RO |
32 |
0x0000 0000 |
0x0000 001C |
0x4001 201C |
|
RO |
32 |
0x0000 0000 |
0x0000 0020 |
0x4001 2020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4001 2024 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0028 |
0x4001 2028 |
|
RW |
32 |
0x0000 FFFF |
0x0000 002C |
0x4001 202C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0030 |
0x4001 2030 |
|
RW |
32 |
0x0000 FFFF |
0x0000 0034 |
0x4001 2034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4001 2038 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x4001 203C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x4001 2040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4001 2044 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0048 |
0x4001 2048 |
|
RO |
32 |
0x0000 FFFF |
0x0000 004C |
0x4001 204C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0050 |
0x4001 2050 |
|
RW |
32 |
0x0000 FFFF |
0x0000 0054 |
0x4001 2054 |
|
RO |
32 |
0x0000 7FFF |
0x0000 0058 |
0x4001 2058 |
|
RO |
32 |
0x0000 0000 |
0x0000 005C |
0x4001 205C |
|
RO |
32 |
0x0000 0000 |
0x0000 0060 |
0x4001 2060 |
|
RO |
32 |
0x0000 0000 |
0x0000 0064 |
0x4001 2064 |
|
RO |
32 |
0x0000 0000 |
0x0000 0068 |
0x4001 2068 |
|
RW |
32 |
0x0000 0000 |
0x0000 006C |
0x4001 206C |
|
RW |
32 |
0x0000 0000 |
0x0000 0070 |
0x4001 2070 |
|
RO |
32 |
0x0000 0400 |
0x0000 0FB0 |
0x4001 2FB0 |
|
RW |
32 |
0x0000 0000 |
0x0000 0FB4 |
0x4001 2FB4 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4001 2000 |
Instance |
GPT2 |
Description |
GPT Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||
2:0 |
CFG |
GPT Configuration
|
RW |
0x0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4001 2004 |
Instance |
GPT2 |
Description |
GPT Timer A Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
|||||||||||||||||||||||||||||||||||||
15:13 |
TCACT |
Timer Compare Action Select
|
RW |
0x0 |
|||||||||||||||||||||||||||||||||||||
12 |
TACINTD |
One-Shot/Periodic Interrupt Disable
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
11 |
TAPLO |
Legacy PWM operation
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
10 |
TAMRSU |
Timer A Match Register Update mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
9 |
TAPWMIE |
GPT Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output.
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
8 |
TAILD |
GPT Timer A PWM Interval Load Write
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
7 |
TASNAPS |
GPT Timer A Snap-Shot Mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
6 |
TAWOT |
GPT Timer A Wait-On-Trigger
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
5 |
TAMIE |
GPT Timer A Match Interrupt Enable
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
4 |
TACDIR |
GPT Timer A Count Direction
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
3 |
TAAMS |
GPT Timer A Alternate Mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
2 |
TACM |
GPT Timer A Capture Mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
1:0 |
TAMR |
GPT Timer A Mode
|
RW |
0x0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x4001 2008 |
Instance |
GPT2 |
Description |
GPT Timer B Mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
|||||||||||||||||||||||||||||||||||||
15:13 |
TCACT |
Timer Compare Action Select
|
RW |
0x0 |
|||||||||||||||||||||||||||||||||||||
12 |
TBCINTD |
One-Shot/Periodic Interrupt Mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
11 |
TBPLO |
Legacy PWM operation
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
10 |
TBMRSU |
Timer B Match Register Update mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
9 |
TBPWMIE |
GPT Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
8 |
TBILD |
GPT Timer B PWM Interval Load Write
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
7 |
TBSNAPS |
GPT Timer B Snap-Shot Mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
6 |
TBWOT |
GPT Timer B Wait-On-Trigger
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
5 |
TBMIE |
GPT Timer B Match Interrupt Enable.
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
4 |
TBCDIR |
GPT Timer B Count Direction
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
3 |
TBAMS |
GPT Timer B Alternate Mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
2 |
TBCM |
GPT Timer B Capture Mode
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||
1:0 |
TBMR |
GPT Timer B Mode
|
RW |
0x0 |
Address offset |
0x0000 000C |
||
Physical address |
0x4001 200C |
Instance |
GPT2 |
Description |
GPT Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||
31:15 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
|||||||||||||||||
14 |
TBPWML |
GPT Timer B PWM Output Level
|
RW |
0 |
|||||||||||||||||
13 |
TBOTE |
GPT Timer B Output Trigger Enable
|
RW |
0 |
|||||||||||||||||
12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
|||||||||||||||||
11:10 |
TBEVENT |
GPT Timer B Event Mode
|
RW |
0x0 |
|||||||||||||||||
9 |
TBSTALL |
GPT Timer B Stall Enable
|
RW |
0 |
|||||||||||||||||
8 |
TBEN |
GPT Timer B Enable
|
RW |
0 |
|||||||||||||||||
7 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
|||||||||||||||||
6 |
TAPWML |
|
RW |
0 |
|||||||||||||||||
5 |
TAOTE |
GPT Timer A Output Trigger Enable
|
RW |
0 |
|||||||||||||||||
4 |
RTCEN |
|
RW |
0 |
|||||||||||||||||
3:2 |
TAEVENT |
GPT Timer A Event Mode
|
RW |
0x0 |
|||||||||||||||||
1 |
TASTALL |
GPT Timer A Stall Enable
|
RW |
0 |
|||||||||||||||||
0 |
TAEN |
GPT Timer A Enable
|
RW |
0 |
Address offset |
0x0000 0010 |
||
Physical address |
0x4001 2010 |
Instance |
GPT2 |
Description |
GPT Synch Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||||||||||
7:6 |
SYNC3 |
Synchronize GPT Timer 3.
|
WO |
0x0 |
|||||||||||||||||||||
5:4 |
SYNC2 |
Synchronize GPT Timer 2.
|
WO |
0x0 |
|||||||||||||||||||||
3:2 |
SYNC1 |
Synchronize GPT Timer 1
|
WO |
0x0 |
|||||||||||||||||||||
1:0 |
SYNC0 |
Synchronize GPT Timer 0
|
WO |
0x0 |
Address offset |
0x0000 0018 |
||
Physical address |
0x4001 2018 |
Instance |
GPT2 |
Description |
GPT Interrupt Mask |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:17 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
|||||||||||||
16 |
WUMIS |
Enabling this bit will make the RIS.WURIS interrupt propagate to MIS.WUMIS
|
RW |
0 |
|||||||||||||
15:14 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
|||||||||||||
13 |
DMABIM |
Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS
|
RW |
0 |
|||||||||||||
12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
|||||||||||||
11 |
TBMIM |
Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS
|
RW |
0 |
|||||||||||||
10 |
CBEIM |
Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS
|
RW |
0 |
|||||||||||||
9 |
CBMIM |
Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS
|
RW |
0 |
|||||||||||||
8 |
TBTOIM |
Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS
|
RW |
0 |
|||||||||||||
7:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
|||||||||||||
5 |
DMAAIM |
Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS
|
RW |
0 |
|||||||||||||
4 |
TAMIM |
Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS
|
RW |
0 |
|||||||||||||
3 |
RTCIM |
Enabling this bit will make the RIS.RTCRIS interrupt propagate to MIS.RTCMIS
|
RW |
0 |
|||||||||||||
2 |
CAEIM |
Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS
|
RW |
0 |
|||||||||||||
1 |
CAMIM |
Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS
|
RW |
0 |
|||||||||||||
0 |
TATOIM |
Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS
|
RW |
0 |
Address offset |
0x0000 001C |
||
Physical address |
0x4001 201C |
Instance |
GPT2 |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:17 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
16 |
WURIS |
GPT Write Update Error Raw Interrupt |
RO |
0 |
||
15:14 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
13 |
DMABRIS |
GPT Timer B DMA Done Raw Interrupt Status |
RO |
0 |
||
12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
||
11 |
TBMRIS |
GPT Timer B Match Raw Interrupt |
RO |
0 |
||
10 |
CBERIS |
GPT Timer B Capture Mode Event Raw Interrupt |
RO |
0 |
||
9 |
CBMRIS |
GPT Timer B Capture Mode Match Raw Interrupt |
RO |
0 |
||
8 |
TBTORIS |
GPT Timer B Time-out Raw Interrupt |
RO |
0 |
||
7:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
5 |
DMAARIS |
GPT Timer A DMA Done Raw Interrupt Status |
RO |
0 |
||
4 |
TAMRIS |
**GPT **Timer A Match Raw Interrupt |
RO |
0 |
||
3 |
RTCRIS |
GPT RTC Raw Interrupt |
RO |
0 |
||
2 |
CAERIS |
GPT Timer A Capture Mode Event Raw Interrupt |
RO |
0 |
||
1 |
CAMRIS |
GPT Timer A Capture Mode Match Raw Interrupt |
RO |
0 |
||
0 |
TATORIS |
GPT Timer A Time-out Raw Interrupt |
RO |
0 |
Address offset |
0x0000 0020 |
||
Physical address |
0x4001 2020 |
Instance |
GPT2 |
Description |
GPT Masked Interrupt Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:17 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
16 |
WUMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
15:14 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
13 |
DMABMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
||
11 |
TBMMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
10 |
CBEMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
9 |
CBMMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
8 |
TBTOMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
7:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
5 |
DMAAMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
4 |
TAMMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
3 |
RTCMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
2 |
CAEMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
1 |
CAMMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
||
0 |
TATOMIS |
0: No interrupt or interrupt not enabled |
RO |
0 |
Address offset |
0x0000 0024 |
||
Physical address |
0x4001 2024 |
Instance |
GPT2 |
Description |
GPT Interrupt Clear |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:17 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
16 |
WUECINT |
RW |
0 |
|||
15:14 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
13 |
DMABINT |
0: Do nothing. |
RW |
0 |
||
12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
||
11 |
TBMCINT |
0: Do nothing. |
RW |
0 |
||
10 |
CBECINT |
0: Do nothing. |
RW |
0 |
||
9 |
CBMCINT |
0: Do nothing. |
RW |
0 |
||
8 |
TBTOCINT |
0: Do nothing. |
RW |
0 |
||
7:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
||
5 |
DMAAINT |
0: Do nothing. |
RW |
0 |
||
4 |
TAMCINT |
0: Do nothing. |
RW |
0 |
||
3 |
RTCCINT |
0: Do nothing. |
RW |
0 |
||
2 |
CAECINT |
0: Do nothing. |
RW |
0 |
||
1 |
CAMCINT |
0: Do nothing. |
RW |
0 |
||
0 |
TATOCINT |
0: Do nothing. |
RW |
0 |
Address offset |
0x0000 0028 |
||
Physical address |
0x4001 2028 |
Instance |
GPT2 |
Description |
GPT Timer A Interval Load Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TAILR |
GPT Timer A Interval Load Register |
RW |
0xFFFF FFFF |
Address offset |
0x0000 002C |
||
Physical address |
0x4001 202C |
Instance |
GPT2 |
Description |
GPT Timer B Interval Load Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TBILR |
GPT Timer B Interval Load Register |
RW |
0x0000 FFFF |
Address offset |
0x0000 0030 |
||
Physical address |
0x4001 2030 |
Instance |
GPT2 |
Description |
GPT Timer A Match Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TAMATCHR |
GPT Timer A Match Register |
RW |
0xFFFF FFFF |
Address offset |
0x0000 0034 |
||
Physical address |
0x4001 2034 |
Instance |
GPT2 |
Description |
GPT Timer B Match Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TBMATCHR |
GPT Timer B Match Register |
RW |
0x0000 FFFF |
Address offset |
0x0000 0038 |
||
Physical address |
0x4001 2038 |
Instance |
GPT2 |
Description |
GPT Timer A Pre-scale |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
TAPSR |
Timer A Pre-scale. |
RW |
0x00 |
Address offset |
0x0000 003C |
||
Physical address |
0x4001 203C |
Instance |
GPT2 |
Description |
GPT Timer B Pre-scale |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
TBPSR |
Timer B Pre-scale. |
RW |
0x00 |
Address offset |
0x0000 0040 |
||
Physical address |
0x4001 2040 |
Instance |
GPT2 |
Description |
GPT Timer A Pre-scale Match |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
TAPSMR |
GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. |
RW |
0x00 |
Address offset |
0x0000 0044 |
||
Physical address |
0x4001 2044 |
Instance |
GPT2 |
Description |
GPT Timer B Pre-scale Match |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
TBPSMR |
GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16. |
RW |
0x00 |
Address offset |
0x0000 0048 |
||
Physical address |
0x4001 2048 |
Instance |
GPT2 |
Description |
GPT Timer A Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TAR |
GPT Timer A Register |
RO |
0xFFFF FFFF |
Address offset |
0x0000 004C |
||
Physical address |
0x4001 204C |
Instance |
GPT2 |
Description |
GPT Timer B Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TBR |
GPT Timer B Register |
RO |
0x0000 FFFF |
Address offset |
0x0000 0050 |
||
Physical address |
0x4001 2050 |
Instance |
GPT2 |
Description |
GPT Timer A Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TAV |
GPT Timer A Register |
RW |
0xFFFF FFFF |
Address offset |
0x0000 0054 |
||
Physical address |
0x4001 2054 |
Instance |
GPT2 |
Description |
GPT Timer B Value |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
TBV |
GPT Timer B Register |
RW |
0x0000 FFFF |
Address offset |
0x0000 0058 |
||
Physical address |
0x4001 2058 |
Instance |
GPT2 |
Description |
GPT RTC Pre-divide Value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
RTCPD |
RO |
0x7FFF |
Address offset |
0x0000 005C |
||
Physical address |
0x4001 205C |
Instance |
GPT2 |
Description |
GPT Timer A Pre-scale Snap-shot |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PSS |
GPT Timer A Pre-scaler |
RO |
0x0000 |
Address offset |
0x0000 0060 |
||
Physical address |
0x4001 2060 |
Instance |
GPT2 |
Description |
GPT Timer A Pre-scale Snap-shot |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PSS |
GPT Timer B Pre-scaler |
RO |
0x0000 |
Address offset |
0x0000 0064 |
||
Physical address |
0x4001 2064 |
Instance |
GPT2 |
Description |
GPT Timer A Pre-scale Value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PSV |
GPT Timer A Pre-scaler Value |
RO |
0x0000 |
Address offset |
0x0000 0068 |
||
Physical address |
0x4001 2068 |
Instance |
GPT2 |
Description |
GPT Timer B Pre-scale Value |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
PSV |
GPT Timer B Pre-scaler Value |
RO |
0x0000 |
Address offset |
0x0000 006C |
||
Physical address |
0x4001 206C |
Instance |
GPT2 |
Description |
GPT DMA Event |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:12 |
RESERVED12 |
Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. |
RO |
0x0 0000 |
||
11 |
TBMDMAEN |
RW |
0 |
|||
10 |
CBEDMAEN |
RW |
0 |
|||
9 |
CBMDMAEN |
RW |
0 |
|||
8 |
TBTODMAEN |
RW |
0 |
|||
7:5 |
RESERVED5 |
Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. |
RW |
0x0 |
||
4 |
TAMDMAEN |
RW |
0 |
|||
3 |
RTCDMAEN |
RW |
0 |
|||
2 |
CAEDMAEN |
RW |
0 |
|||
1 |
CAMDMAEN |
RW |
0 |
|||
0 |
TATODMAEN |
RW |
0 |
Address offset |
0x0000 0070 |
||
Physical address |
0x4001 2070 |
Instance |
GPT2 |
Description |
GPT ADC Event |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:12 |
RESERVED12 |
Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. |
RO |
0x0 0000 |
||
11 |
TBMADCEN |
RW |
0 |
|||
10 |
CBEADCEN |
RW |
0 |
|||
9 |
CBMADCEN |
RW |
0 |
|||
8 |
TBTOADCEN |
RW |
0 |
|||
7:5 |
RESERVED5 |
Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. |
RW |
0x0 |
||
4 |
TAMADCEN |
RW |
0 |
|||
3 |
RTCADCEN |
RW |
0 |
|||
2 |
CAEADCEN |
RW |
0 |
|||
1 |
CAMADCEN |
RW |
0 |
|||
0 |
TATOADCEN |
RW |
0 |
Address offset |
0x0000 0FB0 |
||
Physical address |
0x4001 2FB0 |
Instance |
GPT2 |
Description |
GPT Peripheral Version |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
VERSION |
Timer Revision. |
RO |
0x0000 0400 |
Address offset |
0x0000 0FB4 |
||
Physical address |
0x4001 2FB4 |
Instance |
GPT2 |
Description |
GPT Combined CCP Output |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
CCP_AND_EN |
Enables anding of the CCP outputs for timers A and B |
RW |
0 |
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