Instance: CPU_DWT
Component: CPU_DWT
Base address: 0xe0001000
Cortex-M's Data watchpoint and Trace (DWT)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x4000 0000 |
0x0000 0000 |
0xE000 1000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0xE000 1004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0xE000 1008 |
|
RW |
32 |
0x0000 0000 |
0x0000 000C |
0xE000 100C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0xE000 1010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0xE000 1014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0xE000 1018 |
|
RO |
32 |
0x0000 0000 |
0x0000 001C |
0xE000 101C |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0xE000 1020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0xE000 1024 |
|
RW |
32 |
0x0000 0000 |
0x0000 0028 |
0xE000 1028 |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0xE000 1030 |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0xE000 1034 |
|
RW |
32 |
0x0000 0200 |
0x0000 0038 |
0xE000 1038 |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0xE000 1040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0xE000 1044 |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0xE000 1048 |
|
RW |
32 |
0x0000 0000 |
0x0000 0050 |
0xE000 1050 |
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0xE000 1054 |
|
RW |
32 |
0x0000 0000 |
0x0000 0058 |
0xE000 1058 |
Address offset |
0x0000 0000 |
||
Physical address |
0xE000 1000 |
Instance |
CPU_DWT |
Description |
DWT Control Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:26 |
RESERVED26 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x10 |
|||||||||||||||||||||
25 |
NOCYCCNT |
When set, CYCCNT is not supported. |
RW |
0 |
|||||||||||||||||||||
24 |
NOPRFCNT |
When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. |
RW |
0 |
|||||||||||||||||||||
23 |
RESERVED23 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
|||||||||||||||||||||
22 |
CYCEVTENA |
Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. This event is only emitted if PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. |
RW |
0 |
|||||||||||||||||||||
21 |
FOLDEVTENA |
Enables Folded instruction count event. Emits an event when FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. |
RW |
0 |
|||||||||||||||||||||
20 |
LSUEVTENA |
Enables LSU count event. Emits an event when LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. |
RW |
0 |
|||||||||||||||||||||
19 |
SLEEPEVTENA |
Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 cycles that the processor is sleeping). |
RW |
0 |
|||||||||||||||||||||
18 |
EXCEVTENA |
Enables Interrupt overhead event. Emits an event when EXCCNT overflows (every 256 cycles of interrupt overhead). |
RW |
0 |
|||||||||||||||||||||
17 |
CPIEVTENA |
Enables CPI count event. Emits an event when CPICNT overflows (every 256 cycles of multi-cycle instructions). |
RW |
0 |
|||||||||||||||||||||
16 |
EXCTRCENA |
Enables Interrupt event tracing. |
RW |
0 |
|||||||||||||||||||||
15:13 |
RESERVED13 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 |
|||||||||||||||||||||
12 |
PCSAMPLEENA |
Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this bit overrides CYCEVTENA. |
RW |
0 |
|||||||||||||||||||||
11:10 |
SYNCTAP |
Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA must also be enabled for this feature.
|
RW |
0x0 |
|||||||||||||||||||||
9 |
CYCTAP |
Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or cycle count event (see details in CYCEVTENA).
|
RW |
0 |
|||||||||||||||||||||
8:5 |
POSTCNT |
Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the value from POSTPRESET. |
RW |
0x0 |
|||||||||||||||||||||
4:1 |
POSTPRESET |
Reload value for post-scalar counter POSTCNT. When 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, it forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change. |
RW |
0x0 |
|||||||||||||||||||||
0 |
CYCCNTENA |
Enable CYCCNT, allowing it to increment and generate synchronization and count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. |
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0xE000 1004 |
Instance |
CPU_DWT |
Description |
DWT Current PC Sampler Cycle Count Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
CYCCNT |
Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted. The cycle counter is a free running counter, counting upwards (this counter will not advance in power modes where free-running clock to CPU stops). It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling. |
RW |
0x0000 0000 |
Address offset |
0x0000 0008 |
||
Physical address |
0xE000 1008 |
Instance |
CPU_DWT |
Description |
DWT CPI Count Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
RESERVED8 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 0000 |
||
7:0 |
CPICNT |
Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by LSUCNT. This counter also increments on all instruction fetch stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter overflows. This counter initializes to 0 when it is enabled using CTRL.CPIEVTENA. |
RW |
0x00 |
Address offset |
0x0000 000C |
||
Physical address |
0xE000 100C |
Instance |
CPU_DWT |
Description |
DWT Exception Overhead Count Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
RESERVED8 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 0000 |
||
7:0 |
EXCCNT |
Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. |
RW |
0x00 |
Address offset |
0x0000 0010 |
||
Physical address |
0xE000 1010 |
Instance |
CPU_DWT |
Description |
DWT Sleep Count Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
RESERVED8 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 0000 |
||
7:0 |
SLEEPCNT |
Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note that the sleep counter is clocked using CPU's free-running clock. In some power modes the free-running clock to CPU is gated to minimize power consumption. This means that the sleep counter will be invalid in these power modes. |
RW |
0x00 |
Address offset |
0x0000 0014 |
||
Physical address |
0xE000 1014 |
Instance |
CPU_DWT |
Description |
DWT LSU Count Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
RESERVED8 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 0000 |
||
7:0 |
LSUCNT |
LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (i.e. takes four cycles to execute), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. |
RW |
0x00 |
Address offset |
0x0000 0018 |
||
Physical address |
0xE000 1018 |
Instance |
CPU_DWT |
Description |
DWT Fold Count Register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
RESERVED8 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 0000 |
||
7:0 |
FOLDCNT |
This counts the total number folded instructions. This counter initializes to 0 when it is enabled using CTRL.FOLDEVTENA. |
RW |
0x00 |
Address offset |
0x0000 001C |
||
Physical address |
0xE000 101C |
Instance |
CPU_DWT |
Description |
DWT Program Counter Sample Register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
EIASAMPLE |
Execution instruction address sample, or 0xFFFFFFFF if the core is halted. |
RO |
0x0000 0000 |
Address offset |
0x0000 0020 |
||
Physical address |
0xE000 1020 |
Instance |
CPU_DWT |
Description |
DWT Comparator Register 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
COMP |
Reference value to compare against PC or the data address as given by FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler Counter (CYCCNT). |
RW |
0x0000 0000 |
Address offset |
0x0000 0024 |
||
Physical address |
0xE000 1024 |
Instance |
CPU_DWT |
Description |
DWT Mask Register 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x000 0000 |
||
3:0 |
MASK |
Mask on data address when matching against COMP0. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP0. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be within the word. |
RW |
0x0 |
Address offset |
0x0000 0028 |
||
Physical address |
0xE000 1028 |
Instance |
CPU_DWT |
Description |
DWT Function Register 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:25 |
RESERVED25 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x00 |
||
24 |
MATCHED |
This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. |
RW |
0 |
||
23:8 |
RESERVED8 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 |
||
7 |
CYCMATCH |
This bit is only available in comparator 0. When set, COMP0 will compare against the cycle counter (CYCCNT). |
RW |
0 |
||
6 |
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
||
5 |
EMITRANGE |
Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. |
RW |
0 |
||
4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
||
3:0 |
FUNCTION |
Function settings. |
RW |
0x0 |
Address offset |
0x0000 0030 |
||
Physical address |
0xE000 1030 |
Instance |
CPU_DWT |
Description |
DWT Comparator Register 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
COMP |
Reference value to compare against PC or the data address as given by FUNCTION1. |
RW |
0x0000 0000 |
Address offset |
0x0000 0034 |
||
Physical address |
0xE000 1034 |
Instance |
CPU_DWT |
Description |
DWT Mask Register 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x000 0000 |
||
3:0 |
MASK |
Mask on data address when matching against COMP1. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP1. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be within the word. |
RW |
0x0 |
Address offset |
0x0000 0038 |
||
Physical address |
0xE000 1038 |
Instance |
CPU_DWT |
Description |
DWT Function Register 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:25 |
RESERVED25 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x00 |
||
24 |
MATCHED |
This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. |
RW |
0 |
||
23:20 |
RESERVED20 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 |
||
19:16 |
DATAVADDR1 |
Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1. |
RW |
0x0 |
||
15:12 |
DATAVADDR0 |
Identity of a linked address comparator for data value matching when DATAVMATCH == 1. |
RW |
0x0 |
||
11:10 |
DATAVSIZE |
Defines the size of the data in the COMP1 register that is to be matched: |
RW |
0x0 |
||
9 |
LNK1ENA |
Read only bit-field only supported in comparator 1. |
RO |
1 |
||
8 |
DATAVMATCH |
Data match feature: |
RW |
0 |
||
7:6 |
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 |
||
5 |
EMITRANGE |
Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. |
RW |
0 |
||
4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
||
3:0 |
FUNCTION |
Function settings: |
RW |
0x0 |
Address offset |
0x0000 0040 |
||
Physical address |
0xE000 1040 |
Instance |
CPU_DWT |
Description |
DWT Comparator Register 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
COMP |
Reference value to compare against PC or the data address as given by FUNCTION2. |
RW |
0x0000 0000 |
Address offset |
0x0000 0044 |
||
Physical address |
0xE000 1044 |
Instance |
CPU_DWT |
Description |
DWT Mask Register 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x000 0000 |
||
3:0 |
MASK |
Mask on data address when matching against COMP2. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP2. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be within the word. |
RW |
0x0 |
Address offset |
0x0000 0048 |
||
Physical address |
0xE000 1048 |
Instance |
CPU_DWT |
Description |
DWT Function Register 2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:25 |
RESERVED25 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
||
24 |
MATCHED |
This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. |
RW |
0 |
||
23:6 |
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0 0000 |
||
5 |
EMITRANGE |
Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. |
RW |
0 |
||
4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0 |
||
3:0 |
FUNCTION |
Function settings. |
RW |
0x0 |
Address offset |
0x0000 0050 |
||
Physical address |
0xE000 1050 |
Instance |
CPU_DWT |
Description |
DWT Comparator Register 3 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
COMP |
Reference value to compare against PC or the data address as given by FUNCTION3. |
RW |
0x0000 0000 |
Address offset |
0x0000 0054 |
||
Physical address |
0xE000 1054 |
Instance |
CPU_DWT |
Description |
DWT Mask Register 3 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x000 0000 |
||
3:0 |
MASK |
Mask on data address when matching against COMP3. This is the size of the ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) == COMP3. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be within the word. |
RW |
0x0 |
Address offset |
0x0000 0058 |
||
Physical address |
0xE000 1058 |
Instance |
CPU_DWT |
Description |
DWT Function Register 3 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:25 |
RESERVED25 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x00 |
||
24 |
MATCHED |
This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read. |
RW |
0 |
||
23:6 |
RESERVED6 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0x0 0000 |
||
5 |
EMITRANGE |
Emit range field. This bit permits emitting offset when range match occurs. PC sampling is not supported when emit range is enabled. |
RW |
0 |
||
4 |
RESERVED4 |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RW |
0 |
||
3:0 |
FUNCTION |
Function settings. |
RW |
0x0 |
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