Instance: AUX_WUC
Component: AUX_WUC
Base address: 0x400c6000
AUX Wake-up controller
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 6000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x400C 6004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x400C 6008 |
|
RO |
32 |
0x0000 0000 |
0x0000 000C |
0x400C 600C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 6010 |
|
RO |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C 6014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0020 |
0x400C 6020 |
|
RO |
32 |
0x0000 0000 |
0x0000 0024 |
0x400C 6024 |
|
RO |
32 |
0x0000 0000 |
0x0000 0028 |
0x400C 6028 |
|
RW |
32 |
0x0000 0000 |
0x0000 002C |
0x400C 602C |
|
RW |
32 |
0x0000 0000 |
0x0000 0030 |
0x400C 6030 |
|
RW |
32 |
0x0000 0000 |
0x0000 0034 |
0x400C 6034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x400C 6038 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x400C 603C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x400C 6040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x400C 6044 |
|
RW |
32 |
0x0000 0000 |
0x0000 0048 |
0x400C 6048 |
|
RO |
32 |
0x0000 0000 |
0x0000 004C |
0x400C 604C |
|
RO |
32 |
0x0000 0000 |
0x0000 0050 |
0x400C 6050 |
|
RW |
32 |
0x0000 0000 |
0x0000 0054 |
0x400C 6054 |
|
RW |
32 |
0x0000 0000 |
0x0000 005C |
0x400C 605C |
Address offset |
0x0000 0000 |
||
Physical address |
0x400C 6000 |
Instance |
AUX_WUC |
Description |
Module Clock Enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||
7 |
AUX_ADI4 |
Enables (1) or disables (0) clock for AUX_ADI4.
|
RW |
0 |
|||||||||||||
6 |
AUX_DDI0_OSC |
Enables (1) or disables (0) clock for AUX_DDI0_OSC.
|
RW |
0 |
|||||||||||||
5 |
TDC |
Enables (1) or disables (0) clock for AUX_TDCIF.
|
RW |
0 |
|||||||||||||
4 |
SOC |
Enables (1) or disables (0) clock for AUX_SOC.
|
RW |
0 |
|||||||||||||
3 |
TIMER |
Enables (1) or disables (0) clock for AUX_TIMER.
|
RW |
0 |
|||||||||||||
2 |
AIODIO1 |
Enables (1) or disables (0) clock for AUX_AIODIO1.
|
RW |
0 |
|||||||||||||
1 |
AIODIO0 |
Enables (1) or disables (0) clock for AUX_AIODIO0.
|
RW |
0 |
|||||||||||||
0 |
SMPH |
Enables (1) or disables (0) clock for AUX_SMPH.
|
RW |
0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x400C 6004 |
Instance |
AUX_WUC |
Description |
Power Off Request |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
REQ |
Power off request |
RW |
0 |
Address offset |
0x0000 0008 |
||
Physical address |
0x400C 6008 |
Instance |
AUX_WUC |
Description |
Power Down Request |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
REQ |
Power down request |
RW |
0 |
Address offset |
0x0000 000C |
||
Physical address |
0x400C 600C |
Instance |
AUX_WUC |
Description |
Power Down Acknowledgment |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ACK |
Power down acknowledgment. Indicates whether the power down request given by PWRDWNREQ.REQ is captured by the AON domain or not |
RO |
0 |
Address offset |
0x0000 0010 |
||
Physical address |
0x400C 6010 |
Instance |
AUX_WUC |
Description |
Low Frequency Clock Request |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
REQ |
Low frequency request |
RW |
0 |
Address offset |
0x0000 0014 |
||
Physical address |
0x400C 6014 |
Instance |
AUX_WUC |
Description |
Low Frequency Clock Acknowledgment |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ACK |
Acknowledgment of CLKLFREQ.REQ |
RO |
0 |
Address offset |
0x0000 0020 |
||
Physical address |
0x400C 6020 |
Instance |
AUX_WUC |
Description |
Band Gap Request |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
REQ |
AUX_SCE request for band gap reference. |
RW |
0 |
Address offset |
0x0000 0024 |
||
Physical address |
0x400C 6024 |
Instance |
AUX_WUC |
Description |
Band Gap Acknowledgment |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
ACK |
Acknowledgment of AUX_SCE band gap reference request. |
RO |
0 |
Address offset |
0x0000 0028 |
||
Physical address |
0x400C 6028 |
Instance |
AUX_WUC |
Description |
Wake-up Event Flags |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
AON_RTC_CH2 |
Indicates pending event from AON_RTC_CH2 compare. Note that this flag will be set whenever the AON_RTC_CH2 event happens, but that does not mean that this event is a wake-up event. To make the AON_RTC_CH2 a wake-up event for the AUX domain configure it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV or AON_EVENT:AUXWUSEL.WU2_EV. |
RO |
0 |
||
1 |
AON_SW |
Indicates pending event triggered by system CPU writing a 1 to AON_WUC:AUXCTL.SWEV. |
RO |
0 |
||
0 |
AON_PROG_WU |
Indicates pending event triggered by the sources selected in AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV and AON_EVENT:AUXWUSEL.WU2_EV. |
RO |
0 |
Address offset |
0x0000 002C |
||
Physical address |
0x400C 602C |
Instance |
AUX_WUC |
Description |
Wake-up Event Clear |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:3 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
2 |
AON_RTC_CH2 |
Set to clear the WUEVFLAGS.AON_RTC_CH2 wake-up event. Note that if RTC channel 2 is also set as source for AON_PROG_WU this field can also clear WUEVFLAGS.AON_PROG_WU |
RW |
0 |
||
1 |
AON_SW |
Set to clear the WUEVFLAGS.AON_SW wake-up event. |
RW |
0 |
||
0 |
AON_PROG_WU |
Set to clear the WUEVFLAGS.AON_PROG_WU wake-up event. Note only if an IO event is selected as wake-up event, is it possible to use this field to clear the source. Other sources cannot be cleared using this field. |
RW |
0 |
Address offset |
0x0000 0030 |
||
Physical address |
0x400C 6030 |
Instance |
AUX_WUC |
Description |
ADC Clock Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
ACK |
Acknowledges the last value written to REQ. |
RO |
0 |
||
0 |
REQ |
Enables(1) or disables (0) the ADC internal clock. |
RW |
0 |
Address offset |
0x0000 0034 |
||
Physical address |
0x400C 6034 |
Instance |
AUX_WUC |
Description |
TDC Clock Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
RESERVED |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RO |
0x0000 0000 |
||
1 |
ACK |
Acknowledges the last value written to REQ. |
RO |
0 |
||
0 |
REQ |
Enables(1) or disables (0) the TDC counter clock source. |
RW |
0 |
Address offset |
0x0000 0038 |
||
Physical address |
0x400C 6038 |
Instance |
AUX_WUC |
Description |
Reference Clock Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
ACK |
Acknowledges the last value written to REQ. |
RO |
0 |
||
0 |
REQ |
Enables(1) or disables (0) the TDC reference clock source. |
RW |
0 |
Address offset |
0x0000 003C |
||
Physical address |
0x400C 603C |
Instance |
AUX_WUC |
Description |
Real Time Counter Sub Second Increment 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
INC15_0 |
Bits 15:0 of the RTC sub-second increment value. |
RW |
0x0000 |
Address offset |
0x0000 0040 |
||
Physical address |
0x400C 6040 |
Instance |
AUX_WUC |
Description |
Real Time Counter Sub Second Increment 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
||
7:0 |
INC23_16 |
Bits 23:16 of the RTC sub-second increment value. |
RW |
0x00 |
Address offset |
0x0000 0044 |
||
Physical address |
0x400C 6044 |
Instance |
AUX_WUC |
Description |
Real Time Counter Sub Second Increment Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
UPD_ACK |
Acknowledgment of the UPD_REQ. |
RO |
0 |
||
0 |
UPD_REQ |
Signal that a new real time counter sub second increment value is available |
RW |
0 |
Address offset |
0x0000 0048 |
||
Physical address |
0x400C 6048 |
Instance |
AUX_WUC |
Description |
MCU Bus Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
DISCONNECT_REQ |
Requests the AUX domain bus to be disconnected from the MCU domain bus. The request has no effect when AON_WUC:AUX_CTL.AUX_FORCE_ON is set. |
RW |
0 |
Address offset |
0x0000 004C |
||
Physical address |
0x400C 604C |
Instance |
AUX_WUC |
Description |
MCU Bus Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
DISCONNECTED |
Indicates whether the AUX domain and MCU domain buses are currently disconnected (1) or connected (0). |
RO |
0 |
||
0 |
DISCONNECT_ACK |
Acknowledges reception of the bus disconnection request, by matching the value of MCUBUSCTL.DISCONNECT_REQ. |
RO |
0 |
Address offset |
0x0000 0050 |
||
Physical address |
0x400C 6050 |
Instance |
AUX_WUC |
Description |
AON Domain Control Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
1 |
AUX_FORCE_ON |
Status of AON_WUC:AUX_CTL.AUX_FORCE_ON. |
RO |
0 |
||
0 |
SCE_RUN_EN |
Status of AON_WUC:AUX_CTL.SCE_RUN_EN. |
RO |
0 |
Address offset |
0x0000 0054 |
||
Physical address |
0x400C 6054 |
Instance |
AUX_WUC |
Description |
AUX Input Output Latch |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||
0 |
EN |
Opens (1) or closes (0) the AUX_AIODIO0/AUX_AIODIO1 signal latching.
|
RW |
0 |
Address offset |
0x0000 005C |
||
Physical address |
0x400C 605C |
Instance |
AUX_WUC |
Description |
Module Clock Enable 1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||
31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||
7 |
AUX_ADI4 |
Enables (1) or disables (0) clock for AUX_ADI4.
|
RW |
0 |
|||||||||||||
6 |
AUX_DDI0_OSC |
Enables (1) or disables (0) clock for AUX_DDI0_OSC.
|
RW |
0 |
|||||||||||||
5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RW std text) |
RW |
0 |
|||||||||||||
4 |
SOC |
Enables (1) or disables (0) clock for AUX_SOC.
|
RW |
0 |
|||||||||||||
3 |
TIMER |
Enables (1) or disables (0) clock for AUX_TIMER.
|
RW |
0 |
|||||||||||||
2 |
AIODIO1 |
Enables (1) or disables (0) clock for AUX_AIODIO1.
|
RW |
0 |
|||||||||||||
1 |
AIODIO0 |
Enables (1) or disables (0) clock for AUX_AIODIO0.
|
RW |
0 |
|||||||||||||
0 |
SMPH |
Enables (1) or disables (0) clock for AUX_SMPH.
|
RW |
0 |
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