Instance: AUX_ANAIF
Component: AUX_ANAIF
Base address: 0x400c9000
AUX Analog Peripheral Control Module
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 9010 |
|
RO |
32 |
0x0000 0001 |
0x0000 0014 |
0x400C 9014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 9018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x400C 901C |
|
RW |
32 |
0x0000 0001 |
0x0000 0020 |
0x400C 9020 |
Address offset |
0x0000 0010 |
||
Physical address |
0x400C 9010 |
Instance |
AUX_ANAIF |
Description |
ADC Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
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31:14 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
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13 |
START_POL |
Selected active edge for start event / Selected polarity for start event
|
RW |
0 |
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12:8 |
START_SRC |
Selected source for ADC conversion start event. The start source selected by this field is OR'ed with any trigger coming from writes to ADCTRIG.START. If it is desired to only trigger ADC conversions by writes to ADCTRIG.START one should select NO_EVENT
|
RW |
0x00 |
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7:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
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1:0 |
CMD |
ADC interface control command
|
RW |
0x0 |
Address offset |
0x0000 0014 |
||
Physical address |
0x400C 9014 |
Instance |
AUX_ANAIF |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
||
4 |
OVERFLOW |
FIFO overflow flag. |
RO |
0 |
||
3 |
UNDERFLOW |
FIFO underflow flag. |
RO |
0 |
||
2 |
FULL |
FIFO full flag. |
RO |
0 |
||
1 |
ALMOST_FULL |
FIFO almost full flag. |
RO |
0 |
||
0 |
EMPTY |
FIFO empty flag. |
RO |
1 |
Address offset |
0x0000 0018 |
||
Physical address |
0x400C 9018 |
Instance |
AUX_ANAIF |
Description |
ADC FIFO |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:12 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
||
11:0 |
DATA |
FIFO is popped when read. Data is pushed into FIFO when written. Writing is intended for debugging/code development purposes |
RW |
0x000 |
Address offset |
0x0000 001C |
||
Physical address |
0x400C 901C |
Instance |
AUX_ANAIF |
Description |
ADC Trigger |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
START |
Writing to this register will trigger an ADC conversion given that ADCCTL.START_SRC is set to NO_EVENT0 or NO_EVENT1. If other setting is used in ADCCTL.START_SRC behavior can be unpredictable |
WO |
0 |
Address offset |
0x0000 0020 |
||
Physical address |
0x400C 9020 |
Instance |
AUX_ANAIF |
Description |
Current Source Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
RESET_N |
Current source control |
RW |
1 |
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