Instance: AUX_TDCIF
Component: AUX_TDC
Base address: 0x400c4000
AUX Time To Digital Converter
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 4000 |
|
RO |
32 |
0x0000 0006 |
0x0000 0004 |
0x400C 4004 |
|
RO |
32 |
0x0000 0002 |
0x0000 0008 |
0x400C 4008 |
|
RW |
32 |
0x0000 000F |
0x0000 000C |
0x400C 400C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 4010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C 4014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 4018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x400C 401C |
|
RW |
32 |
0x0000 001F |
0x0000 0020 |
0x400C 4020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x400C 4024 |
Address offset |
0x0000 0000 |
||
Physical address |
0x400C 4000 |
Instance |
AUX_TDCIF |
Description |
Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:2 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
|||||||||||||||||||||
1:0 |
CMD |
TDC command strobes
|
WO |
0x0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x400C 4004 |
Instance |
AUX_TDCIF |
Description |
Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||
31:10 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||
9 |
Reserved |
RO |
0 |
||||||||||||||||||||||||||||||||||||||||||||||||||
8 |
Reserved |
RO |
0 |
||||||||||||||||||||||||||||||||||||||||||||||||||
7 |
SAT |
Saturation flag for TDC measurement |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||
6 |
DONE |
Measurement complete flag |
RO |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||
5:0 |
STATE |
TDC internal state machine status
|
RO |
0x06 |
Address offset |
0x0000 0008 |
||
Physical address |
0x400C 4008 |
Instance |
AUX_TDCIF |
Description |
Result |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:25 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 |
||
24:0 |
VALUE |
Result of the TDC conversion. The result is in clock edges of the clock selected in [OSC_DIG.CTL0.ACLK_TDC_SRC_SEL]. Both rising and falling edges are counted. |
RO |
0x000 0002 |
Address offset |
0x0000 000C |
||
Physical address |
0x400C 400C |
Instance |
AUX_TDCIF |
Description |
Saturation Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||
31:4 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 |
LIMIT |
Select when the TDC should time out. Values not enumerated is not supported
|
RW |
0xF |
Address offset |
0x0000 0010 |
||
Physical address |
0x400C 4010 |
Instance |
AUX_TDCIF |
Description |
Trigger Source |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:14 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 0000 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 |
STOP_POL |
Polarity of stop signal. Note! Must not be changed if STAT.STATE is not IDLE
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12:8 |
STOP_SRC |
Selects the asynchronous stop signal Note! Must not be changed if STAT.STATE is not IDLE
|
RW |
0x00 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 |
START_POL |
Polarity of start signal. Note! Must not be changed if STAT.STATE is not IDLE
|
RW |
0 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 |
START_SRC |
Selects the asynchronous start signal Note! Must not be changed if STAT.STATE is not IDLE
|
RW |
0x00 |
Address offset |
0x0000 0014 |
||
Physical address |
0x400C 4014 |
Instance |
AUX_TDCIF |
Description |
Trigger Counter |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
CNT |
Remaining number of stop events that will be ignored. Writing to this register updates the value. The CNT will be loaded with the value of TRIGCNTLOAD.CNT at the start of every measurement. |
RW |
0x0000 |
Address offset |
0x0000 0018 |
||
Physical address |
0x400C 4018 |
Instance |
AUX_TDCIF |
Description |
Trigger Counter Load |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
CNT |
Selects the number of stop events that will be ignored by the TDC. This can be used to measure multiple periods of a clock signal. The value written to this field is loaded into the stop counter at the start of each measurement. |
RW |
0x0000 |
Address offset |
0x0000 001C |
||
Physical address |
0x400C 401C |
Instance |
AUX_TDCIF |
Description |
Trigger Counter Configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:1 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 0000 |
||
0 |
EN |
Stop counter enable |
RW |
0 |
Address offset |
0x0000 0020 |
||
Physical address |
0x400C 4020 |
Instance |
AUX_TDCIF |
Description |
Prescaler Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
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31:8 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
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7 |
RESET_N |
Prescaler reset control |
RW |
0 |
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6 |
RATIO |
Prescaler ratio. This controls how often an event is generated on the TDC_PRE line. After the prescaler is reset the event output TDC_PRE is 0.
|
RW |
0 |
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5 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0 |
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4:0 |
SRC |
Selects event for prescaler to use as input
|
RW |
0x1F |
Address offset |
0x0000 0024 |
||
Physical address |
0x400C 4024 |
Instance |
AUX_TDCIF |
Description |
Prescaler Counter |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:16 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x0000 |
||
15:0 |
CNT |
Writing to this register will latch the contents of the 16 bit prescaler counter (The value written is don't care). |
RW |
0x0000 |
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