Instance: VIMS
Component: VIMS
Base address: 0x40034000
Versatile Instruction Memory System
Controls memory access to the Flash and encapsulates the following instruction memories:
- Boot ROM
- Cache / GPRAM
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x0000 0000 |
0x0000 0000 |
0x4003 4000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4003 4004 |
|
RO |
32 |
0x0000 0000 |
0x0000 0100 |
0x4003 4100 |
|
RO |
32 |
0x0000 0000 |
0x0000 0104 |
0x4003 4104 |
|
RO |
32 |
0x0000 0000 |
0x0000 0108 |
0x4003 4108 |
|
RO |
32 |
0x0000 0000 |
0x0000 010C |
0x4003 410C |
|
RO |
32 |
0x0000 0000 |
0x0000 0110 |
0x4003 4110 |
|
RO |
32 |
0x0000 0000 |
0x0000 0114 |
0x4003 4114 |
Address offset |
0x0000 0000 |
||
Physical address |
0x4003 4000 |
Instance |
VIMS |
Description |
Status |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x000 0000 |
|||||||||||||||||||||
5 |
IDCODE_LB_DIS |
Icode/Dcode flash line buffer status |
RO |
0 |
|||||||||||||||||||||
4 |
SYSBUS_LB_DIS |
Sysbus flash line buffer control |
RO |
0 |
|||||||||||||||||||||
3 |
MODE_CHANGING |
VIMS mode change status |
RO |
0 |
|||||||||||||||||||||
2 |
INV |
This bit is set when invalidation of the cache memory is active / ongoing |
RO |
0 |
|||||||||||||||||||||
1:0 |
MODE |
Current VIMS mode
|
RO |
0x0 |
Address offset |
0x0000 0004 |
||
Physical address |
0x4003 4004 |
Instance |
VIMS |
Description |
Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|||||||||||||||||||||
31 |
STATS_CLR |
Set this bit to clear statistic counters. |
RW |
0 |
|||||||||||||||||||||
30 |
STATS_EN |
Set this bit to enable statistic counters. |
RW |
0 |
|||||||||||||||||||||
29 |
DYN_CG_EN |
Internal field controlled by TI provided startup code |
RW |
0 |
|||||||||||||||||||||
28:6 |
Reserved |
Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text) |
RO |
0x00 0000 |
|||||||||||||||||||||
5 |
IDCODE_LB_DIS |
Icode/Dcode flash line buffer control |
RW |
0 |
|||||||||||||||||||||
4 |
SYSBUS_LB_DIS |
Sysbus flash line buffer control |
RW |
0 |
|||||||||||||||||||||
3 |
ARB_CFG |
Icode/Dcode and sysbus arbitation scheme |
RW |
0 |
|||||||||||||||||||||
2 |
PREF_EN |
Tag prefetch control |
RW |
0 |
|||||||||||||||||||||
1:0 |
MODE |
Internal field controlled by TI provided startup code
|
RW |
0x0 |
Address offset |
0x0000 0100 |
||
Physical address |
0x4003 4100 |
Instance |
VIMS |
Description |
Cache Statistics |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
HIT |
Cache hit counter (not incuding cache line bufffer accesses) |
RO |
0x0000 0000 |
Address offset |
0x0000 0104 |
||
Physical address |
0x4003 4104 |
Instance |
VIMS |
Description |
Cache Statistics |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
MISS |
Cache miss counter (not incuding cache line bufffer accesses) |
RO |
0x0000 0000 |
Address offset |
0x0000 0108 |
||
Physical address |
0x4003 4108 |
Instance |
VIMS |
Description |
Cache Statistics |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
LB_HIT |
Cache line buffer hit counter |
RO |
0x0000 0000 |
Address offset |
0x0000 010C |
||
Physical address |
0x4003 410C |
Instance |
VIMS |
Description |
Cache Statistics |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
PREF_HIT |
Tag prefetch hit counter |
RO |
0x0000 0000 |
Address offset |
0x0000 0110 |
||
Physical address |
0x4003 4110 |
Instance |
VIMS |
Description |
Cache Statistics |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
ICODE_STALL |
Icode stall counter |
RO |
0x0000 0000 |
Address offset |
0x0000 0114 |
||
Physical address |
0x4003 4114 |
Instance |
VIMS |
Description |
Cache Statistics |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
||
31:0 |
DCODE_STALL |
Dcode stall counter |
RO |
0x0000 0000 |
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