RFC_PHA

Instance: RFC_PHA
Component: RFC_PHA
Base address: 0x40042000

 

Component for pha register bank

 

TOP:RFC_PHA Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

PHAPOLY0

RW

32

0x0000 0000

0x0000 0000

0x4004 2000

PHAPOLY1

RW

32

0x0000 0000

0x0000 0004

0x4004 2004

PHACFG

RW

32

0x0000 0000

0x0000 0010

0x4004 2010

PHASTA

RO

32

0x0000 0000

0x0000 0014

0x4004 2014

PHALFSR0VAL

RW

32

0xFFFF FFFF

0x0000 0020

0x4004 2020

PHALFSR1VAL

RW

32

0xFFFF FFFF

0x0000 0024

0x4004 2024

PHALFSR0VALBR

RW

32

0xFFFF FFFF

0x0000 0030

0x4004 2030

PHALFSR1VALBR

RW

32

0xFFFF FFFF

0x0000 0034

0x4004 2034

PHAOUT0

RW

32

0x0000 0000

0x0000 0040

0x4004 2040

PHAOUT0BR

RO

32

0x0000 0000

0x0000 0048

0x4004 2048

PHAHAMENCIN

RW

32

0x0000 0000

0x0000 0050

0x4004 2050

PHAHAMENCOUT

RO

32

0x0000 0000

0x0000 0054

0x4004 2054

PHAHAMDECIN

RW

32

0x0000 0000

0x0000 0058

0x4004 2058

PHAHAMDECOUT

RO

32

0x0000 0000

0x0000 005C

0x4004 205C

PHALFSR0INL1

RW

32

0x0000 0000

0x0000 0100

0x4004 2100

PHALFSR0INL2

RW

32

0x0000 0000

0x0000 0104

0x4004 2104

PHALFSR0INL3

RW

32

0x0000 0000

0x0000 0108

0x4004 2108

PHALFSR0INL4

RW

32

0x0000 0000

0x0000 010C

0x4004 210C

PHALFSR0INL5

RW

32

0x0000 0000

0x0000 0110

0x4004 2110

PHALFSR0INL6

RW

32

0x0000 0000

0x0000 0114

0x4004 2114

PHALFSR0INL7

RW

32

0x0000 0000

0x0000 0118

0x4004 2118

PHALFSR0INL8

RW

32

0x0000 0000

0x0000 011C

0x4004 211C

PHALFSR0INL9

RW

32

0x0000 0000

0x0000 0120

0x4004 2120

PHALFSR0INL10

RW

32

0x0000 0000

0x0000 0124

0x4004 2124

PHALFSR0INL11

RW

32

0x0000 0000

0x0000 0128

0x4004 2128

PHALFSR0INL12

RW

32

0x0000 0000

0x0000 012C

0x4004 212C

PHALFSR0INL13

RW

32

0x0000 0000

0x0000 0130

0x4004 2130

PHALFSR0INL14

RW

32

0x0000 0000

0x0000 0134

0x4004 2134

PHALFSR0INL15

RW

32

0x0000 0000

0x0000 0138

0x4004 2138

PHALFSR0INL16

RW

32

0x0000 0000

0x0000 013C

0x4004 213C

PHALFSR0INL17

RW

32

0x0000 0000

0x0000 0140

0x4004 2140

PHALFSR0INL18

RW

32

0x0000 0000

0x0000 0144

0x4004 2144

PHALFSR0INL19

RW

32

0x0000 0000

0x0000 0148

0x4004 2148

PHALFSR0INL20

RW

32

0x0000 0000

0x0000 014C

0x4004 214C

PHALFSR0INL21

RW

32

0x0000 0000

0x0000 0150

0x4004 2150

PHALFSR0INL22

RW

32

0x0000 0000

0x0000 0154

0x4004 2154

PHALFSR0INL23

RW

32

0x0000 0000

0x0000 0158

0x4004 2158

PHALFSR0INL24

RW

32

0x0000 0000

0x0000 015C

0x4004 215C

PHALFSR0INL25

RW

32

0x0000 0000

0x0000 0160

0x4004 2160

PHALFSR0INL26

RW

32

0x0000 0000

0x0000 0164

0x4004 2164

PHALFSR0INL27

RW

32

0x0000 0000

0x0000 0168

0x4004 2168

PHALFSR0INL28

RW

32

0x0000 0000

0x0000 016C

0x4004 216C

PHALFSR0INL29

RW

32

0x0000 0000

0x0000 0170

0x4004 2170

PHALFSR0INL30

RW

32

0x0000 0000

0x0000 0174

0x4004 2174

PHALFSR0INL31

RW

32

0x0000 0000

0x0000 0178

0x4004 2178

PHALFSR0INL32

RW

32

0x0000 0000

0x0000 017C

0x4004 217C

PHALFSR0INM1

RW

32

0x0000 0000

0x0000 0180

0x4004 2180

PHALFSR0INM2

RW

32

0x0000 0000

0x0000 0184

0x4004 2184

PHALFSR0INM3

RW

32

0x0000 0000

0x0000 0188

0x4004 2188

PHALFSR0INM4

RW

32

0x0000 0000

0x0000 018C

0x4004 218C

PHALFSR0INM5

RW

32

0x0000 0000

0x0000 0190

0x4004 2190

PHALFSR0INM6

RW

32

0x0000 0000

0x0000 0194

0x4004 2194

PHALFSR0INM7

RW

32

0x0000 0000

0x0000 0198

0x4004 2198

PHALFSR0INM8

RW

32

0x0000 0000

0x0000 019C

0x4004 219C

PHALFSR0INM9

RW

32

0x0000 0000

0x0000 01A0

0x4004 21A0

PHALFSR0INM10

RW

32

0x0000 0000

0x0000 01A4

0x4004 21A4

PHALFSR0INM11

RW

32

0x0000 0000

0x0000 01A8

0x4004 21A8

PHALFSR0INM12

RW

32

0x0000 0000

0x0000 01AC

0x4004 21AC

PHALFSR0INM13

RW

32

0x0000 0000

0x0000 01B0

0x4004 21B0

PHALFSR0INM14

RW

32

0x0000 0000

0x0000 01B4

0x4004 21B4

PHALFSR0INM15

RW

32

0x0000 0000

0x0000 01B8

0x4004 21B8

PHALFSR0INM16

RW

32

0x0000 0000

0x0000 01BC

0x4004 21BC

PHALFSR0INM17

RW

32

0x0000 0000

0x0000 01C0

0x4004 21C0

PHALFSR0INM18

RW

32

0x0000 0000

0x0000 01C4

0x4004 21C4

PHALFSR0INM19

RW

32

0x0000 0000

0x0000 01C8

0x4004 21C8

PHALFSR0INM20

RW

32

0x0000 0000

0x0000 01CC

0x4004 21CC

PHALFSR0INM21

RW

32

0x0000 0000

0x0000 01D0

0x4004 21D0

PHALFSR0INM22

RW

32

0x0000 0000

0x0000 01D4

0x4004 21D4

PHALFSR0INM23

RW

32

0x0000 0000

0x0000 01D8

0x4004 21D8

PHALFSR0INM24

RW

32

0x0000 0000

0x0000 01DC

0x4004 21DC

PHALFSR0INM25

RW

32

0x0000 0000

0x0000 01E0

0x4004 21E0

PHALFSR0INM26

RW

32

0x0000 0000

0x0000 01E4

0x4004 21E4

PHALFSR0INM27

RW

32

0x0000 0000

0x0000 01E8

0x4004 21E8

PHALFSR0INM28

RW

32

0x0000 0000

0x0000 01EC

0x4004 21EC

PHALFSR0INM29

RW

32

0x0000 0000

0x0000 01F0

0x4004 21F0

PHALFSR0INM30

RW

32

0x0000 0000

0x0000 01F4

0x4004 21F4

PHALFSR0INM31

RW

32

0x0000 0000

0x0000 01F8

0x4004 21F8

PHALFSR0INM32

RW

32

0x0000 0000

0x0000 01FC

0x4004 21FC

PHALFSR1INL1

RW

32

0x0000 0000

0x0000 0200

0x4004 2200

PHALFSR1INL2

RW

32

0x0000 0000

0x0000 0204

0x4004 2204

PHALFSR1INL3

RW

32

0x0000 0000

0x0000 0208

0x4004 2208

PHALFSR1INL4

RW

32

0x0000 0000

0x0000 020C

0x4004 220C

PHALFSR1INL5

RW

32

0x0000 0000

0x0000 0210

0x4004 2210

PHALFSR1INL6

RW

32

0x0000 0000

0x0000 0214

0x4004 2214

PHALFSR1INL7

RW

32

0x0000 0000

0x0000 0218

0x4004 2218

PHALFSR1INL8

RW

32

0x0000 0000

0x0000 021C

0x4004 221C

PHALFSR1INL9

RW

32

0x0000 0000

0x0000 0220

0x4004 2220

PHALFSR1INL10

RW

32

0x0000 0000

0x0000 0224

0x4004 2224

PHALFSR1INL11

RW

32

0x0000 0000

0x0000 0228

0x4004 2228

PHALFSR1INL12

RW

32

0x0000 0000

0x0000 022C

0x4004 222C

PHALFSR1INL13

RW

32

0x0000 0000

0x0000 0230

0x4004 2230

PHALFSR1INL14

RW

32

0x0000 0000

0x0000 0234

0x4004 2234

PHALFSR1INL15

RW

32

0x0000 0000

0x0000 0238

0x4004 2238

PHALFSR1INL16

RW

32

0x0000 0000

0x0000 023C

0x4004 223C

PHALFSR1INL17

RW

32

0x0000 0000

0x0000 0240

0x4004 2240

PHALFSR1INL18

RW

32

0x0000 0000

0x0000 0244

0x4004 2244

PHALFSR1INL19

RW

32

0x0000 0000

0x0000 0248

0x4004 2248

PHALFSR1INL20

RW

32

0x0000 0000

0x0000 024C

0x4004 224C

PHALFSR1INL21

RW

32

0x0000 0000

0x0000 0250

0x4004 2250

PHALFSR1INL22

RW

32

0x0000 0000

0x0000 0254

0x4004 2254

PHALFSR1INL23

RW

32

0x0000 0000

0x0000 0258

0x4004 2258

PHALFSR1INL24

RW

32

0x0000 0000

0x0000 025C

0x4004 225C

PHALFSR1INL25

RW

32

0x0000 0000

0x0000 0260

0x4004 2260

PHALFSR1INL26

RW

32

0x0000 0000

0x0000 0264

0x4004 2264

PHALFSR1INL27

RW

32

0x0000 0000

0x0000 0268

0x4004 2268

PHALFSR1INL28

RW

32

0x0000 0000

0x0000 026C

0x4004 226C

PHALFSR1INL29

RW

32

0x0000 0000

0x0000 0270

0x4004 2270

PHALFSR1INL30

RW

32

0x0000 0000

0x0000 0274

0x4004 2274

PHALFSR1INL31

RW

32

0x0000 0000

0x0000 0278

0x4004 2278

PHALFSR1INL32

RW

32

0x0000 0000

0x0000 027C

0x4004 227C

PHALFSR1INM1

RW

32

0x0000 0000

0x0000 0280

0x4004 2280

PHALFSR1INM2

RW

32

0x0000 0000

0x0000 0284

0x4004 2284

PHALFSR1INM3

RW

32

0x0000 0000

0x0000 0288

0x4004 2288

PHALFSR1INM4

RW

32

0x0000 0000

0x0000 028C

0x4004 228C

PHALFSR1INM5

RW

32

0x0000 0000

0x0000 0290

0x4004 2290

PHALFSR1INM6

RW

32

0x0000 0000

0x0000 0294

0x4004 2294

PHALFSR1INM7

RW

32

0x0000 0000

0x0000 0298

0x4004 2298

PHALFSR1INM8

RW

32

0x0000 0000

0x0000 029C

0x4004 229C

PHALFSR1INM9

RW

32

0x0000 0000

0x0000 02A0

0x4004 22A0

PHALFSR1INM10

RW

32

0x0000 0000

0x0000 02A4

0x4004 22A4

PHALFSR1INM11

RW

32

0x0000 0000

0x0000 02A8

0x4004 22A8

PHALFSR1INM12

RW

32

0x0000 0000

0x0000 02AC

0x4004 22AC

PHALFSR1INM13

RW

32

0x0000 0000

0x0000 02B0

0x4004 22B0

PHALFSR1INM14

RW

32

0x0000 0000

0x0000 02B4

0x4004 22B4

PHALFSR1INM15

RW

32

0x0000 0000

0x0000 02B8

0x4004 22B8

PHALFSR1INM16

RW

32

0x0000 0000

0x0000 02BC

0x4004 22BC

PHALFSR1INM17

RW

32

0x0000 0000

0x0000 02C0

0x4004 22C0

PHALFSR1INM18

RW

32

0x0000 0000

0x0000 02C4

0x4004 22C4

PHALFSR1INM19

RW

32

0x0000 0000

0x0000 02C8

0x4004 22C8

PHALFSR1INM20

RW

32

0x0000 0000

0x0000 02CC

0x4004 22CC

PHALFSR1INM21

RW

32

0x0000 0000

0x0000 02D0

0x4004 22D0

PHALFSR1INM22

RW

32

0x0000 0000

0x0000 02D4

0x4004 22D4

PHALFSR1INM23

RW

32

0x0000 0000

0x0000 02D8

0x4004 22D8

PHALFSR1INM24

RW

32

0x0000 0000

0x0000 02DC

0x4004 22DC

PHALFSR1INM25

RW

32

0x0000 0000

0x0000 02E0

0x4004 22E0

PHALFSR1INM26

RW

32

0x0000 0000

0x0000 02E4

0x4004 22E4

PHALFSR1INM27

RW

32

0x0000 0000

0x0000 02E8

0x4004 22E8

PHALFSR1INM28

RW

32

0x0000 0000

0x0000 02EC

0x4004 22EC

PHALFSR1INM29

RW

32

0x0000 0000

0x0000 02F0

0x4004 22F0

PHALFSR1INM30

RW

32

0x0000 0000

0x0000 02F4

0x4004 22F4

PHALFSR1INM31

RW

32

0x0000 0000

0x0000 02F8

0x4004 22F8

PHALFSR1INM32

RW

32

0x0000 0000

0x0000 02FC

0x4004 22FC

TOP:RFC_PHA Register Descriptions

TOP:RFC_PHA:PHAPOLY0

Address offset

0x0000 0000

Physical address

0x4004 2000

Instance

RFC_PHA

Description

LFSR 0 Polynomial Definition

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

POLY0

LFSR 0 polynomial taps

RW

0x0000 0000



TOP:RFC_PHA:PHAPOLY1

Address offset

0x0000 0004

Physical address

0x4004 2004

Instance

RFC_PHA

Description

LFSR 1 Polynomial Definition

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

POLY1

LFSR 1 polynomial taps

RW

0x0000 0000



TOP:RFC_PHA:PHACFG

Address offset

0x0000 0010

Physical address

0x4004 2010

Instance

RFC_PHA

Description

Packet Handler Accelerator Config Register

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:1

MODE1

Dual LFSR operating mode

Value

ENUM name

Description

0x0

INDEP

LFSR0 and LFSR1 are operated independently

0x1

CASC

LFSR0 whitener is followed by LFSR1 CRC

0x2

PARAL

LFSR0 and LFSR1 are operated in parallel

RW

0x0

0

MODE0

LFSR 0 operating mode

Value

ENUM name

Description

0

CRC

LFSR 0 is in CRC mode

1

WHITE

LFSR 0 is in whitening mode

RW

0



TOP:RFC_PHA:PHASTA

Address offset

0x0000 0014

Physical address

0x4004 2014

Instance

RFC_PHA

Description

Packet Handler Accelerator Status

Type

RO

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

BUSY

Status busy flags.

Value

ENUM name

Description

0x0

IDLE

LFSR n sub-engine idle

0x1

BUSY

LFSR n sub-engine busy

RO

0x0



TOP:RFC_PHA:PHALFSR0VAL

Address offset

0x0000 0020

Physical address

0x4004 2020

Instance

RFC_PHA

Description

LFSR 0 Current Value

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR0VAL

LFSR 0 value

RW

0xFFFF FFFF



TOP:RFC_PHA:PHALFSR1VAL

Address offset

0x0000 0024

Physical address

0x4004 2024

Instance

RFC_PHA

Description

LFSR 1 Current Value

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR1VAL

LFSR 1 value

RW

0xFFFF FFFF



TOP:RFC_PHA:PHALFSR0VALBR

Address offset

0x0000 0030

Physical address

0x4004 2030

Instance

RFC_PHA

Description

LFSR 0 Current Value, Bit-reversed

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR0VAL

LFSR 0 value, bit reversed order

RW

0xFFFF FFFF



TOP:RFC_PHA:PHALFSR1VALBR

Address offset

0x0000 0034

Physical address

0x4004 2034

Instance

RFC_PHA

Description

LFSR 1 Current Value, Bit-reversed

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR1VAL

LFSR 1 value, bit reversed order

RW

0xFFFF FFFF



TOP:RFC_PHA:PHAOUT0

Address offset

0x0000 0040

Physical address

0x4004 2040

Instance

RFC_PHA

Description

LFSR 0 Output

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

OUT0

Output value of LFSR0

RW

0x0000 0000



TOP:RFC_PHA:PHAOUT0BR

Address offset

0x0000 0048

Physical address

0x4004 2048

Instance

RFC_PHA

Description

LFSR 0 Output, Bit-reversed

Type

RO

Bits

Field Name

Description

Type

Reset

31:0

OUT0

Output value of LFSR0 in bit reversed order

RO

0x0000 0000



TOP:RFC_PHA:PHAHAMENCIN

Address offset

0x0000 0050

Physical address

0x4004 2050

Instance

RFC_PHA

Description

PHA Hamming Encoder Input

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:4

HAMENCIN1

Data to be (8,4,4) extended Hamming encoded. This is a single-error correcting and double-error detecting code.

RW

0x0

3:0

HAMENCIN0

Data to be (8,4,4) extended Hamming encoded. This is a single-error correcting and double-error detecting code.

RW

0x0



TOP:RFC_PHA:PHAHAMENCOUT

Address offset

0x0000 0054

Physical address

0x4004 2054

Instance

RFC_PHA

Description

PHA Hamming Encoder Output

Type

RO

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:8

HAMENCOUT1

When read, the Hamming encoded value of PHAHAMENCIN.HAMENCIN1 register is returned.

RO

0x00

7:0

HAMENCOUT0

When read, the Hamming encoded value of PHAHAMENCIN.HAMENCIN0 register is returned.

RO

0x00



TOP:RFC_PHA:PHAHAMDECIN

Address offset

0x0000 0058

Physical address

0x4004 2058

Instance

RFC_PHA

Description

PHA Hamming Decoder Input

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:8

HAMDECIN1

Data to be (8,4,4) extended Hamming decoded.

RW

0x00

7:0

HAMDECIN0

Data to be (8,4,4) extended Hamming decoded.

RW

0x00



TOP:RFC_PHA:PHAHAMDECOUT

Address offset

0x0000 005C

Physical address

0x4004 205C

Instance

RFC_PHA

Description

PHA Hamming Decoder Output

Type

RO

Bits

Field Name

Description

Type

Reset

31:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

9

HAMERR1

Uncorrected bit errors was detected when decoding PHAHAMDECIN.HAMDECIN1.

RO

0

8

HAMERR0

Uncorrected bit errors was detected when decoding PHAHAMDECIN.HAMDECIN0.

RO

0

7:4

HAMDECOUT1

When read, the decoded value of the PHAHAMDECIN.HAMDECIN1 register is returned.

RO

0x0

3:0

HAMDECOUT0

When read, the decoded value of the PHAHAMDECIN.HAMDECIN0 register is returned.

RO

0x0



TOP:RFC_PHA:PHALFSR0INL1

Address offset

0x0000 0100

Physical address

0x4004 2100

Instance

RFC_PHA

Description

LFSR 0 1-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

LFSR0IN

LFSR 0 input value LSB first

RW

0



TOP:RFC_PHA:PHALFSR0INL2

Address offset

0x0000 0104

Physical address

0x4004 2104

Instance

RFC_PHA

Description

LFSR 0 2-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0



TOP:RFC_PHA:PHALFSR0INL3

Address offset

0x0000 0108

Physical address

0x4004 2108

Instance

RFC_PHA

Description

LFSR 0 3-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0



TOP:RFC_PHA:PHALFSR0INL4

Address offset

0x0000 010C

Physical address

0x4004 210C

Instance

RFC_PHA

Description

LFSR 0 4-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0



TOP:RFC_PHA:PHALFSR0INL5

Address offset

0x0000 0110

Physical address

0x4004 2110

Instance

RFC_PHA

Description

LFSR 0 5-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x00



TOP:RFC_PHA:PHALFSR0INL6

Address offset

0x0000 0114

Physical address

0x4004 2114

Instance

RFC_PHA

Description

LFSR 0 6-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

5:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x00



TOP:RFC_PHA:PHALFSR0INL7

Address offset

0x0000 0118

Physical address

0x4004 2118

Instance

RFC_PHA

Description

LFSR 0 7-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

6:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x00



TOP:RFC_PHA:PHALFSR0INL8

Address offset

0x0000 011C

Physical address

0x4004 211C

Instance

RFC_PHA

Description

LFSR 0 8-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x00



TOP:RFC_PHA:PHALFSR0INL9

Address offset

0x0000 0120

Physical address

0x4004 2120

Instance

RFC_PHA

Description

LFSR 0 9-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x000



TOP:RFC_PHA:PHALFSR0INL10

Address offset

0x0000 0124

Physical address

0x4004 2124

Instance

RFC_PHA

Description

LFSR 0 10-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

9:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x000



TOP:RFC_PHA:PHALFSR0INL11

Address offset

0x0000 0128

Physical address

0x4004 2128

Instance

RFC_PHA

Description

LFSR 0 11-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:11

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

10:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x000



TOP:RFC_PHA:PHALFSR0INL12

Address offset

0x0000 012C

Physical address

0x4004 212C

Instance

RFC_PHA

Description

LFSR 0 12-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

11:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x000



TOP:RFC_PHA:PHALFSR0INL13

Address offset

0x0000 0130

Physical address

0x4004 2130

Instance

RFC_PHA

Description

LFSR 0 13-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

12:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR0INL14

Address offset

0x0000 0134

Physical address

0x4004 2134

Instance

RFC_PHA

Description

LFSR 0 14-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

13:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR0INL15

Address offset

0x0000 0138

Physical address

0x4004 2138

Instance

RFC_PHA

Description

LFSR 0 15-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:15

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

14:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR0INL16

Address offset

0x0000 013C

Physical address

0x4004 213C

Instance

RFC_PHA

Description

LFSR 0 16-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR0INL17

Address offset

0x0000 0140

Physical address

0x4004 2140

Instance

RFC_PHA

Description

LFSR 0 17-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

16:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR0INL18

Address offset

0x0000 0144

Physical address

0x4004 2144

Instance

RFC_PHA

Description

LFSR 0 18-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

17:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR0INL19

Address offset

0x0000 0148

Physical address

0x4004 2148

Instance

RFC_PHA

Description

LFSR 0 19-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:19

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

18:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR0INL20

Address offset

0x0000 014C

Physical address

0x4004 214C

Instance

RFC_PHA

Description

LFSR 0 20-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

19:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR0INL21

Address offset

0x0000 0150

Physical address

0x4004 2150

Instance

RFC_PHA

Description

LFSR 0 21-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:21

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

20:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR0INL22

Address offset

0x0000 0154

Physical address

0x4004 2154

Instance

RFC_PHA

Description

LFSR 0 22-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:22

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

21:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR0INL23

Address offset

0x0000 0158

Physical address

0x4004 2158

Instance

RFC_PHA

Description

LFSR 0 23-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:23

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

22:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR0INL24

Address offset

0x0000 015C

Physical address

0x4004 215C

Instance

RFC_PHA

Description

LFSR 0 24-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR0INL25

Address offset

0x0000 0160

Physical address

0x4004 2160

Instance

RFC_PHA

Description

LFSR 0 25-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:25

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

24:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR0INL26

Address offset

0x0000 0164

Physical address

0x4004 2164

Instance

RFC_PHA

Description

LFSR 0 26-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:26

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

25:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR0INL27

Address offset

0x0000 0168

Physical address

0x4004 2168

Instance

RFC_PHA

Description

LFSR 0 27-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:27

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

26:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR0INL28

Address offset

0x0000 016C

Physical address

0x4004 216C

Instance

RFC_PHA

Description

LFSR 0 28-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

27:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR0INL29

Address offset

0x0000 0170

Physical address

0x4004 2170

Instance

RFC_PHA

Description

LFSR 0 29-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

28:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR0INL30

Address offset

0x0000 0174

Physical address

0x4004 2174

Instance

RFC_PHA

Description

LFSR 0 30-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

29:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR0INL31

Address offset

0x0000 0178

Physical address

0x4004 2178

Instance

RFC_PHA

Description

LFSR 0 31-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

30:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR0INL32

Address offset

0x0000 017C

Physical address

0x4004 217C

Instance

RFC_PHA

Description

LFSR 0 32-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR0IN

LFSR 0 input value LSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR0INM1

Address offset

0x0000 0180

Physical address

0x4004 2180

Instance

RFC_PHA

Description

LFSR 0 1-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

LFSR0INR

LFSR 0 input value MSB first

RW

0



TOP:RFC_PHA:PHALFSR0INM2

Address offset

0x0000 0184

Physical address

0x4004 2184

Instance

RFC_PHA

Description

LFSR 0 2-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0



TOP:RFC_PHA:PHALFSR0INM3

Address offset

0x0000 0188

Physical address

0x4004 2188

Instance

RFC_PHA

Description

LFSR 0 3-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0



TOP:RFC_PHA:PHALFSR0INM4

Address offset

0x0000 018C

Physical address

0x4004 218C

Instance

RFC_PHA

Description

LFSR 0 4-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0



TOP:RFC_PHA:PHALFSR0INM5

Address offset

0x0000 0190

Physical address

0x4004 2190

Instance

RFC_PHA

Description

LFSR 0 5-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x00



TOP:RFC_PHA:PHALFSR0INM6

Address offset

0x0000 0194

Physical address

0x4004 2194

Instance

RFC_PHA

Description

LFSR 0 6-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

5:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x00



TOP:RFC_PHA:PHALFSR0INM7

Address offset

0x0000 0198

Physical address

0x4004 2198

Instance

RFC_PHA

Description

LFSR 0 7-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

6:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x00



TOP:RFC_PHA:PHALFSR0INM8

Address offset

0x0000 019C

Physical address

0x4004 219C

Instance

RFC_PHA

Description

LFSR 0 8-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x00



TOP:RFC_PHA:PHALFSR0INM9

Address offset

0x0000 01A0

Physical address

0x4004 21A0

Instance

RFC_PHA

Description

LFSR 0 9-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x000



TOP:RFC_PHA:PHALFSR0INM10

Address offset

0x0000 01A4

Physical address

0x4004 21A4

Instance

RFC_PHA

Description

LFSR 0 10-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

9:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x000



TOP:RFC_PHA:PHALFSR0INM11

Address offset

0x0000 01A8

Physical address

0x4004 21A8

Instance

RFC_PHA

Description

LFSR 0 11-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:11

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

10:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x000



TOP:RFC_PHA:PHALFSR0INM12

Address offset

0x0000 01AC

Physical address

0x4004 21AC

Instance

RFC_PHA

Description

LFSR 0 12-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

11:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x000



TOP:RFC_PHA:PHALFSR0INM13

Address offset

0x0000 01B0

Physical address

0x4004 21B0

Instance

RFC_PHA

Description

LFSR 0 13-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

12:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR0INM14

Address offset

0x0000 01B4

Physical address

0x4004 21B4

Instance

RFC_PHA

Description

LFSR 0 14-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

13:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR0INM15

Address offset

0x0000 01B8

Physical address

0x4004 21B8

Instance

RFC_PHA

Description

LFSR 0 15-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:15

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

14:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR0INM16

Address offset

0x0000 01BC

Physical address

0x4004 21BC

Instance

RFC_PHA

Description

LFSR 0 16-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR0INM17

Address offset

0x0000 01C0

Physical address

0x4004 21C0

Instance

RFC_PHA

Description

LFSR 0 17-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

16:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR0INM18

Address offset

0x0000 01C4

Physical address

0x4004 21C4

Instance

RFC_PHA

Description

LFSR 0 18-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

17:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR0INM19

Address offset

0x0000 01C8

Physical address

0x4004 21C8

Instance

RFC_PHA

Description

LFSR 0 19-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:19

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

18:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR0INM20

Address offset

0x0000 01CC

Physical address

0x4004 21CC

Instance

RFC_PHA

Description

LFSR 0 20-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

19:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR0INM21

Address offset

0x0000 01D0

Physical address

0x4004 21D0

Instance

RFC_PHA

Description

LFSR 0 21-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:21

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

20:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR0INM22

Address offset

0x0000 01D4

Physical address

0x4004 21D4

Instance

RFC_PHA

Description

LFSR 0 22-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:22

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

21:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR0INM23

Address offset

0x0000 01D8

Physical address

0x4004 21D8

Instance

RFC_PHA

Description

LFSR 0 23-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:23

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

22:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR0INM24

Address offset

0x0000 01DC

Physical address

0x4004 21DC

Instance

RFC_PHA

Description

LFSR 0 24-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR0INM25

Address offset

0x0000 01E0

Physical address

0x4004 21E0

Instance

RFC_PHA

Description

LFSR 0 25-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:25

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

24:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR0INM26

Address offset

0x0000 01E4

Physical address

0x4004 21E4

Instance

RFC_PHA

Description

LFSR 0 26-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:26

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

25:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR0INM27

Address offset

0x0000 01E8

Physical address

0x4004 21E8

Instance

RFC_PHA

Description

LFSR 0 27-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:27

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

26:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR0INM28

Address offset

0x0000 01EC

Physical address

0x4004 21EC

Instance

RFC_PHA

Description

LFSR 0 28-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

27:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR0INM29

Address offset

0x0000 01F0

Physical address

0x4004 21F0

Instance

RFC_PHA

Description

LFSR 0 29-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

28:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR0INM30

Address offset

0x0000 01F4

Physical address

0x4004 21F4

Instance

RFC_PHA

Description

LFSR 0 30-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

29:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR0INM31

Address offset

0x0000 01F8

Physical address

0x4004 21F8

Instance

RFC_PHA

Description

LFSR 0 31-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

30:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR0INM32

Address offset

0x0000 01FC

Physical address

0x4004 21FC

Instance

RFC_PHA

Description

LFSR 0 32-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR0INR

LFSR 0 input value MSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR1INL1

Address offset

0x0000 0200

Physical address

0x4004 2200

Instance

RFC_PHA

Description

LFSR 1 1-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

LFSR1IN

LFSR 1 input value LSB first

RW

0



TOP:RFC_PHA:PHALFSR1INL2

Address offset

0x0000 0204

Physical address

0x4004 2204

Instance

RFC_PHA

Description

LFSR 1 2-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0



TOP:RFC_PHA:PHALFSR1INL3

Address offset

0x0000 0208

Physical address

0x4004 2208

Instance

RFC_PHA

Description

LFSR 1 3-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0



TOP:RFC_PHA:PHALFSR1INL4

Address offset

0x0000 020C

Physical address

0x4004 220C

Instance

RFC_PHA

Description

LFSR 1 4-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0



TOP:RFC_PHA:PHALFSR1INL5

Address offset

0x0000 0210

Physical address

0x4004 2210

Instance

RFC_PHA

Description

LFSR 1 5-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x00



TOP:RFC_PHA:PHALFSR1INL6

Address offset

0x0000 0214

Physical address

0x4004 2214

Instance

RFC_PHA

Description

LFSR 1 6-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

5:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x00



TOP:RFC_PHA:PHALFSR1INL7

Address offset

0x0000 0218

Physical address

0x4004 2218

Instance

RFC_PHA

Description

LFSR 1 7-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

6:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x00



TOP:RFC_PHA:PHALFSR1INL8

Address offset

0x0000 021C

Physical address

0x4004 221C

Instance

RFC_PHA

Description

LFSR 1 8-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x00



TOP:RFC_PHA:PHALFSR1INL9

Address offset

0x0000 0220

Physical address

0x4004 2220

Instance

RFC_PHA

Description

LFSR 1 9-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x000



TOP:RFC_PHA:PHALFSR1INL10

Address offset

0x0000 0224

Physical address

0x4004 2224

Instance

RFC_PHA

Description

LFSR 1 10-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

9:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x000



TOP:RFC_PHA:PHALFSR1INL11

Address offset

0x0000 0228

Physical address

0x4004 2228

Instance

RFC_PHA

Description

LFSR 1 11-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:11

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

10:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x000



TOP:RFC_PHA:PHALFSR1INL12

Address offset

0x0000 022C

Physical address

0x4004 222C

Instance

RFC_PHA

Description

LFSR 1 12-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

11:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x000



TOP:RFC_PHA:PHALFSR1INL13

Address offset

0x0000 0230

Physical address

0x4004 2230

Instance

RFC_PHA

Description

LFSR 1 13-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

12:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR1INL14

Address offset

0x0000 0234

Physical address

0x4004 2234

Instance

RFC_PHA

Description

LFSR 1 14-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

13:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR1INL15

Address offset

0x0000 0238

Physical address

0x4004 2238

Instance

RFC_PHA

Description

LFSR 1 15-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:15

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

14:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR1INL16

Address offset

0x0000 023C

Physical address

0x4004 223C

Instance

RFC_PHA

Description

LFSR 1 16-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR1INL17

Address offset

0x0000 0240

Physical address

0x4004 2240

Instance

RFC_PHA

Description

LFSR 1 17-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

16:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR1INL18

Address offset

0x0000 0244

Physical address

0x4004 2244

Instance

RFC_PHA

Description

LFSR 1 18-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

17:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR1INL19

Address offset

0x0000 0248

Physical address

0x4004 2248

Instance

RFC_PHA

Description

LFSR 1 19-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:19

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

18:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR1INL20

Address offset

0x0000 024C

Physical address

0x4004 224C

Instance

RFC_PHA

Description

LFSR 1 20-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

19:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR1INL21

Address offset

0x0000 0250

Physical address

0x4004 2250

Instance

RFC_PHA

Description

LFSR 1 21-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:21

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

20:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR1INL22

Address offset

0x0000 0254

Physical address

0x4004 2254

Instance

RFC_PHA

Description

LFSR 1 22-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:22

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

21:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR1INL23

Address offset

0x0000 0258

Physical address

0x4004 2258

Instance

RFC_PHA

Description

LFSR 1 23-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:23

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

22:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR1INL24

Address offset

0x0000 025C

Physical address

0x4004 225C

Instance

RFC_PHA

Description

LFSR 1 24-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR1INL25

Address offset

0x0000 0260

Physical address

0x4004 2260

Instance

RFC_PHA

Description

LFSR 1 25-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:25

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

24:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR1INL26

Address offset

0x0000 0264

Physical address

0x4004 2264

Instance

RFC_PHA

Description

LFSR 1 26-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:26

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

25:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR1INL27

Address offset

0x0000 0268

Physical address

0x4004 2268

Instance

RFC_PHA

Description

LFSR 1 27-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:27

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

26:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR1INL28

Address offset

0x0000 026C

Physical address

0x4004 226C

Instance

RFC_PHA

Description

LFSR 1 28-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

27:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR1INL29

Address offset

0x0000 0270

Physical address

0x4004 2270

Instance

RFC_PHA

Description

LFSR 1 29-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

28:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR1INL30

Address offset

0x0000 0274

Physical address

0x4004 2274

Instance

RFC_PHA

Description

LFSR 1 30-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

29:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR1INL31

Address offset

0x0000 0278

Physical address

0x4004 2278

Instance

RFC_PHA

Description

LFSR 1 31-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

30:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR1INL32

Address offset

0x0000 027C

Physical address

0x4004 227C

Instance

RFC_PHA

Description

LFSR 1 32-bit Input, LSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR1IN

LFSR 1 input value LSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR1INM1

Address offset

0x0000 0280

Physical address

0x4004 2280

Instance

RFC_PHA

Description

LFSR 1 1-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:1

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

0

LFSR1INR

LFSR 1 input value MSB first

RW

0



TOP:RFC_PHA:PHALFSR1INM2

Address offset

0x0000 0284

Physical address

0x4004 2284

Instance

RFC_PHA

Description

LFSR 1 2-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:2

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

1:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0



TOP:RFC_PHA:PHALFSR1INM3

Address offset

0x0000 0288

Physical address

0x4004 2288

Instance

RFC_PHA

Description

LFSR 1 3-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:3

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000 0000

2:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0



TOP:RFC_PHA:PHALFSR1INM4

Address offset

0x0000 028C

Physical address

0x4004 228C

Instance

RFC_PHA

Description

LFSR 1 4-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:4

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

3:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0



TOP:RFC_PHA:PHALFSR1INM5

Address offset

0x0000 0290

Physical address

0x4004 2290

Instance

RFC_PHA

Description

LFSR 1 5-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:5

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

4:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x00



TOP:RFC_PHA:PHALFSR1INM6

Address offset

0x0000 0294

Physical address

0x4004 2294

Instance

RFC_PHA

Description

LFSR 1 6-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:6

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

5:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x00



TOP:RFC_PHA:PHALFSR1INM7

Address offset

0x0000 0298

Physical address

0x4004 2298

Instance

RFC_PHA

Description

LFSR 1 7-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:7

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000 0000

6:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x00



TOP:RFC_PHA:PHALFSR1INM8

Address offset

0x0000 029C

Physical address

0x4004 229C

Instance

RFC_PHA

Description

LFSR 1 8-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:8

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

7:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x00



TOP:RFC_PHA:PHALFSR1INM9

Address offset

0x0000 02A0

Physical address

0x4004 22A0

Instance

RFC_PHA

Description

LFSR 1 9-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:9

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

8:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x000



TOP:RFC_PHA:PHALFSR1INM10

Address offset

0x0000 02A4

Physical address

0x4004 22A4

Instance

RFC_PHA

Description

LFSR 1 10-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:10

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

9:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x000



TOP:RFC_PHA:PHALFSR1INM11

Address offset

0x0000 02A8

Physical address

0x4004 22A8

Instance

RFC_PHA

Description

LFSR 1 11-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:11

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00 0000

10:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x000



TOP:RFC_PHA:PHALFSR1INM12

Address offset

0x0000 02AC

Physical address

0x4004 22AC

Instance

RFC_PHA

Description

LFSR 1 12-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:12

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

11:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x000



TOP:RFC_PHA:PHALFSR1INM13

Address offset

0x0000 02B0

Physical address

0x4004 22B0

Instance

RFC_PHA

Description

LFSR 1 13-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:13

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

12:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR1INM14

Address offset

0x0000 02B4

Physical address

0x4004 22B4

Instance

RFC_PHA

Description

LFSR 1 14-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:14

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

13:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR1INM15

Address offset

0x0000 02B8

Physical address

0x4004 22B8

Instance

RFC_PHA

Description

LFSR 1 15-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:15

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0 0000

14:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR1INM16

Address offset

0x0000 02BC

Physical address

0x4004 22BC

Instance

RFC_PHA

Description

LFSR 1 16-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:16

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

15:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0000



TOP:RFC_PHA:PHALFSR1INM17

Address offset

0x0000 02C0

Physical address

0x4004 22C0

Instance

RFC_PHA

Description

LFSR 1 17-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:17

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

16:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR1INM18

Address offset

0x0000 02C4

Physical address

0x4004 22C4

Instance

RFC_PHA

Description

LFSR 1 18-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:18

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

17:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR1INM19

Address offset

0x0000 02C8

Physical address

0x4004 22C8

Instance

RFC_PHA

Description

LFSR 1 19-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:19

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0000

18:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR1INM20

Address offset

0x0000 02CC

Physical address

0x4004 22CC

Instance

RFC_PHA

Description

LFSR 1 20-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:20

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

19:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0 0000



TOP:RFC_PHA:PHALFSR1INM21

Address offset

0x0000 02D0

Physical address

0x4004 22D0

Instance

RFC_PHA

Description

LFSR 1 21-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:21

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

20:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR1INM22

Address offset

0x0000 02D4

Physical address

0x4004 22D4

Instance

RFC_PHA

Description

LFSR 1 22-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:22

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

21:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR1INM23

Address offset

0x0000 02D8

Physical address

0x4004 22D8

Instance

RFC_PHA

Description

LFSR 1 23-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:23

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x000

22:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR1INM24

Address offset

0x0000 02DC

Physical address

0x4004 22DC

Instance

RFC_PHA

Description

LFSR 1 24-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:24

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

23:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x00 0000



TOP:RFC_PHA:PHALFSR1INM25

Address offset

0x0000 02E0

Physical address

0x4004 22E0

Instance

RFC_PHA

Description

LFSR 1 25-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:25

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

24:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR1INM26

Address offset

0x0000 02E4

Physical address

0x4004 22E4

Instance

RFC_PHA

Description

LFSR 1 26-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:26

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

25:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR1INM27

Address offset

0x0000 02E8

Physical address

0x4004 22E8

Instance

RFC_PHA

Description

LFSR 1 27-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:27

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x00

26:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR1INM28

Address offset

0x0000 02EC

Physical address

0x4004 22EC

Instance

RFC_PHA

Description

LFSR 1 28-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:28

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

27:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x000 0000



TOP:RFC_PHA:PHALFSR1INM29

Address offset

0x0000 02F0

Physical address

0x4004 22F0

Instance

RFC_PHA

Description

LFSR 1 29-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:29

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

28:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR1INM30

Address offset

0x0000 02F4

Physical address

0x4004 22F4

Instance

RFC_PHA

Description

LFSR 1 30-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:30

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0x0

29:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR1INM31

Address offset

0x0000 02F8

Physical address

0x4004 22F8

Instance

RFC_PHA

Description

LFSR 1 31-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31

Reserved

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.(RO std text)

RO

0

30:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0000 0000



TOP:RFC_PHA:PHALFSR1INM32

Address offset

0x0000 02FC

Physical address

0x4004 22FC

Instance

RFC_PHA

Description

LFSR 1 32-bit Input, MSB First

Type

RW

Bits

Field Name

Description

Type

Reset

31:0

LFSR1INR

LFSR 1 input value MSB first

RW

0x0000 0000