The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC342x Quad-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converter datasheet (Rev. A) | PDF | HTML | 30 Sep 2015 |
| EVM User's guide | ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) | 24 Aug 2018 |
For additional terms or required resources, click any title below to view the detail page where available.
The ADC3423 EVM demonstrates the performance of a low power quad 80Msps 12 bit ADC. It includes the ADC3423 device and TI voltage regulators to provide the necessary voltages. The input for the ADC is by default connected to the transformer input which can be connected to a 50 ohm (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RTQ) | 56 | Ultra Librarian |
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.