LMK04808
Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO
LMK04808
- Ultra-Low RMS Jitter Performance
- 111 fs RMS Jitter (12 kHz to 20 MHz)
- 123 fs RMS Jitter (100 Hz to 20 MHz)
- Dual Loop PLLatinum™ PLL Architecture
- PLL1
- Integrated Low-Noise Crystal Oscillator
Circuit - Holdover Mode when Input Clocks are Lost
- Automatic or Manual Triggering/Recovery
- Integrated Low-Noise Crystal Oscillator
- PLL2
- Normalized PLL Noise Floor of –227 dBc/Hz
- Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Integrated Low-Noise VCO
- 2 Redundant Input Clocks with LOS
- Automatic and Manual Switch-Over Modes
- 50 % Duty Cycle Output Divides, 1 to 1045 (Even
and Odd) - 12 LVPECL, LVDS, or LVCMOS Programmable
Outputs - Digital Delay: Fixed or Dynamically Adjustable
- 25 ps Step Analog Delay Control.
- 14 Differential Outputs. Up to 26 Single Ended.
- Up to 6 VCXO/Crystal Buffered Outputs
- Clock Rates of up to 1536 MHz
- 0-Delay Mode
- Three Default Clock Outputs at Power Up
- Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution - Industrial Temperature Range: –40 to 85°C
- 3.15-V to 3.45-V Operation
- 2 Dedicated Buffered/Divided OSCin Clocks
- Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
The LMK0480x family is the industrys highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
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Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet (Rev. K) | PDF | HTML | 24 Dec 2014 |
User guide | TSW308x Evaluation Module (Rev. B) | 18 May 2016 | ||
EVM User's guide | TSW4806EVM User's Guide (Rev. A) | 26 Apr 2016 | ||
EVM User's guide | LMK0480x Evaluation Board Instructions (Rev. B) | 04 Aug 2014 | ||
Design guide | TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide | 03 Sep 2013 | ||
Application note | Using the LMK0480x/LMK04906 for Hitless Switching and Holdover | 12 Jul 2013 | ||
Application note | Effects of Clock Noise on High Speed DAC Performance | 08 Nov 2012 | ||
User guide | TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) | 29 Dec 2011 | ||
Design guide | Clock Conditioner Owner's Manual | 10 Nov 2006 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
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TSW30H84EVM — Wideband Transmit Signal Chain Evaluation Board and Reference Design
The TSW30H84EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (Please see LMK04800) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution (...)
SLAC532 — TSW4806 Installer GUI
Supported products & hardware
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Clock jitter cleaners
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The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
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Supported products & hardware
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Clock generators
Clock buffers
Clock jitter cleaners
RF PLLs & synthesizers
Hardware development
Evaluation board
CLOCKDESIGNTOOL — Clock Design Tool Software
The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
Supported products & hardware
Products
Clock generators
Clock buffers
Clock jitter cleaners
RF PLLs & synthesizers
CLOCK-TREE-ARCHITECT — Clock tree architect programming software
PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
Supported products & hardware
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
RF PLLs & synthesizers
IQ demodulators
Hardware development
Evaluation board
Software
Application software & framework
IDE, configuration, compiler or debugger
Support software
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
WQFN (NKD) | 64 | Ultra Librarian |
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