SN75LVDS83B

ACTIVE

10- to 135-MHz 28-bit LVDS transmitter/serializer & FlatLink™ integrated circuit

Product details

Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • LVDS Display Series Interfaces Directly to LCD
    Display Panels With Integrated LVDS
  • Package Options: 4.5-mm × 7-mm BGA,
    and 8.1-mm × 14-mm TSSOP
  • 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
    Directly to Low-Power, Low-Voltage Application and
    Graphic Processors
  • Transfer Rate up to 135 Mpps (Mega Pixel Per Second);
    Pixel Clock Frequency Range 10 MHz to 135 MHz
  • Suited for Display Resolutions Ranging From HVGA
    up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170 mW (Typ.)
    at 75 MHz
  • 28 Data Channels Plus Clock in Low-Voltage TTL to 4
    Data Channels Plus Clock Out Low-Voltage Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered
    Inputs
  • ESD: 5-kV HBM
  • Support Spread Spectrum Clocking (SSC)
  • Compatible with all OMAP™ 2x, OMAP™ 3x, and
    DaVinci™ Application Processors
  • LVDS Display Series Interfaces Directly to LCD
    Display Panels With Integrated LVDS
  • Package Options: 4.5-mm × 7-mm BGA,
    and 8.1-mm × 14-mm TSSOP
  • 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
    Directly to Low-Power, Low-Voltage Application and
    Graphic Processors
  • Transfer Rate up to 135 Mpps (Mega Pixel Per Second);
    Pixel Clock Frequency Range 10 MHz to 135 MHz
  • Suited for Display Resolutions Ranging From HVGA
    up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170 mW (Typ.)
    at 75 MHz
  • 28 Data Channels Plus Clock in Low-Voltage TTL to 4
    Data Channels Plus Clock Out Low-Voltage Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered
    Inputs
  • ESD: 5-kV HBM
  • Support Spread Spectrum Clocking (SSC)
  • Compatible with all OMAP™ 2x, OMAP™ 3x, and
    DaVinci™ Application Processors

The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of –10°C to 70°C.

Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.

The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of –10°C to 70°C.

Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.

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Technical documentation

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Type Title Date
* Data sheet SN75LVDS83B FlatLink™ Transmitter datasheet (Rev. C) PDF | HTML 29 Jul 2014
Application note AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) 03 Aug 2018
Application note How to Bridge HDMI/DVI to LVDS/OLDI (Rev. C) 07 Jun 2018
Technical article Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Ind PDF | HTML 24 Aug 2017
Application note FlatLink™ Data Transmission System Using SN75LVDS83B/SN75LVDS82/SN75LVDS86A 02 Feb 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LVDS83BTSSOPEVM — LVDS83BT 10-135 MHz 28-bit LVDS Transmitter/Serializer Evaluation Module

The SN75LVDS83B transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted (...)
User guide: PDF
Not available on TI.com
Simulation model

SN75LVDS83B IBIS Model

SLLM077.ZIP (31 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Reference designs

TIDA-010013 — RGB to OLDI/LVDS Display Bridge Reference Design for Sitara™ Processors

Higher resolution displays are now in larger demand than ever before. This results in a higher pixel clock which can lead to challenges such as high EMI emission and noise immunity. As a result, the video interface now transitions from a traditional RGB to LVDS video interface. As microprocessors (...)
Design guide: PDF
Schematic: PDF
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TSSOP (DGG) 56 Ultra Librarian

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