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High-speed ADCs (≥10 MSPS)

ADC12D1800RF

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12-Bit, Dual 1.8GSPS or Single 3.6GSPS, RF-Sampling Analog-to-Digital Converter (ADC)

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Data sheet

ADC12D1800RF

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 1800, 3600 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 4400 Architecture Folding Interpolating SNR (dB) 58.6 ENOB (Bits) 9.3 SFDR (dB) 71.7 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1800, 3600 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 4400 Architecture Folding Interpolating SNR (dB) 58.6 ENOB (Bits) 9.3 SFDR (dB) 71.7 Operating temperature range (°C) -40 to 85 Input buffer Yes
PBGA (NXA) 292 729 mm² 27 x 27
  • Excellent Noise and Linearity Up to and Above fIN = 2.7 GHz
  • Configurable to Either 3.6 GSPS Interleaved or 1800 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00, ADC12Dx00RF
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution: 12 Bits
    • Interleaved 3.6 GSPS ADC (all typical)
      • IMD3 (Fin = 2.7GHz at -13dBFS) –62 dBc
      • IMD3 (Fin = 2.7GHz at -16dBFS) –64 dBc
      • Noise Floor Density -155.0 dBm/Hz
      • Power 4.29 W
    • Dual 1800 MSPS ADC, Fin = 498 MHz
      • ENOB 9.3 Bits (typ)
      • SNR 58.1 dB (typ)
      • SFDR 71.7 dBc (typ)
      • Power per Channel 2.15 W (typ)
  • Excellent Noise and Linearity Up to and Above fIN = 2.7 GHz
  • Configurable to Either 3.6 GSPS Interleaved or 1800 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00, ADC12Dx00RF
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution: 12 Bits
    • Interleaved 3.6 GSPS ADC (all typical)
      • IMD3 (Fin = 2.7GHz at -13dBFS) –62 dBc
      • IMD3 (Fin = 2.7GHz at -16dBFS) –64 dBc
      • Noise Floor Density -155.0 dBm/Hz
      • Power 4.29 W
    • Dual 1800 MSPS ADC, Fin = 498 MHz
      • ENOB 9.3 Bits (typ)
      • SNR 58.1 dB (typ)
      • SFDR 71.7 dBc (typ)
      • Power per Channel 2.15 W (typ)

The 12-bit 1.8 GSPS ADC12D1800RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D1800RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone.

The ADC12D1800RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to +85°C.

The 12-bit 1.8 GSPS ADC12D1800RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D1800RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone.

The ADC12D1800RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to +85°C.
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Technical documentation

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Type Title Date
* Data sheet ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC datasheet (Rev. J) PDF | HTML 11 Nov 2014
Application note AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 03 Feb 2017
Application note Wide Bandwidth Receiver Implementation by Interleaving Two Giga-Sampling ADCs 07 Dec 2015
Application note Signal Chain Noise Figure Analysis 29 Oct 2014
Application note Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs 06 Aug 2014
Application note Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat 09 Dec 2013
Application note AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 01 May 2013
User guide Schematic and Layout Recommendations for the GSPS ADC 29 Apr 2013
Application note AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 26 Apr 2013
Application note From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 18 Dec 2012
Product overview ADC12Dxx00RF Direct RF-Sampling ADC Family 16 May 2012
User guide 12-Bit, Dual 1.6/1.8 GSPS or Single 3.2/3.6 GSPS A/D Converter Ref Bd User Guide 25 Jan 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC-LD-BB — ADC low-distortion balun board

One ADC-LD-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

User guide: PDF
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Support software

WAVEVISION5 — WaveVision 5 Software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

Supported products & hardware

Supported products & hardware

Products
High-speed ADCs (≥10 MSPS)
ADC08D1020 — 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS, Analog-to-Digital Converter (ADC) ADC08D1520 — 8-Bit, Dual 1.5-GSPS or Single 3.0-GSPS Analog-to-Digital Converter (ADC) ADC10D1000 — 10-Bit, Dual 1.0-GSPS or Single 2.0-GSPS Analog-to-Digital Converter (ADC) ADC10D1500 — 10-Bit, Dual 1.5-GSPS or Single 3.0-GSPS Analog-to-Digital Converter (ADC) ADC10DV200 — Dual-Channel, 10-Bit, 200-MSPS Analog-to-Digital Converter (ADC) ADC12D1000 — 12-Bit, Dual 1.0-GSPS or Single 2.0-GSPS Analog-to-Digital Converter (ADC) ADC12D1000RF — 12-Bit, Dual 1.0-GSPS or Single 2.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC) ADC12D1600 — 12-bit, dual 1.6-GSPS or single 3.2-GSPS analog-to-digital converter (ADC) ADC12D1600RF — 12-bit, dual 1.6-GSPS or single 3.2-GSPS, RF-sampling analog-to-digital converter (ADC) ADC12D1800 — 12-bit, dual 1.8GSPS or single 3.6GSPS analog-to-digital converter (ADC) ADC12D1800RF — 12-Bit, Dual 1.8GSPS or Single 3.6GSPS, RF-Sampling Analog-to-Digital Converter (ADC) ADC12D500RF — 12-Bit, Dual 500-MSPS or Single 1.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC) ADC12D800RF — 12-Bit, Dual 800-MSPS or Single 1.6-GSPS, RF Sampling Analog-to-Digital Converter (ADC) ADC14DC080 — Dual-Channel, 14-Bit, 80-MSPS, 1.0-GHz Input Bandwidth Analog-to-Digital Converter (ADC) ADC16DV160 — Dual-Channel, 16-Bit, 160-MSPS Analog-to-Digital Converter (ADC) ADC16V130 — 16-Bit, 130-MSPS Analog-to-Digital Converter (ADC)
Hardware development
Evaluation board
ADC12D1600RB — 12-bit, dual 1.6-/1.8-GSPS or single 3.2-/3.6-GSPS ADC reference board ADC16DV160HFEB — ADC16DV160HFEB Evaluation Board LM98640CVAL — Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output WAVEVSN-BRD-5.1 — WaveVision 5 Data Capture Board Version 5.1
Software
Application software & framework
WAVEVISION5 — Data acquisition and analysis software
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Simulation model

ADC12D1000 IBIS Model

SNAM014.ZIP (41 KB) - IBIS Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-00113 — Driving GSPS ADCs in Single-Channel or Dual-Channel Mode for High Bandwidth Applications

This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications.  The tradeoffs considered include balun construction, insertion loss, dynamic (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00479 — Optimal Clock Sources for GSPS ADCs Reference Design

The ADC12D1600RFRB reference design provides a platform to demonstrate a high speed digitizer application which incorporates clocking, power management, and signal processing. The reference design utilizes the 1.6 GSPS ADC12D1600RF device, onboard FPGA Xilinx Virtex 4, and high performance clock (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00071 — Schematic and Layout Recommendations for the Giga Sample Per Second (GSPS) ADC

This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference (...)
User guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
PBGA (NXA) 292 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

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