SLUSCF0B November   2015  – September 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power Up
        1. 8.3.1.1 Power-On-Reset (POR)
        2. 8.3.1.2 Power Up from Battery without DC Source
          1. 8.3.1.2.1 BATFET Turn Off
          2. 8.3.1.2.2 Shipping Mode
        3. 8.3.1.3 Power Up from DC Source
          1. 8.3.1.3.1 REGN LDO
          2. 8.3.1.3.2 Input Source Qualification
          3. 8.3.1.3.3 Input Current Limit Detection
          4. 8.3.1.3.4 PSEL/OTG Pins Set Input Current Limit
          5. 8.3.1.3.5 HIZ State with 100 mA USB Host
          6. 8.3.1.3.6 Force Input Current Limit Detection
        4. 8.3.1.4 Converter Power-Up
        5. 8.3.1.5 Boost Mode Operation from Battery
      2. 8.3.2 Power Path Management
        1. 8.3.2.1 Narrow VDC Architecture
        2. 8.3.2.2 Dynamic Power Management
        3. 8.3.2.3 Supplement Mode
      3. 8.3.3 Battery Charging Management
        1. 8.3.3.1 Autonomous Charging Cycle
        2. 8.3.3.2 Battery Charging Profile
        3. 8.3.3.3 Thermistor Qualification
          1. 8.3.3.3.1 Cold/Hot Temperature Window
        4. 8.3.3.4 Charging Termination
          1. 8.3.3.4.1 Termination When REG02[0] = 1
        5. 8.3.3.5 Charging Safety Timer
          1. 8.3.3.5.1 Safety Timer Configuration Change
        6. 8.3.3.6 USB Timer When Charging from USB100 mA Source
      4. 8.3.4 Status Outputs (PG, STAT, and INT)
        1. 8.3.4.1 Power Good Indicator (PG)
        2. 8.3.4.2 Charging Status Indicator (STAT)
        3. 8.3.4.3 Interrupt to Host (INT)
      5. 8.3.5 Protections
        1. 8.3.5.1 Input Current Limit on ILIM
        2. 8.3.5.2 Thermal Regulation and Thermal Shutdown
        3. 8.3.5.3 Voltage and Current Monitoring in Buck Mode
          1. 8.3.5.3.1 Input Over Voltage (ACOV)
          2. 8.3.5.3.2 System Over Voltage Protection (SYSOVP)
        4. 8.3.5.4 Voltage and Current Monitoring in Boost Mode
          1. 8.3.5.4.1 Over Current Protection
          2. 8.3.5.4.2 VBUS Over Voltage Protection
        5. 8.3.5.5 Battery Protection
          1. 8.3.5.5.1 Battery Over-Voltage Protection (BATOVP)
          2. 8.3.5.5.2 Battery Short Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
        1. 8.4.1.1 Plug in USB100 mA Source with Good Battery
        2. 8.4.1.2 USB Timer When Charging from USB100 mA Source
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Slave Address and Data Direction Bit
          1. 8.5.1.5.1 Single Read and Write
          2. 8.5.1.5.2 Multi-Read and Multi-Write
    6. 8.6 Register Map
      1. 8.6.1 I2C Registers
        1. 8.6.1.1  Input Source Control Register REG00 [reset = 00110xxx, or 3x]
        2. 8.6.1.2  Power-On Configuration Register REG01 [reset = 00011011, or 0x1B]
        3. 8.6.1.3  Charge Current Control Register REG02 [reset = 01100000, or 60]
        4. 8.6.1.4  Pre-Charge/Termination Current Control Register REG03 [reset = 00010001, or 0x11]
        5. 8.6.1.5  Charge Voltage Control Register REG04 [reset = 10110010, or 0xB2]
        6. 8.6.1.6  Charge Termination/Timer Control Register REG05 [reset = 10011100, or 0x9C]
        7. 8.6.1.7  Boost Voltage/Thermal Regulation Control Register REG06 [reset = 01110011, or 0x73]
        8. 8.6.1.8  Misc Operation Control Register REG07 [reset = 01001011, or 4B]
        9. 8.6.1.9  System Status Register REG08
        10. 8.6.1.10 New Fault Register REG09
        11. 8.6.1.11 Vender / Part / Revision Status Register REG0A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 90% High Efficiency Switch Mode 2-A Charger
  • 3.9-V to 6.2-V Single Input USB-Compliant Charger with 6.4-V Over-Voltage Protection
    • Input voltage and current limit supports USB 2.0 and USB 3.0
    • Input Current Limit: 100 mA, 150 mA, 500 mA, 900 mA, 1 A, 1.5 A, 2 A
  • USB OTG with Adjustable output 4.55 V to 5.5 V at 1 A or 1.5 A
    • Fast OTG Startup (22 ms Typical)
    • 90% 5-V Boost Mode Efficiency
    • Accurate ±15% Hiccup Mode Overcurrent Protection
  • Narrow VDC (NVDC) Power Path Management
    • Instant System On with No Battery or Deeply Discharged Battery
    • Ideal Diode Operation in Battery Supplement Mode
  • 1.5-MHz Switching Frequency for Low Profile 1.2-mm Inductor
  • I2C port for optimal system performance and status reporting
  • Autonomous Battery Charging with or without Host Management
    • Battery Charge Enable
    • Battery Charge Preconditioning
    • Charge Termination and Recharge
  • High Accuracy
    • ±0.5% Charge Voltage Regulation
    • ±7% Charge Current Regulation
    • ±7.5% Input Current Regulation
    • ±3% Output Voltage Regulation in USB OTG Boost Mode
  • High Integration
    • Power Path Management
    • Synchronous Switching MOSFETs
    • Integrated Current Sensing
    • Bootstrap Diode
    • Internal Loop Compensation
  • Safety
    • Battery Temperature Sensing for Charging and Discharging in OTG Mode
    • Battery Charging Safety Timer
    • Thermal Regulation and Thermal Shutdown
    • Input and System Over-Voltage Protection
    • MOSFET Over-Current Protection
  • Charge Status Outputs for LED or Host Processor
  • Maximum power tracking capability by input voltage regulation
  • 20-µA Low Battery Leakage Current and Support Shipping Mode
  • 4-mm x 4-mm VQFN-24 Package

2 Applications

  • Tablet PC, Smart Phone, Internet Devices
  • Portable Audio Speaker

3 Description

The bq24259 is a highly-integrated switch-mode battery charge management and system power path management device for 1 cell Li-Ion and Li-polymer battery in a wide range of smart phone and tablet applications. Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase. The I2C serial interface with charging and system settings makes the device a truly flexible solution.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
bq24259 VQFN (24) 4.00 mm x 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

PSEL from PHY, Charging from SDP/DCP, and Optional BATFET Enable Interface

bq24259 app_diag_SLUSCF0.gif

4 Revision History

Changes from A Revision (January 2016) to B Revision

  • Changed pin 21 of the Pin Functions table From: "anode of the boost-strap diode." To: "cathode of the boost-strap diode." Go
  • Changed pin 22 of the Pin Functions table From: cathode of the boost-strap diode." To: "anode of the boost-strap diode." Go
  • Changed VREF To: VREGN in Figure 17, Figure 18, and Equation 1Go
  • Changed the RESET value of Bit 3 and Bit 2 From: 1 To: 0 in Table 10 Go
  • Changed the RESET value of Bit 2 From: 0 To: 1 and Bit 1 From: 1 To: 0 in Table 11 Go
  • Added Note 1 to Figure 39 Go
  • Changed "between 15 kHz and 25 kHz" To: "between 15 kHz and 36 kHz" in the last paragraph of the Output Capacitor sectionGo

Changes from * Revision (November 2015) to A Revision

  • Changed pin "BOOT" To: "BTST" in the schematic imageGo
  • Changed pin "BOOT" To: "BTST" in Figure 39Go