CDC208

ACTIVE

5-V dual 1-to-4 clock driver

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Data sheet

document-pdfAcrobat Dual 1-Line To 4-Line Clock Drivers With 3-State Outputs datasheet (Rev. F)

CDC208

ACTIVE

Data sheet

Order now

Product details

Function

Single-ended

Output frequency (max) (MHz)

60

Number of outputs

8

Output supply voltage (V)

5

Core supply voltage (V)

5

Output skew (ps)

1000

Features

Dual 1:4 fanout

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

CMOS

Input type

TTL

Function

Single-ended

Output frequency (max) (MHz)

60

Number of outputs

8

Output supply voltage (V)

5

Core supply voltage (V)

5

Output skew (ps)

1000

Features

Dual 1:4 fanout

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

CMOS

Input type

TTL

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SOP (NS)

20

98.28 mm² 12.6 x 7.8

Low-Skew Propagation Delay Specifications for Clock-Driver Applications
TTL-Compatible Inputs and CMOS-Compatible Outputs
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V_CC and GND Pin Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-um Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (DW)

EPIC is a trademark of Texas Instruments Incorporated.

Low-Skew Propagation Delay Specifications for Clock-Driver Applications
TTL-Compatible Inputs and CMOS-Compatible Outputs
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V_CC and GND Pin Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-um Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (DW)

EPIC is a trademark of Texas Instruments Incorporated.

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC208 is characterized for operation from -40°C to 85°C.

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC208 is characterized for operation from -40°C to 85°C.

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