Product details

Function Single-ended Additive RMS jitter (typ) (fs) 56 Output frequency (max) (MHz) 200 Number of outputs 4 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 150 Features 1:4 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
Function Single-ended Additive RMS jitter (typ) (fs) 56 Output frequency (max) (MHz) 200 Number of outputs 4 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 150 Features 1:4 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
TSSOP (PW) 8 19.2 mm² 3 x 6.4
  • General-Purpose and PCI-X 1:4 Clock Buffer
  • Operating Frequency
    • 0 MHz to 200 MHz General-Purpose
  • Low Output Skew: <100 ps
  • Distributes One Clock Input to One Bank of Four Outputs
  • Output Enable Control that Drives Outputs Low when OE is Low
  • Operates from Single 3.3-V Supply or 2.5-V Supply
  • PCI-X Compliant
  • 8-Pin TSSOP Package
  • General-Purpose and PCI-X 1:4 Clock Buffer
  • Operating Frequency
    • 0 MHz to 200 MHz General-Purpose
  • Low Output Skew: <100 ps
  • Distributes One Clock Input to One Bank of Four Outputs
  • Output Enable Control that Drives Outputs Low when OE is Low
  • Operates from Single 3.3-V Supply or 2.5-V Supply
  • PCI-X Compliant
  • 8-Pin TSSOP Package

The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X specifications.

The CDCV304 is characterized for operation from –40°C to 85°C for automotive and industrial applications.

The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X specifications.

The CDCV304 is characterized for operation from –40°C to 85°C for automotive and industrial applications.

Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Pin-for-pin with same functionality to the compared device
LMK1C1104 ACTIVE 4-channel output LVCMOS 1.8-V buffer LMK1C1104 is parametrically superior to the CDCV304, more cost-effective than the CDCV304, and has added features, such as synchronous output enable.

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 3
Type Title Date
* Data sheet CDCV304 200-MHz General-Purpose Clock Buffer, PCI-X Compliant datasheet (Rev. I) PDF | HTML 16 Oct 2017
Application note Clocking Design Guidelines: Unused Pins 19 Nov 2015
Application note Using TI's CDCV304 w/Backplane Transceiver (TLK1201/1501/2201/2501/2701/3101) (Rev. A) 20 Apr 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC08200EVM — ADC08200 8-Bit 200MSPS Low-Power ADC With Internal Sample and Hold Evaluation Module

The ADC08200 evaluation module (EVM) is designed to evaluate the high-speed
CMOS-interface ADC08200. The ADC08200EVM provides simple and minimal external components to minimize system cost and power consumption.

User guide: PDF
Not available on TI.com
Simulation model

CDCV304 IBIS Model Version 1.2 (Rev. D)

SCAC024D.ZIP (38 KB) - IBIS Model
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00076 — Adjacent Channel Power Ratio (ACPR) and Error Vector Magnitude (%EVM) Measurements

This reference design discusses the use of the TSW3085EVM with the TSW3100 pattern generator to test adjacent channel power ratio (ACPR) and error vector magnitude (EVM) measurements of LTE baseband signals. By using the TSW3100 LTE GUI, patterns are loaded into the TSW3085EVM which is comprised of (...)
User guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 8 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos