Home Interface Ethernet ICs Ethernet retimers, redrivers & mux-buffers

DS250DF810

ACTIVE

25-Gbps multi-rate 8-channel retimer

Product details

Type Retimer Mux Number of channels 8 Input compatibility AC-coupling, CML Speed (max) (Gbpp) 25.8 Protocols 100GbE, CDFP, CFP2/CFP4, IEEE802.3bj, Infiniband EDR, OIF-CEi-25G-LR/MR/SR/VSR, QSFP28 Operating temperature range (°C) -10 to 85
Type Retimer Mux Number of channels 8 Input compatibility AC-coupling, CML Speed (max) (Gbpp) 25.8 Protocols 100GbE, CDFP, CFP2/CFP4, IEEE802.3bj, Infiniband EDR, OIF-CEi-25G-LR/MR/SR/VSR, QSFP28 Operating temperature range (°C) -10 to 85
FCCSP (ABV) 135 104 mm² 13 x 8
  • Octal-channel multi-rate retimer with integrated signal conditioning
  • All channels lock independently from 20.2752 to 25.8 Gbps (including sub-rates like 10.3125 Gbps, 12.5 Gbps, and more)
  • Ultra-low latency: <500 ps typical for 25.78125 Gbps data rate
  • Single power supply, no low-jitter reference clock required, and integrated ac coupling capacitors to reduce board routing complexity and BOM cost
  • Integrated 2×2 cross point
  • Adaptive continuous time linear equalizer (CTLE)
  • Adaptive decision feedback equalizer (DFE)
  • Low-jitter transmitter with 3-Tap FIR filter
  • Combined equalization supporting 35+ dB channel loss at 12.9 GHz
  • Adjustable transmit amplitude: 205 mVppd to 1225 mVppd (typical)
  • On-chip eye opening monitor (EOM), PRBS pattern checker/generator small 8 mm × 13 mm BGA package with easy flow-through routing
  • Unique pinout allows routing high-speed signals underneath the package
  • Pin-compatible repeater available
  • Octal-channel multi-rate retimer with integrated signal conditioning
  • All channels lock independently from 20.2752 to 25.8 Gbps (including sub-rates like 10.3125 Gbps, 12.5 Gbps, and more)
  • Ultra-low latency: <500 ps typical for 25.78125 Gbps data rate
  • Single power supply, no low-jitter reference clock required, and integrated ac coupling capacitors to reduce board routing complexity and BOM cost
  • Integrated 2×2 cross point
  • Adaptive continuous time linear equalizer (CTLE)
  • Adaptive decision feedback equalizer (DFE)
  • Low-jitter transmitter with 3-Tap FIR filter
  • Combined equalization supporting 35+ dB channel loss at 12.9 GHz
  • Adjustable transmit amplitude: 205 mVppd to 1225 mVppd (typical)
  • On-chip eye opening monitor (EOM), PRBS pattern checker/generator small 8 mm × 13 mm BGA package with easy flow-through routing
  • Unique pinout allows routing high-speed signals underneath the package
  • Pin-compatible repeater available

The DS250DF810 is an eight-channel multi-rate Retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired high-speed serial links while achieving a bit error rate (BER) of 10-15 or less.

Each channel of the DS250DF810 independently locks to serial data rates in a continuous range from 20.6 Gbps to 25.8 Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.3125 Gbps and 12.5 Gbps, which allows the DS250DF810 to support individual lane Forward Error Correction (FEC) pass-through.

Integrated physical AC coupling capacitors (TX and RX) eliminate the need for external capacitors on the PCB. The DS250DF810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and BOM cost.

The advanced equalization features of the DS250DF810 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is ideal for front-port optical module applications to reset the jitter budget and retime the high-speed serial data. The DS250DF810 implements 2x2 cross-point on each channel pair, providing the host with both lane crossing and fanout options.

The DS250DF810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. A non-disruptive on-chip eye monitor and a PRBS generator/checker allow for in-system diagnostics.

The DS250DF810 is an eight-channel multi-rate Retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired high-speed serial links while achieving a bit error rate (BER) of 10-15 or less.

Each channel of the DS250DF810 independently locks to serial data rates in a continuous range from 20.6 Gbps to 25.8 Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.3125 Gbps and 12.5 Gbps, which allows the DS250DF810 to support individual lane Forward Error Correction (FEC) pass-through.

Integrated physical AC coupling capacitors (TX and RX) eliminate the need for external capacitors on the PCB. The DS250DF810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and BOM cost.

The advanced equalization features of the DS250DF810 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is ideal for front-port optical module applications to reset the jitter budget and retime the high-speed serial data. The DS250DF810 implements 2x2 cross-point on each channel pair, providing the host with both lane crossing and fanout options.

The DS250DF810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. A non-disruptive on-chip eye monitor and a PRBS generator/checker allow for in-system diagnostics.

Download View video with transcript Video
Request more information

The IBIS AMI models, device programming guide and device GUI profile, are available. Request now

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 10
Type Title Date
* Data sheet DS250DF810 25 Gbps Multi-Rate 8-Channel Retimer datasheet (Rev. C) PDF | HTML 24 Oct 2019
Application note Implementing Pin Compatible Ethernet Redrivers and Retimers PDF | HTML 28 Oct 2024
Application note Optimal Implementation of 25G-28G Ethernet Retimers versus Redrivers (Rev. B) PDF | HTML 01 May 2023
Application note DS2X0DF810 Junction Temperature Readback and Temperature Lock Range (TLR) Extens PDF | HTML 24 May 2021
EVM User's guide DS250DF810EVM User's Guide (Rev. C) 03 Sep 2019
Application note Transmitter Optimization for ≥ 25Gbps Retimer Links 08 Sep 2017
More literature Advanced Signal Conditioning Made Easy and Efficient 12 Jan 2017
Analog Design Journal Green box testing: A method for optimizing high-speed serial links 21 Jul 2016
Technical article Designing a 25G system: 5 tips to balance power, performance and price PDF | HTML 01 Feb 2016
Application note Understanding EEPROM Programming for 25G and 28G Repeaters and Retimers 13 Jan 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DS250DF810EVM — 25 Gbps multi-rate 8-channel retimer evaluation module

The DS250DF810EVM allows for easy evaluation of the 25 Gbps retimer DS250DF810. Users are required to supply power and high speed traffic to the EVM via Huber+Suhner 1x8 MXP connectors. Huber+Suhner cables are not included.

Through the onboard USB2ANY connection and EVM software, users can evaluate (...)

User guide: PDF
Not available on TI.com
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Reference designs

TIDA-00427 — 2-port 100GbE/40GbE/10GbE QSFP28 Signal Conditioner Reference Design

This verified reference design is a signal conditioning solution for front-port QSFP28 supporting two 100GbE ports compatible with 100G-CR4/SR4/LR4, 40G-CR4/SR4/LR4 and 10G SFF-8431 requirements. The design is applicable to optical and passive/active copper cables. It allows for reach extension (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
FCCSP (ABV) 135 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos