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DS90CF384AQ-Q1

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+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65MHz - Automotive Grade

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Data sheet

DS90CF384AQ-Q1

ACTIVE
Data sheet Order now

Product details

Function Deserializer Color depth (bpp) 24 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Automotive Operating temperature range (°C) -40 to 85
Function Deserializer Color depth (bpp) 24 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Automotive Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Automotive Grade Device, AEC-Q100 Grade 3 Qualified
  • Operating Temperature Range: –40°C to +85°C
  • 20 to 65 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best–in–Class Set & Hold Times on RxOUTPUTs
  • Rx Power Consumption <142 mW (typ) @65MHz Grayscale
  • Rx Power-down Mode <200μW (max)
  • ESD Rating >7 kV (HBM), >700V (EIAJ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • PLL Requires No External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Lead TSSOP Package

All trademarks are the property of their respective owners.

  • Automotive Grade Device, AEC-Q100 Grade 3 Qualified
  • Operating Temperature Range: –40°C to +85°C
  • 20 to 65 MHz Shift Clock Support
  • 50% Duty Cycle on Receiver Output Clock
  • Best–in–Class Set & Hold Times on RxOUTPUTs
  • Rx Power Consumption <142 mW (typ) @65MHz Grayscale
  • Rx Power-down Mode <200μW (max)
  • ESD Rating >7 kV (HBM), >700V (EIAJ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • PLL Requires No External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 56-Lead TSSOP Package

All trademarks are the property of their respective owners.

The DS90CF384AQ receiver converts the four LVDS data streams at up to 1.8 Gbps throughput (227 Megabytes/sec bandwidth) back into parallel 28 bits of LVCMOS/LVTTL data. In a Display application, the 28 bits include: 24 bits of RGB data and up to 4 bits of video control (Hsync, Vsync, DE and CNTL).

The DS90CF384AQ device is enhanced over prior generation FPD-Link receivers, provides a wider data valid time on the receiver output and is offered as an AEC-Q100 grade 3 device.

FPD-Link is an ideal means to solve EMI and cable size problems associated with wide, high speed LVCMOS/LVTTL interfaces.

The DS90CF384AQ receiver converts the four LVDS data streams at up to 1.8 Gbps throughput (227 Megabytes/sec bandwidth) back into parallel 28 bits of LVCMOS/LVTTL data. In a Display application, the 28 bits include: 24 bits of RGB data and up to 4 bits of video control (Hsync, Vsync, DE and CNTL).

The DS90CF384AQ device is enhanced over prior generation FPD-Link receivers, provides a wider data valid time on the receiver output and is offered as an AEC-Q100 grade 3 device.

FPD-Link is an ideal means to solve EMI and cable size problems associated with wide, high speed LVCMOS/LVTTL interfaces.
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Type Title Date
* Data sheet DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz datasheet (Rev. A) 17 Apr 2013
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29 Jun 2018
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 08 Aug 2017
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15 May 2004
Application note AN-1056 STN Application Using FPD-Link 14 May 2004
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14 May 2004

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