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LMH6521

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High Performance Dual DVGA

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Data sheet

LMH6521

ACTIVE
Data sheet Order now

Product details

2nd harmonic (dBc) 84 3rd harmonic (dBc) 83 Frequency of harmonic distortion measurement (MHz) 200 Acl, min spec gain (V/V) 0.53 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 1400 Gain (max) (dB) 26 Gain (min) (dB) -5.5 Step size (dB) 0.5 Type RF VGA Iq per channel (typ) (mA) 113 Number of channels 2 Rating Catalog Operating temperature range (°C) -40 to 85 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Vs (min) (V) 4.75 Vs (max) (V) 5.25
2nd harmonic (dBc) 84 3rd harmonic (dBc) 83 Frequency of harmonic distortion measurement (MHz) 200 Acl, min spec gain (V/V) 0.53 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 1400 Gain (max) (dB) 26 Gain (min) (dB) -5.5 Step size (dB) 0.5 Type RF VGA Iq per channel (typ) (mA) 113 Number of channels 2 Rating Catalog Operating temperature range (°C) -40 to 85 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Vs (min) (V) 4.75 Vs (max) (V) 5.25
WQFN (RTV) 32 25 mm² 5 x 5
  • OIP3 of 48.5 dBm at 200 MHz
  • Maximum Voltage Gain of 26 dB
  • Gain Range: 31.5 dB with 0.5-dB Step Size
  • Channel Gain Matching of ±0.04 dB
  • Noise Figure: 7.3 dB at Maximum Gain
  • –3-dB Bandwidth of 1200 MHz
  • Low Power Dissipation
  • Independent Channel Power Down
  • Three Gain Control Modes:
    • Parallel Interface
    • Serial Interface (SPI)
    • Pulse Mode Interface
  • Temperature Range: –40°C to +85°C
  • Thermally-Enhanced, 32-Pin WQFN Package
  • OIP3 of 48.5 dBm at 200 MHz
  • Maximum Voltage Gain of 26 dB
  • Gain Range: 31.5 dB with 0.5-dB Step Size
  • Channel Gain Matching of ±0.04 dB
  • Noise Figure: 7.3 dB at Maximum Gain
  • –3-dB Bandwidth of 1200 MHz
  • Low Power Dissipation
  • Independent Channel Power Down
  • Three Gain Control Modes:
    • Parallel Interface
    • Serial Interface (SPI)
    • Pulse Mode Interface
  • Temperature Range: –40°C to +85°C
  • Thermally-Enhanced, 32-Pin WQFN Package

The LMH6521 contains two high performance, digitally controlled variable gain amplifiers (DVGA).

Both channels of the LMH6521 have an independent, digitally controlled attenuator followed by a high linearity, differential output amplifier. Each block has been optimized for low distortion and maximum system design flexibility. Each channel has a high speed power down mode.

The internal digitally controlled attenuator provides precise 0.5-dB gain steps over a 31.5-dB range. Serial and parallel programming options are provided. Serial mode programming uses the SPI interface. A pulse mode is also offered where simple up or down commands can change the gain one step at a time.

The output amplifier has a differential output allowing 10-VPPD signal swings on a single 5-V supply. The low impedance output provides maximum flexibility when driving filters or analog to digital converters.

The LMH6521 contains two high performance, digitally controlled variable gain amplifiers (DVGA).

Both channels of the LMH6521 have an independent, digitally controlled attenuator followed by a high linearity, differential output amplifier. Each block has been optimized for low distortion and maximum system design flexibility. Each channel has a high speed power down mode.

The internal digitally controlled attenuator provides precise 0.5-dB gain steps over a 31.5-dB range. Serial and parallel programming options are provided. Serial mode programming uses the SPI interface. A pulse mode is also offered where simple up or down commands can change the gain one step at a time.

The output amplifier has a differential output allowing 10-VPPD signal swings on a single 5-V supply. The low impedance output provides maximum flexibility when driving filters or analog to digital converters.
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Technical documentation

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Type Title Date
* Data sheet LMH6521 High Performance Dual DVGA datasheet (Rev. E) PDF | HTML 23 Aug 2016
E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 Mar 2017
User guide Using the LMH6521 in DC Coupled Applications Design Guide 08 Jan 2015
Design guide TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide 03 Sep 2013
Design guide TSW1266 Wideband RF-to-Digital Complex Receiver-Feedback Signal Chain 03 Sep 2013
Application note AN-1719 Noise Figure Analysis Fully Differential Amplifier (Rev. A) 01 May 2013
EVM User's guide AN-2045 LMH6521EVAL Evaluation Board (Rev. A) 01 May 2013
Application note AN-2235 Ckt Brd Design for LMH6517/21/22 & Other H-Sp IF/RF F Amp (Rev. A) 01 May 2013
Application note Between the Amplifier and ADC: Managing Filter Loss in Communications Systems (Rev. B) 26 Apr 2013
Application note Drivng HSpeed ADCs w/LMH6521 DVGA for High IF AC-Coupled Apps (Rev. A) 26 Apr 2013
Application note Using High Speed Diff Amp to Drive ADCs (Rev. A) 26 Apr 2013
More literature Featured High Speed Differential Amplifiers 23 Oct 2012
Application note A Walk Along the Signal Path (High-Speed Signal Path) 30 Mar 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TSW1265EVM — Wideband Dual Receiver Reference Design and Evaluation Platform

The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)

User guide: PDF
Not available on TI.com
Simulation model

LMH6521 ADS2009 Spice Model

SNOJ009.ZIP (46 KB) - Spice Model
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Simulation model

LMH6521 PSpice Model

SNOM715.ZIP (68 KB) - PSpice Model
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Simulation model

LMH6521 TINA-TI Reference Design

SNOM321.TSC (286 KB) - TINA-TI Reference Design
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Simulation model

LMH6521 TINA-TI Spice Model

SNOM322.ZIP (8 KB) - TINA-TI Spice Model
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Reference designs

TIDA-00360 — 700–2700 MHz Dual-Channel Receiver with 16-Bit ADC and 100 MHz IF Bandwidth Reference Design

The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00353 — Equalization Optimization of a JESD204B Serial Link Reference Design

Employing equalization techniques is an effective way of compensating for channel loss in JESD204B high speed serial interfaces for data converters. This reference design features the ADC16DX370, a dual 16-bit, 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00074 — Wideband RF-to-Digital Complex Receiver-Feedback Signal Chain

This is a wideband complex-receiver reference design and evaluation platform that is ideally suited for use as a feedback receiver for transmitter digital predistortion. The EVM signal chain is ideal for high intermediate-frequency (IF) complex-feedback applications and contains a complex (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00073 — Dual-Wideband RF-to-Digital Receiver Design

The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this.  This reference EVEM coupled with a capture (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
WQFN (RTV) 32 Ultra Librarian
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