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LMK04001

ACTIVE

Low-noise jitter cleaner with 1430 to 1570-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS

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Data sheet

LMK04001

ACTIVE
Data sheet Order now

Product details

Function Cascaded PLLs Number of outputs 7 RMS jitter (fs) 150 Output frequency (min) (MHz) 0.35 Output frequency (max) (MHz) 1570 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Features Integrated VCO Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Cascaded PLLs Number of outputs 7 RMS jitter (fs) 150 Output frequency (min) (MHz) 0.35 Output frequency (max) (MHz) 1570 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Features Integrated VCO Rating Catalog Operating temperature range (°C) -40 to 85 Number of input channels 2
WQFN (RHS) 48 49 mm² 7 x 7

  • Cascaded PLLatinum PLL Architecture

  • PLL1

  • Phase detector rate of up to 40 MHz
  • Integrated Low-Noise Crystal Oscillator Circuit
  • Dual redundant input reference clock with LOS
  • PLL2

  • Normalized [1 Hz] PLL noise floor of -224 dBc/Hz
  • Phase detector rate up to 100 MHz
  • Input frequency-doubler
  • Integrated Low-Noise VCO
  • Ultra-Low RMS Jitter Performance

  • 150 fs RMS jitter (12 kHz – 20 MHz)
  • 200 fs RMS jitter (100 Hz – 20 MHz)
  • LVPECL/2VPECL, LVDS, and LVCMOS outputs
  • Support clock rates up to 1080 MHz
  • Default Clock Output (CLKout2) at power up
  • Five dedicated channel divider and delay blocks
  • Pin compatible family of clocking devices
  • Industrial Temperature Range: -40 to 85 °C
  • 3.15 V to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

    • Target Applications

  • Data Converter Clocking
  • Wireless Infrastructure
  • Networking, SONET/SDH, DSLAM
  • Medical
  • Military / Aerospace
  • Test and Measurement
  • Video
    •

  • Cascaded PLLatinum PLL Architecture

  • PLL1

  • Phase detector rate of up to 40 MHz
  • Integrated Low-Noise Crystal Oscillator Circuit
  • Dual redundant input reference clock with LOS
  • PLL2

  • Normalized [1 Hz] PLL noise floor of -224 dBc/Hz
  • Phase detector rate up to 100 MHz
  • Input frequency-doubler
  • Integrated Low-Noise VCO
  • Ultra-Low RMS Jitter Performance

  • 150 fs RMS jitter (12 kHz – 20 MHz)
  • 200 fs RMS jitter (100 Hz – 20 MHz)
  • LVPECL/2VPECL, LVDS, and LVCMOS outputs
  • Support clock rates up to 1080 MHz
  • Default Clock Output (CLKout2) at power up
  • Five dedicated channel divider and delay blocks
  • Pin compatible family of clocking devices
  • Industrial Temperature Range: -40 to 85 °C
  • 3.15 V to 3.45 V operation
  • Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

    • Target Applications

  • Data Converter Clocking
  • Wireless Infrastructure
  • Networking, SONET/SDH, DSLAM
  • Medical
  • Military / Aerospace
  • Test and Measurement
  • Video
    •

    The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

    The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.

    The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.

    The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

    The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.

    The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.

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    Technical documentation

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    Type Title Date
    * Data sheet LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs datasheet (Rev. J) 19 Sep 2011
    User guide LMK040xx Evaluation Board User's Guide (Rev. B) 08 Jan 2015
    Application note AN-1734 Using the LMK03000C to Clean Recovered Clocks (Rev. B) 26 Apr 2013
    Application note AN-1821 CPRI Repeater System (Rev. A) 26 Apr 2013
    Application note AN-1865 Frequency Synthesis and Planning for PLL Architectures (Rev. C) 26 Apr 2013
    Application note AN-1910 LMK04000 Family Phase Noise Characterization (Rev. A) 26 Apr 2013
    Application note AN-1939 Crystal Based Oscillator Design with the LMK04000 Family (Rev. A) 26 Apr 2013
    Application note Phase Synchronization with Multiple Devices and Frequencies (Rev. A) 26 Apr 2013
    Design guide Clock Conditioner Owner's Manual 10 Nov 2006

    Design & development

    For additional terms or required resources, click any title below to view the detail page where available.

    Software programming tool

    CODELOADER — CodeLoader Device Register Programming v4.19.0

    The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

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    Supported products & hardware

    Supported products & hardware

    Products
    Clock generators
    LMK02000 — 1 to 800-MHz, precision clock distributor with integrated PLL and 3 LVDS / 5 LVPECL outputs LMK02002 — 1 to 800-MHz, precision clock distributor with integrated PLL and 4 LVPECL outputs LMK03000 — 1185 to 1296-MHz, 800fs RMS jitter, precision clock conditioner with integrated VCO LMK03001 — 1470 to 1570-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO LMK03002 — 1566 to 1724-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO LMK03033 — 1843 to 2160-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO LMK03200 — Precision 0-delay clock conditioner with integrated VCO LMK03806 — Ultra-low jitter clock generator with 14 outputs
    Clock buffers
    LMK01000 — 1.6-GHz high performance clock buffer, divider, and distributor with 3 LVDS & 5 LVPECL outputs LMK01010 — 1.6-GHz high performance clock buffer, divider, and distributor with 8 LVDS outputs LMK01020 — 1.6-GHz high performance clock buffer, divider, and distributor with 8 LVPECL outputs LMK01801 — Dual clock distribution
    Clock jitter cleaners
    LMK04000 — Precision clock conditioners low-noise clock jitter cleaner with cascaded PLLs LMK04001 — Low-noise jitter cleaner with 1430 to 1570-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04002 — Low-noise jitter cleaner with 1600 to 1750-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04010 — Low-noise jitter cleaner with 1185 to 1296-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04011 — Low-noise jitter cleaner with 1430 to 1570-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04031 — Low-noise jitter cleaner with 1430 to 1570-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04033 — Low-noise jitter cleaner with 1840 to 2160-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04100 — Precision clock conditioners clock jitter cleaner with cascaded PLLs LMK04101 — Jitter cleaner with integrated 1430 to 1570-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04102 — Jitter cleaner with integrated 1600 to 1750-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04110 — Jitter cleaner with integrated 1185 to 1296-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04111 — Jitter cleaner with integrated 1430 to 1570-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04131 — Jitter cleaner with integrated 1430 to 1570-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04133 — Jitter cleaner with integrated 1840 to 2160-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04208 — Ultra low-noise clock jitter cleaner with 6 programmable outputs LMK04228 — Ultra low-noise clock jitter cleaner with dual loop PLLs LMK04806 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO LMK04808 — Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO LMK04816 — Three input low-noise clock jitter cleaner with dual loop PLLs LMK04821 — Ultra low jitter synthesizer and jitter cleaner with JESD204B support LMK04826 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0 LMK04906 — Ultra low noise clock jitter cleaner/multiplier with 6 programmable outputs
    RF PLLs & synthesizers
    LMX2430 — 3.0-GHz/0.8-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2433 — 3.6-GHz/1.7-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2434 — 5.0-GHz/2.5-GHz PLLatinum low power dual frequency synthesizer for RF personal communications LMX2470 — 2.6-GHz delta-sigma fractional-N PLL with 800-MHz integer-N PLL LMX2485 — 500-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485E — 50-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485Q-Q1 — 500MHz to 3GHz automotive delta-sigma low power dual PLL LMX2486 — 1-GHz to 4.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2487 — 1 to 6-GHz delta-sigma low power dual PLLatinum frequency synthesizer with 3.0-GHz integer PLL LMX2487E — 3-GHz to 7.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2502 — Frequency synthesizer system with integrated VCOs LMX2522 — PLLatinum dual frequency synthesizer system with integrated VCOs LMX2531 — High performance frequency synthesizer system with integrated VCO LMX2541 — Ultra-low noise PLLatinum frequency synthesizer with integrated VCO LMX2581 — 3.76-GHz wideband frequency synthesizer with integrated VCO
    Hardware development
    Evaluation board
    LMK00301EVAL — LMK00301 Evaluation Board LMK01000EVAL — 1.6 GHz Low Noise Clock Buffer, Divider, and Distributor LMK03033CEVAL — Precision Clock Conditioner with Integrated VCO (1843 - 2160 MHz) LMK03806BEVAL — LMK03806B Evaluation Board
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    Support software

    CLOCKDESIGNTOOL — Clock Design Tool Software

    The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

    Supported products & hardware

    Supported products & hardware

    Products
    Clock generators
    LMK02000 — 1 to 800-MHz, precision clock distributor with integrated PLL and 3 LVDS / 5 LVPECL outputs LMK02002 — 1 to 800-MHz, precision clock distributor with integrated PLL and 4 LVPECL outputs LMK03000 — 1185 to 1296-MHz, 800fs RMS jitter, precision clock conditioner with integrated VCO LMK03001 — 1470 to 1570-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO LMK03002 — 1566 to 1724-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO LMK03033 — 1843 to 2160-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO LMK03200 — Precision 0-delay clock conditioner with integrated VCO LMK03806 — Ultra-low jitter clock generator with 14 outputs
    Clock buffers
    LMK00301 — 3-GHz, 10-output differential fanout buffer / level translator LMK00304 — 3.1-GHz differential clock buffer/level translator with 4 configurable outputs LMK00306 — 3.1-GHz differential clock buffer/level translator with 6 configurable outputs LMK00308 — 3.1-GHz differential clock buffer/level translator with 8 configurable outputs LMK01000 — 1.6-GHz high performance clock buffer, divider, and distributor with 3 LVDS & 5 LVPECL outputs LMK01010 — 1.6-GHz high performance clock buffer, divider, and distributor with 8 LVDS outputs LMK01020 — 1.6-GHz high performance clock buffer, divider, and distributor with 8 LVPECL outputs LMK01801 — Dual clock distribution
    Clock jitter cleaners
    LMK04000 — Precision clock conditioners low-noise clock jitter cleaner with cascaded PLLs LMK04001 — Low-noise jitter cleaner with 1430 to 1570-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04002 — Low-noise jitter cleaner with 1600 to 1750-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04010 — Low-noise jitter cleaner with 1185 to 1296-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04011 — Low-noise jitter cleaner with 1430 to 1570-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04031 — Low-noise jitter cleaner with 1430 to 1570-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04033 — Low-noise jitter cleaner with 1840 to 2160-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04100 — Precision clock conditioners clock jitter cleaner with cascaded PLLs LMK04101 — Jitter cleaner with integrated 1430 to 1570-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04102 — Jitter cleaner with integrated 1600 to 1750-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04110 — Jitter cleaner with integrated 1185 to 1296-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04111 — Jitter cleaner with integrated 1430 to 1570-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04131 — Jitter cleaner with integrated 1430 to 1570-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04133 — Jitter cleaner with integrated 1840 to 2160-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04208 — Ultra low-noise clock jitter cleaner with 6 programmable outputs LMK04228 — Ultra low-noise clock jitter cleaner with dual loop PLLs LMK04806 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO LMK04808 — Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO LMK04816 — Three input low-noise clock jitter cleaner with dual loop PLLs LMK04826 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0 LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0. LMK04906 — Ultra low noise clock jitter cleaner/multiplier with 6 programmable outputs
    RF PLLs & synthesizers
    LMX2430 — 3.0-GHz/0.8-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2433 — 3.6-GHz/1.7-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2434 — 5.0-GHz/2.5-GHz PLLatinum low power dual frequency synthesizer for RF personal communications LMX2485 — 500-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485E — 50-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485Q-Q1 — 500MHz to 3GHz automotive delta-sigma low power dual PLL LMX2486 — 1-GHz to 4.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2487 — 1 to 6-GHz delta-sigma low power dual PLLatinum frequency synthesizer with 3.0-GHz integer PLL LMX2487E — 3-GHz to 7.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2531 — High performance frequency synthesizer system with integrated VCO LMX2541 — Ultra-low noise PLLatinum frequency synthesizer with integrated VCO LMX2581 — 3.76-GHz wideband frequency synthesizer with integrated VCO
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    Simulation model

    LMK04001 IBIS Model

    SNOM111.ZIP (52 KB) - IBIS Model
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    Design tool

    CLOCK-TREE-ARCHITECT — Clock tree architect programming software

    Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
    Design now
    Simulation tool

    PSPICE-FOR-TI — PSpice® for TI design and simulation tool

    PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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    WQFN (RHS) 48 Ultra Librarian
    TI's Standard Terms and Conditions for Evaluation Items apply.

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