LP2995

ACTIVE

DDR Termination Regulator

Product details

Vin (min) (V) 2.2 Vin (max) (V) 5.5 Vout (min) (V) 1.21 Vout (max) (V) 1.26 Features No external resistors Iq (typ) (mA) 0.25 Rating Catalog Operating temperature range (°C) 0 to 125 Product type DDR DDR memory type DDR
Vin (min) (V) 2.2 Vin (max) (V) 5.5 Vout (min) (V) 1.21 Vout (max) (V) 1.26 Features No external resistors Iq (typ) (mA) 0.25 Rating Catalog Operating temperature range (°C) 0 to 125 Product type DDR DDR memory type DDR
HSOIC (DDA) 8 29.4 mm² 4.9 x 6 SOIC (D) 8 29.4 mm² 4.9 x 6 WQFN (NHP) 16 16 mm² 4 x 4
  • Low Output Voltage Offset
  • Works with +5v, +3.3v and 2.5v Rails
  • Source and Sink Current
  • Low External Component Count
  • No External Resistors Required
  • Linear Topology
  • Available in SOIC-8, SO PowerPAD-8 or WQFN-16 Packages
  • Low Cost and Easy to Use

All trademarks are the property of their respective owners.

  • Low Output Voltage Offset
  • Works with +5v, +3.3v and 2.5v Rails
  • Source and Sink Current
  • Low External Component Count
  • No External Resistors Required
  • Linear Topology
  • Available in SOIC-8, SO PowerPAD-8 or WQFN-16 Packages
  • Low Cost and Easy to Use

All trademarks are the property of their respective owners.

The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS.

The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS.

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Technical documentation

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Type Title Date
* Data sheet LP2995 DDR Termination Regulator datasheet (Rev. M) 19 Mar 2013
Application note Limiting DDR Termination Regulators’ Inrush Current 23 Aug 2016
EVM User's guide AN-1241 LP2995 Evaluation Board (Rev. B) 07 May 2013
Application note AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) 06 May 2013
Application note DDR-SDRAM Termination Simplified Using A Linear Regulator 23 Jul 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

LP2995 PSpice Transient Model

SNVMAH6.ZIP (71 KB) - PSpice Model
Simulation model

LP2995 Unencrypted PSpice Transient Model

SNVMAH5.ZIP (4 KB) - PSpice Model
Reference designs

TIDA-010011 — High efficiency power supply architecture reference design for protection relay processor module

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
HSOIC (DDA) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
WQFN (NHP) 16 Ultra Librarian

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