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SN74AHCT1G00

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Single 2-input, 4.5-V to 5.5-V NAND gate with TTL-compatible CMOS inputs

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Data sheet

SN74AHCT1G00

ACTIVE
Data sheet Order now

Product details

Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Operating Range of 4.5 V to 5.5 V
  • Maximum tpd of 7.1 ns at 5 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±8-mA Output Drive at 5 V
  • Inputs Are TTL-Voltage Compatible
  • Latch-up Performance Exceeds 250 mA Per JESD 17
  • Operating Range of 4.5 V to 5.5 V
  • Maximum tpd of 7.1 ns at 5 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±8-mA Output Drive at 5 V
  • Inputs Are TTL-Voltage Compatible
  • Latch-up Performance Exceeds 250 mA Per JESD 17

The SN74AHCT1G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.

The SN74AHCT1G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.
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Technical documentation

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Type Title Date
* Data sheet SN74AHCT1G00 Single 2-Input Positive-NAND Gate datasheet (Rev. P) PDF | HTML 01 Feb 2024
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

SN74AHCT1G00 Behavioral SPICE Model

SCLM248.ZIP (7 KB) - PSpice Model
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Simulation model

SN74AHCT1G00 IBIS Model

SCLM011.ZIP (7 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOT-23 (DBV) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
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