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SN75372

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10-mA/40-mA dual-Channal gate driver with enable pin

Product details

Number of channels 2 Power switch MOSFET Peak output current (A) 0.5 Input supply voltage (min) (V) 4.75 Input supply voltage (max) (V) 7 Features Low Quiescent Current Operating temperature range (°C) 0 to 70 Rise time (ns) 20 Fall time (ns) 20 Propagation delay time (µs) 0.065 Input threshold CMOS, TTL Channel input logic Non-Inverting Input negative voltage (V) 0 Rating Catalog Driver configuration Dual inputs
Number of channels 2 Power switch MOSFET Peak output current (A) 0.5 Input supply voltage (min) (V) 4.75 Input supply voltage (max) (V) 7 Features Low Quiescent Current Operating temperature range (°C) 0 to 70 Rise time (ns) 20 Fall time (ns) 20 Propagation delay time (µs) 0.065 Input threshold CMOS, TTL Channel input logic Non-Inverting Input negative voltage (V) 0 Rating Catalog Driver configuration Dual inputs
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6 SOP (PS) 8 48.36 mm² 6.2 x 7.8
  • Dual Circuits Capable of Driving High-Capacitance Loads at High Speeds
  • Output Supply Voltage Range up to 24 V
  • Low Standby Power Dissipation

  • Dual Circuits Capable of Driving High-Capacitance Loads at High Speeds
  • Output Supply Voltage Range up to 24 V
  • Low Standby Power Dissipation

The SN75372 is a dual NAND gate interface circuit designed to drive power MOSFETs from TTL inputs. It provides high current and voltage levels necessary to drive large capacitive loads at high speeds. The device operates from a VCC1 of 5 V and a VCC2 of up to 24 V.

The SN75372 is characterized for operation from 0°C to 70°C.

The SN75372 is a dual NAND gate interface circuit designed to drive power MOSFETs from TTL inputs. It provides high current and voltage levels necessary to drive large capacitive loads at high speeds. The device operates from a VCC1 of 5 V and a VCC2 of up to 24 V.

The SN75372 is characterized for operation from 0°C to 70°C.

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Technical documentation

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Type Title Date
* Data sheet SN75372 Dual MOSFET Driver datasheet (Rev. A) 22 Sep 2023
Application note Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs PDF | HTML 22 Jan 2024
Application brief External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Application brief How to overcome negative voltage transients on low-side gate drivers' inputs 18 Jan 2019

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Package Pins CAD symbols, footprints & 3D models
PDIP (P) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
SOP (PS) 8 Ultra Librarian

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