TMS320C6421

Name: TMS320C6421
Brand: TI
SKU: TMS320C6421
Price: 9.987 USD

ACTIVE

C64x+ fixed point DSP- up to 600MHz, 8 Bit EMIFA , 16-Bit DDR2, SDRAM

Order now

Data sheet

document-pdfAcrobat TMS320C6421 Fixed-Point Digital Signal Processor datasheet (Rev. D)

Errata

document-pdfAcrobat
TMS320C6424/21 Digital Signal Processor Silicon Errata (Revs 1.3 1.2 1.1 & 1.0) (Rev. D)

TMS320C6421

ACTIVE

Data sheet

Order now

Product details

DSP type

1 C64x+

DSP (max) (MHz)

400, 500, 600

CPU

32-/64-bit

Operating system

DSP/BIOS

Ethernet MAC

10/100

Rating

Catalog

Operating temperature range (°C)

0 to 90

DSP type

1 C64x+

DSP (max) (MHz)

400, 500, 600

CPU

32-/64-bit

Operating system

DSP/BIOS

Ethernet MAC

10/100

Rating

Catalog

Operating temperature range (°C)

0 to 90

BGA (ZDU)

376

529 mm² 23 x 23

NFBGA (ZWT)

361

256 mm² 16 x 16

High-Performance Digital Signal Processor (C6421)
- 2.5-, 2.-, 1.67, 1.43-ns Instruction Cycle Time
- 400-, 500-, 600-MHz C64x+™ Clock Rate
- Eight 32-Bit C64x+ Instructions/Cycle
- 3200, 4000, 4800, 5600 MIPS
- Fully Software-Compatible With C64x
- Commercial and Automotive (Q or S suffix) Grades
- Low-Power Device (L suffix)
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2 Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
  - Protected Mode Operation
  - Exceptions Support for Error Detection and Program Redirection
  - Hardware Support for Modulo Loop Auto-Focus Module Operation
C64x+ Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2 Increased Orthogonality
- C64x+ Extensions
  - Compact 16-bit Instructions
  - Additional Instructions to Support Complex Multiplies
C64x+ L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program RAM/Cache [Flexible Allocation]
- 384K-Bit (48K-Byte) L1D Data RAM/Cache [Flexible Allocation]
- 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
Endianess: Supports Both Little Endian and Big Endian
External Memory Interfaces (EMIFs)
- 16-Bit DDR2 SDRAM Memory Controller With 128M-Byte Address Space (1.8-V I/O)
  - Supports up to 266-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
- Asynchronous 8-Bit-Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
  - Flash Memory Interfaces
    - NOR (8-Bit-Wide Data)
    - NAND (8-Bit-Wide Data)
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
One 64-Bit Watch Dog Timer
One UART With RTS and CTS Flow Control
Master/Slave Inter-Integrated Circuit (I2C Bus™)
Multichannel Buffered Serial Port (McBSP0)
- I2S and TDM
- AC97 Audio Codec Interface
- SPI
- Standard Voice Codec Interface (AIC12)
- Telecom Interfaces - ST-Bus, H-100
- 128 Channel Mode
Multichannel Audio Serial Port (McASP0)
- Four Serializers and SPDIF (DIT) Mode
16-Bit Host-Port Interface (HPI)
10/100 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Supports Multiple Media Independent Interfaces (MII, RMII)
- Management Data I/O (MDIO) Module
VLYNQ™ Interface (FPGA Interface)
Three Pulse Width Modulator (PWM) Outputs
On-Chip ROM Bootloader
Individual Power-Savings Modes
Flexible PLL Clock Generators
IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
Packages:
- 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
- 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
0.09-µm/6-Level Cu Metal Process (CMOS)
3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-Q6/-Q5/-Q4)
3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
Applications:
- Telecom
- Audio
- Industrial Applications

All trademarks are the property of their respective owners.

High-Performance Digital Signal Processor (C6421)
- 2.5-, 2.-, 1.67, 1.43-ns Instruction Cycle Time
- 400-, 500-, 600-MHz C64x+™ Clock Rate
- Eight 32-Bit C64x+ Instructions/Cycle
- 3200, 4000, 4800, 5600 MIPS
- Fully Software-Compatible With C64x
- Commercial and Automotive (Q or S suffix) Grades
- Low-Power Device (L suffix)
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2 Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
  - Protected Mode Operation
  - Exceptions Support for Error Detection and Program Redirection
  - Hardware Support for Modulo Loop Auto-Focus Module Operation
C64x+ Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2 Increased Orthogonality
- C64x+ Extensions
  - Compact 16-bit Instructions
  - Additional Instructions to Support Complex Multiplies
C64x+ L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program RAM/Cache [Flexible Allocation]
- 384K-Bit (48K-Byte) L1D Data RAM/Cache [Flexible Allocation]
- 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
Endianess: Supports Both Little Endian and Big Endian
External Memory Interfaces (EMIFs)
- 16-Bit DDR2 SDRAM Memory Controller With 128M-Byte Address Space (1.8-V I/O)
  - Supports up to 266-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
- Asynchronous 8-Bit-Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
  - Flash Memory Interfaces
    - NOR (8-Bit-Wide Data)
    - NAND (8-Bit-Wide Data)
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
One 64-Bit Watch Dog Timer
One UART With RTS and CTS Flow Control
Master/Slave Inter-Integrated Circuit (I2C Bus™)
Multichannel Buffered Serial Port (McBSP0)
- I2S and TDM
- AC97 Audio Codec Interface
- SPI
- Standard Voice Codec Interface (AIC12)
- Telecom Interfaces - ST-Bus, H-100
- 128 Channel Mode
Multichannel Audio Serial Port (McASP0)
- Four Serializers and SPDIF (DIT) Mode
16-Bit Host-Port Interface (HPI)
10/100 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Supports Multiple Media Independent Interfaces (MII, RMII)
- Management Data I/O (MDIO) Module
VLYNQ™ Interface (FPGA Interface)
Three Pulse Width Modulator (PWM) Outputs
On-Chip ROM Bootloader
Individual Power-Savings Modes
Flexible PLL Clock Generators
IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
Packages:
- 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
- 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
0.09-µm/6-Level Cu Metal Process (CMOS)
3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-Q6/-Q5/-Q4)
3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
Applications:
- Telecom
- Audio
- Industrial Applications

All trademarks are the property of their respective owners.

The TMS320C64x+™ DSPs (including the TMS320C6421 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6421 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The C6421 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6421 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 128K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 384K-bit memory space that can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP0); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 1 UART with hardware handshaking support; 3 pulse width modulator (PWM) peripherals; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6421 and the network. The C6421 EMAC supports 10Base-T and 100Base-TX or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow C6421 to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6421 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow C6421 to easily control peripheral devices and/or communicate with host processors.

filter

Find other Digital signal processors (DSPs)

Download View video with transcript Video

No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2E^TM support forums.

Technical documentation

star

=Top documentation for this product selected by TI

No results found. Please clear your search and try again.

View all 42

	Type	Title		Date
*	Data sheet	TMS320C6421 Fixed-Point Digital Signal Processor datasheet (Rev. D)		10 Jun 2008
*	Errata	TMS320C6424/21 Digital Signal Processor Silicon Errata (Revs 1.3 1.2 1.1 & 1.0) (Rev. D)		12 Aug 2011
	Application note	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	19 May 2021
	User guide	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		01 Jun 2020
	Application note	Plastic Ball Grid Array [PBGA] Application Note (Rev. B)		13 Aug 2015
	Application note	Using the TMS320C642x Bootloader (Rev. B)		23 Mar 2012
	Application note	TMS320C642x Power Consumption Summary (Rev. D)		17 Feb 2012
	Application note	Introduction to TMS320C6000 DSP Optimization		06 Oct 2011
	User guide	TMS320C642x DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. D)		25 Mar 2011
	User guide	TMS320C642x DSP DDR2 Memory Controller User's Guide (Rev. B)		12 Jan 2011
	User guide	TMS320C642x DSP EMAC/MDIO User's Guide (Rev. C)		23 Dec 2010
	User guide	TMS320C642x DSP Pulse-Width Modulator (PWM) User's Guide (Rev. B)		05 Aug 2010
	User guide	TMS320C642x DSP 64-Bit Timer User's Guide (Rev. A)		03 Aug 2010
	User guide	TMS320C64x+ DSP Megamodule Reference Guide (Rev. K)		03 Aug 2010
	User guide	TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J)		30 Jul 2010
	User guide	TMS320C642x DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guide (Rev. C)		15 Dec 2009
	User guide	TMS320C642x DSP Asynchronous External Memory Interface (EMIF) User's Guide (Rev. B)		24 Feb 2009
	Application note	Implementing DDR2 PCB Layout on the TMS320C6421 DSP (Rev. C)		13 Feb 2009
	User guide	TMS320C64x+ DSP Cache User's Guide (Rev. B)		11 Feb 2009
	Application note	12Vin C642x Power using Integrated-FET DC/DC Converters and LDO		09 Oct 2008
	Application note	5Vin C642x Power using a PMIC (Multi-output DC/DC Converter)		09 Oct 2008
	Application note	TMS320C620x/C642x McBSP: UART (Rev. C)		09 Sep 2008
	Application note	Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A)		21 Aug 2008
	Application note	Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A)		17 Jul 2008
	User guide	TMS320C642x DSP Host Port Interface (HPI) User's Guide (Rev. A)		16 Jul 2008
	User guide	TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A)		05 May 2008
	User guide	TMS320C642x DSP General-Purpose Input/Output (GPIO) User's Guide (Rev. A)		18 Mar 2008
	User guide	TMS320C642x DSP Multichannel Audio Serial Port (McASP) User's Guide (Rev. C)		13 Mar 2008
	User guide	TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B)		06 Mar 2008
	User guide	TMS320C642x DSP Enhanced DMA (EDMA) Controller User's Guide (Rev. A)		03 Mar 2008
	User guide	TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (Rev. A)		05 Feb 2008
	User guide	TMS320C642x DSP Phase-Locked Loop Controller (PLLC) User's Guide (Rev. B)		12 Dec 2007
	Application note	Using DMA with Framework Components for C64x+ (Rev. A)		29 Oct 2007
	User guide	TMS320C642x DSP VLYNQ Port User's Guide (Rev. B)		20 Sep 2007
	User guide	TMS320C642x DSP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. B)		17 Sep 2007
	Application note	TMS320C642x Pin Multiplexing Utility		09 Jul 2007
	Application note	Thermal Considerations for the DM64xx, DM64x, and C6000 Devices		20 May 2007
	User guide	TMS320C642x DSP Peripherals Overview Reference Guide		04 Mar 2007
	User guide	TMS320C64x+ DSP Big-Endian Library Programmer's Reference		10 Mar 2006
	User guide	TMS320C64x+ Image/Video Processing Library Programmer's Reference		10 Mar 2006
	Application note	Migrating from TMS320C64x to TMS320C64x+ (Rev. A)		20 Oct 2005
	Test report	Download: C64x+ Benchmarks (v1.00)		06 Jul 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices. The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2. It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

Not available on TI.com

Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com

Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com

Driver or library

SPRC122 — C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

Supported products & hardware

Products

Digital signal processors (DSPs)

SM320C6201-EP — Enhanced product C6201 fixed point DSP

SM320C6455-EP — Enhanced product C6455 fixed point DSP

SMJ320C6201B — Fixed Point Digital Signal Processor, Military

SMJ320C6203 — Military grade C62x fixed point DSP - ceramic package

TMS320C6202B — C62x fixed point DSP- up to 300MHz, 384KB

TMS320C6203B — C62x fixed point DSP- up to 300MHz, 896KB

TMS320C6204 — Fixed-Point Digital Signal Processor

TMS320C6205 — Fixed-Point Digital Signal Processor

TMS320C6211B — C62x fixed point DSP- up to 167MHz

TMS320C6412 — C64x fixed point DSP- up to 720MHz, McBSP, McASP, I2cC, Ethernet

TMS320C6414 — C64x fixed point DSP- up to 720MHz, McBSP

TMS320C6414T — C64x fixed point DSP- up to 1GHz, McBSP

TMS320C6415 — C64x fixed point DSP- up to 720MHz, McBSP, PCI

TMS320C6415T — C64x fixed point DSP- up to 850MHz, McBSP, PCI

TMS320C6416 — C64x fixed point DSP- up to 720MHz, McBSP, PCI, VCP/TCP

TMS320C6416T — C64x fixed point DSP- up to 850MHz, McBSP, PCI, VCP/TCP

TMS320C6421 — C64x+ fixed point DSP- up to 600MHz, 8 Bit EMIFA , 16-Bit DDR2, SDRAM

TMS320C6421Q — C64x+ fixed point DSP- up to 600MHz, 8 Bit EMIFA, 16-Bit DDR2

TMS320C6424 — C64x+ fixed point DSP- up to 600MHz, 16/8-Bit EMIFA, 32/16 Bit DDR2, SDRAM

TMS320C6424Q — C64x+ fixed point DSP- up to 600MHz, 16/8-Bit EMIFA, 32/16 Bit DDR2

TMS320C6452 — C64x+ fixed point DSP- up to 900MHz, 1Gbps Ethernet

TMS320C6454 — C64x+ fixed point DSP- up to 1GHz, 64-Bit EMIFA, 32/16 Bit DDR2, 1 Gbps Ethernet

TMS320C6455 — C64x+ fixed-point DSP up to 1.2GHz, 64-bit EMIFA, 32- and 16-bit DDR2, 1Gbps Ethernet

TMS320C6457 — Communications infrastructure digital signal processor

TMS320C6474 — Multicore Digital Signal Processor

TMS320DM640 — Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM641 — Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642 — Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642Q — Video/imaging fixed-point digital signal processor

TMS320DM6431 — Digital Media Processor

TMS320DM6431Q — Digital media processor, up to 2400 MIPS, 300 MHz clock rate

TMS320DM6433 — Digital Media Processor

TMS320DM6435 — Digital Media Processor

TMS320DM6435Q — Digital media processor, up to 4800 MIPS, 600 MHz clock rate, 1 McASP, 1 McBSP

TMS320DM6437 — Digital Media Processor

TMS320DM6437Q — Digital media processor, up to 4800 MIPS, 600 MHz clock rate, 1 McASP, 2 McBSP

TMS320DM6441 — DaVinci Digital Media System-on-Chip

TMS320DM6443 — DaVinci Digital Media System-on-Chip

TMS320DM6446 — DaVinci Digital Media System-on-Chip

Download

Driver or library

SPRC264 — TMS320C5000/6000 Image Library (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

View Options

Driver or library

SPRC265 — TMS320C6000 DSP Library (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

View Options

Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

View Options

IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

parametric-filter Digital signal processors (DSPs)
parametric-filter Arm-based processors
parametric-filter MSP430 microcontrollers
parametric-filter C2000 real-time microcontrollers
parametric-filter Arm-based microcontrollers
parametric-filter Signal conditioners
parametric-filter mmWave radar sensors
parametric-filter Wi-Fi products
parametric-filter Sub-1 GHz products
parametric-filter Digital power isolated controllers

Launch

Download options

Software codec

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies DSP VOIP, speech and audio codecs

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)

From: Adaptive Digital Technologies, Inc.

Visit partner site

Software codec

VOCAL-3P-DSPVOIPCODECS — Vocal technologies DSP VoIP codecs

With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)

From: VOCAL Technologies, Ltd.

Visit partner site

Simulation model