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TMS320C6746

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Low power C674x floating-point DSP- 456MHz

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Data sheet
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TMS320C6746

ACTIVE
Data sheet Order now

Product details

DSP type 1 C674x DSP (max) (MHz) 375, 456 CPU 32-/64-bit Operating system SYS/BIOS Security Basic Secure Boot Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C674x DSP (max) (MHz) 375, 456 CPU 32-/64-bit Operating system SYS/BIOS Security Basic Secure Boot Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 105
NFBGA (ZCE) 361 169 mm² 13 x 13 NFBGA (ZWT) 361 256 mm² 16 x 16
  • 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2746 MFLOPS
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Floating-Point VLIW DSP Core
    • Load-Store Architecture With Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units:
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP × SP → SP Per Clock
        • 2 SP × SP → DP Every Two Clocks
        • 2 SP × DP → DP Every Three Clocks
        • 2 DP × DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • Software Support
    • TI DSPBIOS
    • Chip Support Library and DSP Library
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM With 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller With one of the Following:
      • 16-Bit DDR2 SDRAM With 256-MB Address Space
      • 16-Bit mDDR SDRAM With 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus™)
  • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM Per Core
      • 512 Bytes of Data RAM Per Core
      • PRUSS can be Disabled Through Software to Save Power
      • Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
  • Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Timestamps
  • Packages:
    • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
    • 361-Ball Pb-Free PBGA [ZWT Suffix],
      0.80-mm Ball Pitch
  • Commercial, Extended, or Industrial Temperature

All trademarks are the property of their respective owners.

  • 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2746 MFLOPS
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Floating-Point VLIW DSP Core
    • Load-Store Architecture With Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units:
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP × SP → SP Per Clock
        • 2 SP × SP → DP Every Two Clocks
        • 2 SP × DP → DP Every Three Clocks
        • 2 DP × DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • Software Support
    • TI DSPBIOS
    • Chip Support Library and DSP Library
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM With 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller With one of the Following:
      • 16-Bit DDR2 SDRAM With 256-MB Address Space
      • 16-Bit mDDR SDRAM With 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus™)
  • One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM Per Core
      • 512 Bytes of Data RAM Per Core
      • PRUSS can be Disabled Through Software to Save Power
      • Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces With START, ENABLE, and WAIT Controls
  • Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Timestamps
  • Packages:
    • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
    • 361-Ball Pb-Free PBGA [ZWT Suffix],
      0.80-mm Ball Pitch
  • Commercial, Extended, or Industrial Temperature

All trademarks are the property of their respective owners.

The TMS320C6746 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a
32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The DSP L2 is accessible by other hosts in the system.

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; two I2C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) provides a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

The TMS320C6746 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a
32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The DSP L2 is accessible by other hosts in the system.

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; two I2C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) provides a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
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Technical documentation

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Type Title Date
* Data sheet TMS320C6746 Fixed- and Floating-Point DSP datasheet (Rev. F) PDF | HTML 31 Jan 2017
* Errata TMS320C6746 Fixed- and Floating-Point DSP (Revs 2.3, 2.1, 2.0, 1.1 & 1.0) (Rev. H) 21 Mar 2014
* User guide TMS320C6746 DSP Technical Reference Manual (Rev. C) 12 Sep 2016
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 May 2021
Application note OMAPL138/C6748 ROM Bootloader Resources and FAQ (Rev. A) PDF | HTML 21 Jan 2021
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 Jun 2020
Application note Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x 20 Dec 2019
User guide L138/C6748 development kit (LCDK) (Rev. A) PDF | HTML 18 Sep 2019
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 11 Jun 2019
Application note Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx 25 Apr 2019
Application note TMS320C6748/46/42 power consumption summary 26 Mar 2019
Application note General Hardware Design/BGA PCB Design/BGA 22 Feb 2019
Application note OMAP-L13x / C674x / AM1x schematic review guidelines PDF | HTML 14 Feb 2019
Application note McASP Design Guide - Tips, Tricks, and Practical Examples 10 Jan 2019
User guide PRU Assembly Instruction User Guide 16 Feb 2018
Application note Processor SDK RTOS Audio Benchmark Starter Kit 12 Apr 2017
Application note TI DSP Benchmarking 13 Jan 2016
Application note Using the TMS320C6748/C6746/C6742 Bootloader (Rev. F) 23 Jan 2014
User guide System Analyzer User's Guide (Rev. F) 18 Nov 2013
Application note OMAP-L132/L138, TMS320C6742/6/8 Pin Multiplexing Utility (Rev. B) 27 Sep 2013
Application note Powering the TMS320C6742, TMS320C6746, and TMS320C6748 With the TPS650061 19 Dec 2011
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
User guide TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F) 14 Sep 2011
Application note High-Vin, High-Efficiency Power Solution Using DC/DC Converter With DVFS (Rev. C) 29 Aug 2011
Application note Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO (Rev. B) 29 Aug 2011
Application note Simple Power Solution Using LDOs (Rev. B) 29 Aug 2011
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 19 May 2011
User guide TMS320C674x DSP Megamodule Reference Guide (Rev. A) 03 Aug 2010
User guide TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) 30 Jul 2010
Application note High-Efficiency Power Solution Using DC/DC Converters With DVFS (Rev. A) 05 May 2010
Application note High-Integration, High-Efficiency Power Solution Using DC/DC Converters w/DVFS (Rev. A) 05 May 2010
User guide OMAP-L138/C6748/C6746 Programmable Real-Time Unit Subsystem 24 Aug 2009
Application note TMS320C6748/46/42 & OMAP-L132/L138 USB Downstream Host Compliance Testing 17 Aug 2009
Application note TMS320C6748/46/42 & OMAP-L1x8 USB Upstream Device Compliance Testing 17 Aug 2009
Application note TMS320C6748/46/42 Complementary Products 20 Jul 2009
White paper Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core 24 Jun 2009
Application note TMS320C674x/OMAP-L1x USB Compliance Checklist 12 Mar 2009
User guide TMS320C674x DSP Cache User's Guide (Rev. A) 11 Feb 2009

Design & development

Power-supply solutions

Find available power-supply solutions for the TMS320C6746. TI offers power-supply solutions for TI and non-TI systems on a chip (SoCs), processors, microcontrollers, sensors, and field-programmable gate arrays (FPGAs).

View solutions
Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Development kit

TMDSLCDK138 — OMAP-L138 development kit (LCDK)

The OMAP-L138 DSP+Arm9™ development kit will enable fast and easy Linux software and hardware development. This scalable platform will ease and accelerate software and hardware development of everyday applications that require real-time signal processing and control functional, including (...)

User guide: PDF | HTML
Not available on TI.com
Development kit

TMDSLCDK6748 — TMS320C6748 DSP development kit (LCDK)

The TMS320C6748 DSP development kit (LCDK) is a scalable platform that breaks down development barriers for applications that require embedded analytics and real-time signal processing, including biometric analytics, communications and audio. The low-cost LCDK will also speed and ease your hardware (...)

User guide: PDF | HTML
Not available on TI.com
Software development kit (SDK)

PROCESSOR-SDK-C6748 — Processor SDK for C6748 Processors TI-RTOS Support

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
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Software development kit (SDK)

PROCESSOR-SDK-RTOS-OMAPL138 — TI-RTOS Processor SDK for OMAP-L138, OMAP-L132 and C6748, C6746, C6742 (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
OMAP-L138 — Low power C674x floating-point DSP + Arm9 processor - up to 456MHz
Digital signal processors (DSPs)
TMS320C6742 — Low power C674x floating-point DSP- 200MHz TMS320C6746 — Low power C674x floating-point DSP- 456MHz TMS320C6748 — Low power C674x floating-point DSP- 456MHz, SATA
Hardware development
Development kit
TMDSLCDK138 — OMAP-L138 development kit (LCDK) TMDSLCDK6748 — TMS320C6748 DSP development kit (LCDK)
Download options
Driver or library

MATHLIB — DSP Math Library for Floating Point Devices

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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Driver or library

SPRC264 — TMS320C5000/6000 Image Library (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
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Driver or library

SPRC265 — TMS320C6000 DSP Library (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
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Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

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Software codec

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies DSP VOIP, speech and audio codecs

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
From: Adaptive Digital Technologies, Inc.
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Software codec

VOCAL-3P-DSPVOIPCODECS — Vocal technologies DSP VoIP codecs

With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)
From: VOCAL Technologies, Ltd.
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Simulation model

C6746 ZCE BSDL Model (Rev. B)

SPRM373B.ZIP (18 KB) - BSDL Model
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Simulation model

C6746 ZCE IBIS Model (Rev. B)

SPRM375B.ZIP (120 KB) - IBIS Model
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Simulation model

C6746 ZWT BSDL Model (Rev. B)

SPRM372B.ZIP (18 KB) - BSDL Model
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Simulation model

C6746 ZWT IBIS Model (Rev. B)

SPRM374B.ZIP (121 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
NFBGA (ZCE) 361 Ultra Librarian
NFBGA (ZWT) 361 Ultra Librarian
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