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TPS53317

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Low Input Voltage, 6A Synchronous Step-Down SWIFT™ Converter for DDR Memory Termination

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Data sheet

TPS53317

ACTIVE
Data sheet Order now

Product details

Vin (min) (V) 1 Vin (max) (V) 6 Vout (min) (V) -0.3 Vout (max) (V) 3.6 Features Complete Solution Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.32 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 1 Vin (max) (V) 6 Vout (min) (V) -0.3 Vout (max) (V) 3.6 Features Complete Solution Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.32 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
VQFN (RGB) 20 14 mm² 4 x 3.5
  • TI proprietary Integrated MOSFET and Packaging Technology
  • Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
  • External Tracking
  • Minimum External Components Count
  • to 6-V Conversion Voltage
  • D-CAP+ Mode Architecture
  • Supports All MLCC Output Capacitors and SP/POSCAP
  • Selectable SKIP Mode or Forced CCM
  • Optimized Efficiency at Light and Heavy Loads
  • Selectable 600-kHz or 1-MHz Switching Frequency
  • Selectable Overcurrent Limit (OCL)
  • Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
  • Adjustable Output Voltage from to 2 V
  • 3.5 mm × 4 mm, 20-Pin VQFN Package
  • TI proprietary Integrated MOSFET and Packaging Technology
  • Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
  • External Tracking
  • Minimum External Components Count
  • to 6-V Conversion Voltage
  • D-CAP+ Mode Architecture
  • Supports All MLCC Output Capacitors and SP/POSCAP
  • Selectable SKIP Mode or Forced CCM
  • Optimized Efficiency at Light and Heavy Loads
  • Selectable 600-kHz or 1-MHz Switching Frequency
  • Selectable Overcurrent Limit (OCL)
  • Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
  • Adjustable Output Voltage from to 2 V
  • 3.5 mm × 4 mm, 20-Pin VQFN Package

The device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with bothsink and source capability. The device employs D-CAP+ mode operation that provides ease of use, low external componentcount and fast transient response. The device can also be used for other point-of-load (POL)regulation applications requiring up to 6 A. In addition, the device supports full, 6-A, outputsinking current capability with tight voltage regulation.

The device features two switching frequency settings (600 kHz and 1 MHz), integrateddroop support, external tracking capability, pre-bias startup, output soft discharge, integratedbootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic andSP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from to 2.0 V.

The device is available in the 3.5 mm × 4 mm, 20-pin, VQFNpackage (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.

For all available packages, see the orderable addendum at the end of the data sheet.

The device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with bothsink and source capability. The device employs D-CAP+ mode operation that provides ease of use, low external componentcount and fast transient response. The device can also be used for other point-of-load (POL)regulation applications requiring up to 6 A. In addition, the device supports full, 6-A, outputsinking current capability with tight voltage regulation.

The device features two switching frequency settings (600 kHz and 1 MHz), integrateddroop support, external tracking capability, pre-bias startup, output soft discharge, integratedbootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic andSP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from to 2.0 V.

The device is available in the 3.5 mm × 4 mm, 20-pin, VQFNpackage (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.

For all available packages, see the orderable addendum at the end of the data sheet.
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Technical documentation

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Type Title Date
* Data sheet TPS53317 6-A Output, D-CAP+ Mode, Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination datasheet (Rev. D) PDF | HTML 10 Jul 2015
Selection guide SWIFT DC/DC Converters Selector Guide (Rev. G) 06 Feb 2019
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
EVM User's guide Using the TPS53317EVM-750 D-CAP+™ Mode Synchronous Step-Down Integrated FETs Con 06 Sep 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

TPS53317 IBIS Model

SLUM347.ZIP (10 KB) - IBIS Model
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Simulation model

TPS53317 PSpice Transient Model

SLUM370.ZIP (64 KB) - PSpice Model
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Package Pins CAD symbols, footprints & 3D models
VQFN (RGB) 20 Ultra Librarian
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Ordering & quality

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