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Fixed data center switch

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Block diagram

Fixed data center switch

Block diagram

Overview

Our integrated circuits and reference designs help you create data center switches with ultra-high bandwidth and low-power consumption. Use the interactive reference diagram below to design a high-speed Ethernet switch with the right interface, physical interface device (PHY) and power management products to support the connectivity needs of modern Ethernet switch fabrics.

Design requirements

Modern data center switch designs require:

  • Highly-efficient power solutions for the latest-generation FPGAs, ASICs and CPUs.
  • Best-in-class signal integrity for ever increasing data rates.
  • Reduced system downtime through detection and prevention of damaging conditions.
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Block diagram

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Fixed data center switch

JTAG JTAG AC AC -48V -48V HV DC Bus HV DC Bus N+1 PSU N+1 PSU DC/DC DC/DC IBV1 IBV1 Hot swap controller Hot swap controller AC/DC AC/DC IBV1 IBV1 FET FET Bus converter (optional) Bus converter (optional) eFuse eFuse DC/DC DC/DC IBV2 IBV2 POL power (FPGA, ASIC, merchant Si, clocks, etc.) POL power (FPGA, ASIC, merchant Si, clocks, etc.) Converter Converter LDO LDO Multiphase controller Multiphase controller Power stage Power stage CPU & memory power CPU & memory power Multiphase controller Multiphase controller Power stage Power stage Converter Converter DDR termination DDR termination Sequencing & monitoring Sequencing & monitoring Logic Logic Power on reset Power on reset Sequencer Sequencer Clocking Clocking Clock generator Clock generator Clock buffer Clock buffer Fan control Fan control Hot swap controller Hot swap controller Fan controller Fan controller Temp sense Temp sense eFuse eFuse CPU CPU CPU CPU I2C expander I2C expander I2C lvel translator I2C lvel translator Voltage translator Voltage translator Buffer Buffer Retimer/redriver Retimer/redriver DDR DDR Switch fabric Switch fabric I2C vel translator I2C vel translator I2C expander I2C expander Voltage translator Voltage translator Latch Latch CPLD CPLD BMC BMC Power on reset Power on reset Logic Logic REF REF FPGA FPGA Temp sense Temp sense VMon VMon I2C mux I2C mux Switch ASIC / merchant silicon Switch ASIC / merchant silicon Retimer/redriver Retimer/redriver Memory Memory DDR DDR Flash Flash IO (JTAG, RS232, RS485) IO (JTAG, RS232, RS485) Buffer Buffer JTAG MUX JTAG MUX RS-232 RS-232 RS-485 RS-485 ESD ESD PHY PHY LDO LDO USB USB USB load switch USB load switch ESD ESD USB mux USB mux Buck + LS Buck + LS LED driver LED driver LED driver LED driver Shift register Shift register Logic Logic Downlink (optical interface) Downlink (optical interface) Optical module Optical module Optical module Optical module Optical module Optical module PHY PHY PHY PHY PHY PHY Retimer/redriver Retimer/redriver Retimer/redriver Retimer/redriver Retimer/redriver Retimer/redriver Front port controller Front port controller eFuse eFuse Uplink (optical interface) Uplink (optical interface) Optical module Optical module Retimer Retimer eFuse eFuse Switch Switch SPI MUX SPI MUX I2C mux I2C mux

Clocking

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Clock and Timing Circuitry that provides the ability to offer time and frequency synchronization. These signals can be challenging to generate and to route across the board, therefore clock buffers are used to distribute the clock signals with low skew.

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Clocks & timing (19)
Oscillators
  • LMK6C—Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVCMOS oscillator
    Data sheet: PDF | HTML
  • CDC6C—Low-power, low-jitter, bulk-acoustic-wave (BAW), fixed-frequency LVCMOS oscillator
    Data sheet: PDF | HTML
  • LMK61E2—156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator
    Data sheet: PDF | HTML
  • LMK6P—Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVPECL oscillator
    Data sheet: PDF | HTML
Clock buffers
  • LMKDB1104—4-output LP-HCSL clock buffer for PCIe Gen 1 to Gen 6
    Data sheet: PDF | HTML
  • LMK1C1102—2-channel output LVCMOS 1.8-V buffer
    Data sheet: PDF | HTML
  • LMK1C1104—4-channel output LVCMOS 1.8-V buffer
    Data sheet: PDF | HTML
  • LMK00334—4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator
    Data sheet: PDF | HTML
  • CDCLVP1102—Low jitter 1:2 universal-to-LVPECL buffer
    Data sheet: PDF | HTML
  • CDCV304—General purpose and PCI-X 1:4 LVCMOS clock buffer
    Data sheet: PDF | HTML
Clock generators
  • LMK3H0102—Bulk acoustic wave (BAW)-based PCIe Gen 1 to Gen 6-compliant referenceless clock generator
    Data sheet: PDF | HTML
  • LMK03318—Ultra-low jitter clock generator family with single PLL
    Data sheet: PDF | HTML
  • LMK03328—Ultra-low jitter clock generator family with two independent PLLs
    Data sheet: PDF | HTML
  • CDCE6214—Ultra-low power clock generator with one PLL, four differential output
    Data sheet: PDF | HTML
Real-time clocks (RTCs) & timers
  • TLC555—2.1-MHz, 250-µA, Low-Power Timer
    Data sheet: PDF | HTML
  • TLC555-Q1—Automotive LinCMOS TIMER
    Data sheet: PDF | HTML
  • LMC555—World’s smallest 555 timer with low power, high accuracy and a Fmax of 3MHz
    Data sheet: PDF | HTML
  • BQ4802LY—Y2K-Compliant Parallel RTC with CPU Supervisor and External NVSRAM Control, 3V Vcc
    Data sheet: PDF | HTML
  • SE555—Precision timer for -55 to 125C operation
    Data sheet: PDF | HTML
  • PMP21887—High-current 360-A static / 600-A peak core PMBus voltage 12-phase reference design for ASICs
    Test report: PDF Schematic: PDF

Technical documentation

View all 13
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Type Title Date
Technical article Are you ready for BAW? PDF | HTML 29 Jun 2023
Application note How to use the LMK05318 as a jitter cleaner 27 Feb 2019
Application note Glitch free power sequencing with AXC level translators (Rev. A) 20 Sep 2018
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 19 Sep 2018
Application note Optimizing Layout of the TPS54824 HotRod™ Package for Thermal Performance 16 Nov 2018
Application note Interfacing Between LVPECL, VML, CML and LVDS Levels 16 Dec 2002
Application note Supported synchronization modes for TI network synchronizers (Rev. A) 11 May 2022
Application note DC/DC Point-of-load Power Solutions for Wired Networking Switch Systems 11 May 2022
Application note Understanding clocking needs for high-speed 56G PAM-4 serial links (Rev. A) 11 May 2022
Application note Optimizing Network Switch Designs with Common Logic Use Cases (Rev. A) PDF | HTML 10 May 2022
Analog Design Journal Understanding thermal-resistance specification of DC/DC convert. w/ MOSFETs 08 Jan 2018
White paper Internally compensated advanced current mode (ACM) (Rev. A) 07 Dec 2018
Analog Design Journal Comparing internally-compensated advanced current mode (ACM) w/ D-CAP3™ control (Rev. A) 06 Nov 2018

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