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Latest version
Version: 1.7.7.6
Release date: 29 Oct 2024
TICS Pro 1.7.7.6 installer binary for Windows operating system
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Products
Clock generators
CDCE6214-Q1
—
Ultra-low power clock generator supporting PCIe gen 1-5 with 2 inputs, 4 outputs and internal EEPROM
CDCI6214
—
PCIe Gen4 support ultra-low power clock generator with four programmable outputs & EEPROM
LMK02000
—
1 to 800-MHz, precision clock distributor with integrated PLL and 3 LVDS / 5 LVPECL outputs
LMK02002
—
1 to 800-MHz, precision clock distributor with integrated PLL and 4 LVPECL outputs
LMK03200
—
Precision 0-delay clock conditioner with integrated VCO
LMK03318
—
Ultra-low jitter clock generator family with single PLL
LMK03328
—
Ultra-low jitter clock generator family with two independent PLLs
LMK03806
—
Ultra-low jitter clock generator with 14 outputs
LMK3H0102
—
Bulk acoustic wave (BAW)-based PCIe Gen 1 to Gen 6-compliant referenceless clock generator
Clock buffers
CDCDB2000
—
DB2000QL compliant 20-output clock buffer for PCIe® Gen 1 to Gen 5
CDCDB800
—
8-output clock buffer for PCIe® Gen 1 to Gen 6
LMK01000
—
1.6-GHz high performance clock buffer, divider, and distributor with 3 LVDS & 5 LVPECL outputs
LMK01010
—
1.6-GHz high performance clock buffer, divider, and distributor with 8 LVDS outputs
LMK01020
—
1.6-GHz high performance clock buffer, divider, and distributor with 8 LVPECL outputs
LMK01801
—
Dual clock distribution
LMK1D1208I
—
8-channel output, 1.8-V, 2.5-V, and 3.3-V LVDS buffer with I²C
LMKDB1104
—
4-output LP-HCSL clock buffer for PCIe Gen 1 to Gen 6
LMKDB1108
—
8-output LP-HCSL clock buffer for PCIe Gen 1 to Gen 6
LMKDB1120
—
DB2000QL-compliant 20-output clock buffer for PCIe Gen 1 to Gen 6
LMKDB1204
—
2-input 4-output LP-HCSL clock MUX for PCIe Gen 1 to Gen 6
Oscillators
LMK61E0M
—
LVCMOS ultra-low jitter programmable oscillator with internal EEPROM
LMK61E2
—
156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator
Clock jitter cleaners
LMK04100
—
Precision clock conditioners clock jitter cleaner with cascaded PLLs
LMK04101
—
Jitter cleaner with integrated 1430 to 1570-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS
LMK04102
—
Jitter cleaner with integrated 1600 to 1750-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS
LMK04110
—
Jitter cleaner with integrated 1185 to 1296-MHz VCO:5 outputs for 2VPEC/LVPEC
LMK04111
—
Jitter cleaner with integrated 1430 to 1570-MHz VCO:5 outputs for 2VPEC/LVPEC
LMK04131
—
Jitter cleaner with integrated 1430 to 1570-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS
LMK04133
—
Jitter cleaner with integrated 1840 to 2160-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS
LMK04208
—
Ultra low-noise clock jitter cleaner with 6 programmable outputs
LMK04228
—
Ultra low-noise clock jitter cleaner with dual loop PLLs
LMK04368-EP
—
Enhanced product ultra-low-noise 3.2-GHz JESD204C jitter cleaner
LMK04610
—
Ultra low-noise and low power JESD204B compliant clock jitter cleaner with dual PLLs
LMK04616
—
Ultra low-noise and low power JESD204B compliant clock jitter cleaner
LMK04714-Q1
—
Automotive, ultra low-noise 3.2-GHz, JESD204B and JESD204C dual-loop clock jitter cleaner
LMK04803
—
Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO
LMK04816
—
Three input low-noise clock jitter cleaner with dual loop PLLs
LMK04821
—
Ultra low jitter synthesizer and jitter cleaner with JESD204B support
LMK04826
—
Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0
LMK04828
—
Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.
LMK04828-EP
—
Ultra low-noise JESD204B compliant clock jitter cleaner with temperature range -55 to 105c
LMK04832
—
Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop
LMK04832-SEP
—
Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner
LMK04832-SP
—
Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner
Clock network synchronizers
LMK05028
—
Low-jitter dual-channel network synchronizer clock
LMK05318
—
Ultra-low jitter single channel network synchronizer clock with BAW
LMK05318B
—
Ultra-low jitter single channel network synchronizer clock with BAW
LMK5B12204
—
Ultra-low jitter clock generator with network synchronization and BAW technology
LMK5B33216
—
16-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO
LMK5B33414
—
14-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO
LMK5C33216
—
Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW
LMK5C33216A
—
Three DPLL, three APLL, two-input and 16-output network synchronizer with JESD204B/C and BAW VCO
RF PLLs & synthesizers
LMX1204
—
12.8-GHz RF buffer, multiplier and divider with JESD204B/C SYSREF support and phase synchronization
LMX1214
—
1:5 18GHz RF buffer and divider with auxiliary clock
LMX1860-SEP
—
Rad tolerant 15GHz RF buffer, multiplier, divider with SYSREF (JESD204B/C support) and FPGA clock
LMX1906-SP
—
Radiation-hardness-assured (RHA) 15GHz buffer, multiplier and divider with SYSREF and FPGA clock
LMX2485
—
500-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications
LMX2485E
—
50-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications
LMX2485Q-Q1
—
500MHz to 3GHz automotive delta-sigma low power dual PLL
LMX2486
—
1-GHz to 4.5-GHz delta-sigma low power dual PLL for RF personal communications
LMX2487
—
1 to 6-GHz delta-sigma low power dual PLLatinum frequency synthesizer with 3.0-GHz integer PLL
LMX2487E
—
3-GHz to 7.5-GHz delta-sigma low power dual PLL for RF personal communications
LMX2491
—
6.4-GHz low noise fractional-N PLL with ramp/chirp generation
LMX2492
—
500MHz to 14GHz wideband, low noise fractional-N PLL with ramp/chirp generation
LMX2492-Q1
—
Automotive grade 500-MHz to 14-GHz wideband, low noise fractional-N PLL with ramp/chirp generation
LMX2531
—
High performance frequency synthesizer system with integrated VCO
LMX2541
—
Ultra-low noise PLLatinum frequency synthesizer with integrated VCO
LMX2571
—
1.34-GHz, low-power, extreme-temperature RF synthesizer with frequency-shift keying (FSK) modulation
LMX2571-EP
—
Enhanced-product, 1.34-GHz, low-power, extreme-temperature RF synthesizer with FSK modulation
LMX2572
—
6.4-GHz low-power wideband RF synthesizer
LMX2572LP
—
2-GHz low power wideband RF synthesizer with FSK modulation
LMX2581
—
3.76-GHz wideband frequency synthesizer with integrated VCO
LMX2581E
—
3.8-GHz wideband frequency synthesizer with integrated VCO
LMX2582
—
5.5-GHz high performance, wideband PLLatinum RF synthesizer
LMX2592
—
9.8-GHz wideband frequency synthesizer with integrated VCO
LMX2594
—
15-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support
LMX2595
—
20-GHz wideband RF synthesizer with phase synchronization & JESD204B support
LMX2820
—
22.6-GHz wideband RF synthesizer with phase synchronization, JESD and <5-µs frequency calibration
Hardware development
Evaluation board
LMK03806BEVAL
—
LMK03806B Evaluation Board
LMK04208EVM
—
Two Input, 6+1 Output, Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO
LMK04616EVM
—
LMK04616 Evaluation Module
LMK04805BEVAL
—
Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO
LMK04806BEVAL
—
Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.5 GHz VCO
LMK04816BEVAL
—
Three Input, Thirteen Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VC
LMK04826BEVM
—
LMK04826BEVM Evaluation Module
LMK04828BEVM
—
LMK04828 evaluation module
LMK04832EVM
—
LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module
LMK04832SEPEVM
—
LMK04832-SEP evaluation module for ultra-low-noise, 3.2-GHz 15-output clock jitter clea
LMK04906BEVAL
—
Three Input, Seven Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VCO
LMK5B33216EVM
—
LMK5B33216 evaluation module for 16-output, three DPLL and APLL, network synchronizer with BAW VCO
LMX2571EPEVM
—
LMX2571-EP evaluation module for 1.34-GHz, low-power, extreme-temperature RF synthesizer
LMX2582EVM
—
LMX2582EVM High Performance, Wideband Frequency PLLatinum RF Synthesizer With Integrated VCO
LMX2592EVM
—
LMX2592EVM high-performance, wideband frequency RF synthesizer PLLATINUM™ integrated circuit
LMX2594PSEVM
—
LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization
XMICR-3P-LMX2492
—
LMX2492 X-MWblock evaluation modules
XMICR-3P-LMX2572
—
LMX2572 X-MWblock evaluation modules
XMICR-3P-LMX2592
—
LMX2592 X-MWblock evaluation modules
XMICR-3P-LMX2594
—
LMX2594 X-MWblock evaluation modules
XMICR-3P-LMX2595
—
LMX2595 X-MWblock evaluation modules
LMK04832EVM-CVAL
—
LMK04832-SP evaluation module for ultra-low-noise, dual-loop, JESD204B clock jitter cleaner
LMK04368EPEVM
—
LMK04368-EP evaluation module for JESD204B/C dual-loop clock jitter cleaner
LMK61E0MEVM
—
LMK61E0M Ultra-Low-Jitter Programmabler Oscillator Evaluation Module
LMK61E2EVM
—
LMK61E2EVM Ultra-Low-Jitter Programmable Oscillator Evaluation Module
LMX1204EVM
—
LMX1204 evaluation module for RF buffer, multiplier and divider with JESD204B/C SYSREF support
LMX2594EVM
—
LMX2594EVM 15-GHz wideband RF synthesizer with phase synchronization & JESD204B evaluation module
LMX2595EVM
—
20-GHz Wideband RF Synthesizer With Phase Synchronization and JESD204B Evaluation Module
LMX2615EVM-CVAL
—
Space grade synthesizer evaluation module
LMX2694EPEVM
—
15-GHz wideband RF synthesizer evaluation module
LMX2572EVM
—
6.4-GHz Low Power Wideband RF Synthesizer with Phase Synchronization and JESD204B Support
LMX2572LPEVM
—
2-GHz Low Power Wideband RF Synthesizer with FSK Modulation Evaluation Module
LMX2581EVM
—
LMX2581 evaluation module
LMX2820EVM
—
LMX2820 22.6-GHz wideband RF synthesizer evaluation module
LMX8410LEVM
—
I/Q demodulator evaluation module
LMK5B12212EVM
—
LMK5B12212 evaluation module
LMK5B33414EVM
—
LMK5B33414 evaluation module for 14-output, three DPLL and APLL, network synchronizer with BAW VCO
LMK5C33216AEVM
—
LMK5C33216A evaluation module
LMK5C33216EVM
—
LMK5C33216 clock synchronizer DPLL 2 input 16 outputs evaluation module
LMK5C33414AEVM
—
LMK5C33414A evaluation module
LMK05028EVM
—
LMK05028 Network Clock Generator and Synchronizer Evaluation Module
LMK05318BEVM
—
Network synchronizer clock evaluation module
CDCI6214EVM
—
CDCI6214 Ultra-Low Power Clock Generator Evaluation Module
CDCE6214-Q1EVM
—
4 differential and 1 LVCMOS outputs clock generator evaluation module
LMK3H0102EVM
—
LMK3H0102 evaluation module
TICS Pro 1.7.7.6 Release Notes
TICS Pro 1.7.7.6 Software Manifest
Added Features
LMK5Bxxyyy, LMK5Cxxyyy
- Warnings and errors improved, particularly corrective suggestions
- REFx_FREQ=0 automatically disables DPLL reference input selection for that input
- Input validation enabled and disabled by start page settings, including 1PPS
- APLL reference selection moved to Step 5, just before clock output definition
- Quick-set multiple outputs to the same settings on frequency planner
- BAW VCO allows some ppm deviation
- Force SYSREF option on OUT0/1
- Expose DPLLx_LCK_TIMER field
- Match LMK05318B EEPROM page design
- .EPR export option
- EEPROM SRAM programming generation support
- For complete changelist, see release notes
LMK3H0102
- Configuration search tool
- Wizard: voltage selection option
Bug Fixes
- LMK04832-SP, LMK04832-SEP, LMK04714-Q1, LMK04368-EP - PD_FIN0 corrected to FIN0_PD
- LMK3H0102 - Several wizard bugfixes
Known Issues
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.