The ADC12DJ3200 evaluation module (EVM) allows for the evaluation of device ADC12DJ3200. The ADC12DJ3200 is a low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO and decimation settings (including undecimated 12- and 8-bit ADC output), which features a JESD204B interface. The EVM has transformer-coupled analog inputs to accommodate a wide range of signal sources and frequencies. An LMX2582 clock synthesizer and LMK04828 JESD204B clock generator are included on the EVM and can be configured to provide an ultra-low-jitter ADC device clock and SYSREF for a complete JESD204B subclass 1 clocking solution.
ADC12DJ3200, LMX2582, and LMK04828 are controlled through an easy-to-use software GUI enabling quick configuration for a variety of uses.
The ADC12DJ3200EVM connects directly to TSW14J57EVM data capture hardware via the high-speed FMC+ connector. High-Speed Data Converter Pro Software (DATACONVERTERPRO-SW) is also available for data capture and analysis support when using the TSW14J57EVM.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | EVM User's guide | ADCxxDJxx00 Evaluation Module User's Guide (Rev. A) | 09 Jan 2018 | |
| Data sheet | ADC12DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) | PDF | HTML | 21 Feb 2019 | |
| Certificate | ADC12DJ3200EVM EU Declaration of Conformity (DoC) | 02 Jan 2019 | ||
| Technical article | Preparing for 5G applications: sync your multichannel JESD204B data acquisition sy | PDF | HTML | 28 Aug 2017 | |
| Technical article | High-speed data converter clocking for JESD204B | PDF | HTML | 07 Jul 2017 |
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