CODELOADER
CodeLoader Software for device register programming
CODELOADER
Overview
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | Loop filter & device configuration + simulation | Device register programming |
LMX24xx PLL family | EasyPLL | CodeLoader* |
LMX25xx PLL+VCO family | ||
LMK jitter cleaners and distributors |
*For new designs, use the Clocks and Synthesizers (TICS) Pro Software tool.
Downloads
Additional resources you might need
TICSPRO-SW — TICS Pro software
Supported products & hardware
Products
Clock generators
RF PLLs & synthesizers
Clock buffers
Oscillators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
TICSPRO-SW — TICS Pro software
TICS Pro 1.7.7.3 installer binary for Windows operating system
Products
Clock generators
RF PLLs & synthesizers
Clock buffers
Oscillators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
Documentation
TICS Pro 1.7.7.3 Release Notes
TICS Pro 1.7.7.3 Software Manifest
Release Information
New Devices
- Added LMX1404-EP, LMX1860-SEP, and LMKDB1204
Bug Fixes
- Stability improvements to TCP server
- Catch WMI exceptions on USB malfunction
- Warnings (a low-level class of error) now trigger a status bar update instead of just a log entry
- LMK04832 - fractions module and current calculator fixes
- CDCE6214-Q1 - frequency planner fix
- LMX2594/LMX2595 - ramp function fix
- LMX2694 - remove CE pin (invalid option on this device)
- LMK3H0102 - current calculator, PPM, and OE pin updates
- LMX1204, LMX1214, LMX1906-SP - many bugfixes
- PCIe Report Generator tool - delimiter and NaN handling fixes
Known Issues
- LMK5C33216
- When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318
- In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
What's new
- Added LMX1404-EP, LMX1860-SEP, and LMKDB1204
PLLATINUMSIM-SW — PLLatinum Sim Tool
Supported products & hardware
Products
RF PLLs & synthesizers
Clock buffers
Clock generators
IQ demodulators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
PLLATINUMSIM-SW — PLLatinum Sim Tool
Products
RF PLLs & synthesizers
Clock buffers
Clock generators
IQ demodulators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
Documentation
Release Information
Minor Bug Fix
What's new
- Fixed multi-language support fix for period and comma mix-up issue
Supported products & hardware
Clock buffers
Clock generators
Clock jitter cleaners
RF PLLs & synthesizers
Evaluation board
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | User guide | CodeLoader 4 Operating Instructions User's Guide (Rev. A) | 21 Jul 2014 | |
Technical article | A survival guide to scaling your PLL loop filter design | PDF | HTML | 22 Nov 2016 | |
Technical article | What to do when your PLL does not lock | PDF | HTML | 12 Jul 2016 |
Support & training
TI E2E™ forums with technical support from TI engineers
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