Design tool
PLLATINUMSIM-SW — PLLatinum Sim Tool
Supported products & hardware
Products
RF PLLs & synthesizers
Clock buffers
Clock generators
IQ demodulators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
PLLATINUMSIM-SW — PLLatinum Sim Tool
Products
RF PLLs & synthesizers
Clock buffers
Clock generators
IQ demodulators
Clock jitter cleaners
Clock network synchronizers
Hardware development
Evaluation board
Documentation
Release Information
Bug fixes
What's new
- Fixed Kvco calculation bug introduced in 1.6.6
- Added warning for loop bandwidth being restricted due to min high order capacitance.