SCES888C May   2018  – May 2024 2N7001T

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Up-Translation or Down-Translation from 1.65 V to 3.60 V
      2. 7.3.2 Balanced CMOS Push-Pull Outputs
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Negative Clamping Diodes
      5. 7.3.5 Partial Power Down (Ioff)
      6. 7.3.6 Over-voltage Tolerant Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Processor Error Up Translation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Discrete FET Translation Replacement
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2 Detailed Design Procedure

To begin the design process, determine the following:

  • Input voltage range
    • The supply voltage of the upstream device (device that is driving input pin A) will determine the appropriate input voltage range. For a valid logic-high, the value must exceed the high-level input voltage (VIH) of the input port. For a valid logic low the value must be less than the low-level input voltage (VIL) of the input port.
  • Output voltage range
    • The supply voltage of the downstream device (device that output pin B is driving) will determine the appropriate output voltage range.