SPRSP07F June 2017 – December 2019 66AK2G12
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
TI only supports board designs using DDR3L memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3L memory controller are shown in Table 7-1 and Figure 7-1.
NO. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tc(DDR3_CLKOUT_P/N) | Cycle time, DDR3_CLKOUT_P/N | Device Speed 60 | 2.5 | 3.3(1) | ns |
Device Speed 100 | 1.876 | 3.3(1) | ns |