SPRS866G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
      1. 1.3.1 Enhancements in KeyStone II
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. 6 C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
    7. 6.7 C66x CorePac Register Descriptions
  7. 7 ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. 8 Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. 8.2.1.1 MPU Register Map
        2. 8.2.1.2 Device-Specific MPU Registers
          1. 8.2.1.2.1 Configuration Register (CONFIG)
      2. 8.2.2 MPU Programmable Range Registers
        1. 8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
        2. 8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
        3. 8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. 8.3.2.1 CIC0 Register Map
        2. 8.3.2.2 CIC1 Register Map
        3. 8.3.2.3 CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. 10.1.2.1 Boot Device Field
        2. 10.1.2.2 Device Configuration Field
          1. 10.1.2.2.1 Sleep Boot Mode Configuration
          2. 10.1.2.2.2 I2C Boot Device Configuration
            1. 10.1.2.2.2.1 I2C Passive Mode
            2. 10.1.2.2.2.2 I2C Master Mode
          3. 10.1.2.2.3 SPI Boot Device Configuration
          4. 10.1.2.2.4 EMIF Boot Device Configuration
          5. 10.1.2.2.5 NAND Boot Device Configuration
        3. 10.1.2.3 Serial Rapid I/O Boot Device Configuration
        4. 10.1.2.4 Ethernet (SGMII) Boot Device Configuration
          1. 10.1.2.4.1 PCIe Boot Device Configuration
          2. 10.1.2.4.2 HyperLink Boot Device Configuration
          3. 10.1.2.4.3 UART Boot Device Configuration
        5. 10.1.2.5 Boot Parameter Table
          1. 10.1.2.5.1  EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3  Ethernet Boot Parameter Table
          4. 10.1.2.5.4  PCIe Boot Parameter Table
          5. 10.1.2.5.5  I2C Boot Parameter Table
          6. 10.1.2.5.6  SPI Boot Parameter Table
          7. 10.1.2.5.7  HyperLink Boot Parameter Table
          8. 10.1.2.5.8  UART Boot Parameter Table
          9. 10.1.2.5.9  NAND Boot Parameter Table
          10. 10.1.2.5.10 DDR3 Configuration Table
        6. 10.1.2.6 Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. 10.1.4.1 ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1. 10.2.3.1  Device Status (DEVSTAT) Register
        2. 10.2.3.2  Device Configuration Register
        3. 10.2.3.3  JTAG ID (JTAGID) Register Description
        4. 10.2.3.4  Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5  DSP Boot Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        7. 10.2.3.7  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        8. 10.2.3.8  Reset Status (RESET_STAT) Register
        9. 10.2.3.9  Reset Status Clear (RESET_STAT_CLR) Register
        10. 10.2.3.10 Boot Complete (BOOTCOMPLETE) Register
        11. 10.2.3.11 Power State Control (PWRSTATECTL) Register
        12. 10.2.3.12 NMI Event Generation to C66x CorePac (NMIGRx) Register
        13. 10.2.3.13 IPC Generation (IPCGRx) Registers
        14. 10.2.3.14 IPC Acknowledgment (IPCARx) Registers
        15. 10.2.3.15 IPC Generation Host (IPCGRH) Register
        16. 10.2.3.16 IPC Acknowledgment Host (IPCARH) Register
        17. 10.2.3.17 Timer Input Selection Register (TINPSEL)
        18. 10.2.3.18 Timer Output Selection Register (TOUTPSEL)
        19. 10.2.3.19 Reset Mux (RSTMUXx) Register
        20. 10.2.3.20 Device Speed (DEVSPEED) Register
        21. 10.2.3.21 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
        22. 10.2.3.22 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
        23. 10.2.3.23 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
        24. 10.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
        25. 10.2.3.25 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
        26. 10.2.3.26 System Endian Status Register (SYSENDSTAT)
        27. 10.2.3.27 SYNECLK_PINCTL Register
        28. 10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. 11.2.1.1 Core-Before-IO Power Sequencing
        2. 11.2.1.2 IO-Before-Core Power Sequencing
        3. 11.2.1.3 Prolonged Resets
        4. 11.2.1.4 Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. 11.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2 Local Clock Dividers
        3. 11.5.1.3 Module Clock Input
        4. 11.5.1.4 Main PLL Controller Operating Modes
        5. 11.5.1.5 Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. 11.5.2.1 PLL Secondary Control Register (SECCTL)
        2. 11.5.2.2 PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
        5. 11.5.2.5 SYSCLK Status Register (SYSTAT)
        6. 11.5.2.6 Reset Type Status Register (RSTYPE)
        7. 11.5.2.7 Reset Control Register (RSTCTRL)
        8. 11.5.2.8 Reset Configuration Register (RSTCFG)
        9. 11.5.2.9 Reset Isolation Register (RSISO)
      3. 11.5.3 Main PLL Control Registers
      4. 11.5.4 ARM PLL Control Registers
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
    12. 11.12 HyperLink Peripheral
    13. 11.13 UART Peripheral
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. 11.26.1.1 ARM Subsystem Features
        2. 11.26.1.2 DSP Features
      2. 11.26.2 ICEPick Module
        1. 11.26.2.1 ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. 11.27.6.1 Trace Electrical Data and Timing
      7. 11.27.7 IEEE 1149.1 JTAG
        1. 11.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2 JTAG Electrical Data and Timing
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AAW|1517
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings

over operating case temperature range (unless otherwise noted)(1)
Supply voltage(2): CVDD –0.3 V to 1.3 V
CVDD1 –0.3 V to 1.3 V
CVDDT1 –0.3 V to 1.3 V
DVDD15 –0.3 V to 1.98 V
DVDD18 –0.3 V to 2.45 V
DVDD33 –0.3V to 3.63 V
DDR3VREFSSTL 0.49 × DVDD15 to 0.51 × DVDD15
VDDAHV –0.3 V to 1.98 V
VDDALV –0.3 V to 0.935 V
VDDUSB –0.3V to 0.935 V
AVDDA1, AVDDA2, AVDDA3,AVDDA4, AVDDA5 –0.3 V to 1.98 V
AVDDA6, AVDDA7, AVDDA8, AVDDA9, AVDDA10, AVDDA11, AVDDA12, AVDDA13, AVDDA14, AVDDA15 –0.3 V to 1.98 V
VSS Ground 0 V
Input voltage (VI):(3) LVCMOS (1.8 V) –0.3 V to DVDD18+0.3 V
DDR3A, DDR3B –0.3 V to 1.98 V
I2C –0.3 V to 2.45 V
LVDS –0.3 V to DVDD18+0.3 V
LJCB –0.3 V to 1.3 V
SerDes –0.3 V to VDDAHV1+0.3 V
Output voltage (VO):(3) LVCMOS (1.8 V) –0.3 V to DVDD18+0.3 V
DDR3A, DDR3B –0.3 V to 1.98 V
I2C –0.3 V to 2.45 V
SerDes –0.3 V to VDDAHV+0.3 V
Operating case temperature, TC: Commercial 0°C to 85°C
Extended –40°C to 100°C
Overshoot/undershoot (4) LVCMOS (1.8 V) 20% overshoot/undershoot for 20% of signal duty cycle
DDR3A, DDR3B
I2C
Storage temperature, Tstg: –65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
(3) For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
(4) Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8 V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and maximum undershoot value would be VSS - 0.20 × DVDD18

5.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge (ESD) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged device model (CDM), per JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

 (1)(2)
MIN NOM MAX UNIT
CVDD SR DSP core supply Initial (3) 0.95 1.0 1.05 V
1000-MHz device SRVnom*0.95 (4) SRVnom SRVnom*1.05 V
1200-MHz device SRVnom*0.95 (4) SRVnom SRVnom*1.05 V
CVDD1 DSP core supply 0.902 0.95 0.997 V
CVDDT1 Cortex-A15 processor core supply 0.902 0.95 0.997 V
DVDD18 1.8-V supply I/O voltage 1.71 1.8 1.89 V
DVDD15 DDR3 I/O voltage DDR3 1.425 1.5 1.575 V
DDR3L at 1.5 V 1.425 1.5 1.575
DDR3L at 1.35 V 1.283 1.35 1.45
DDR3VREFSSTL DDR3A, DDR3B reference voltage 0.49 × DVDD15 0.5 × DVDD15 0.51 × DVDD15 V
VDDAHV SerDes regulator supply 1.71 1.8 1.89 V
AVDDx (5) PLL analog, DDR DLL supply 1.71 1.8 1.89 V
VDDALH SerDes termination supply 0.807 0.85 0.892 V
DVDD33 USB 3.135 3.3 3.465 V
VDDUSB USB 0.807 0.85 0.892 V
VSS Ground 0 0 0 V
VIH(6) High-level input voltage LVCMOS (1.8 V) 0.65 × DVDD18 V
I2C 0.7 × DVDD18
DDR3A, DDR3B EMIF VREFSSTL + 0.1
VIL (6) Low-level input voltage LVCMOS (1.8 V) 0.35 × DVDD18 V
DDR3A, DDR3B EMIF -0.3 VREFSSTL - 0.1
I2C 0.3 × DVDD18
TC Operating case temperature Commercial 0 85 °C
Extended –40 100
(1) All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
(2) All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
(3) Users are required to program their board CVDD supply initial value to 1.0 V on the device. The initial CVDD voltage at power-on will be 1.0 V nominal and it must transition to VID set value, immediately after being presented on the VCNTL pins. This is required to maintain full power functionality and reliability targets ensured by TI.
(4) SRVnom refers to the unique SmartReflex core supply voltage that has a potential range of 0.8 V and 1.1 V which preset from the factory for each individual device. Your device may never be programmed to operate at the upper range but has been designed accordingly should it be determined to be acceptable or necessary. Power supplies intended to support the variable SRV function shall be capable of providing a 0.8 V-1.1 V dynamic range using a 4- or 6-bit binary input value which as provided by the DSP SmartReflex output.
(5) Where x = 1,2,3,4... to indicate all supplies of the same kind.
(6) For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.

5.4 Power Consumption Summary

For information on the device power consumption, see the power estimation spreadsheet provided in 66AK2H14 Power Consumption Model, 66AK2H12 Power Consumption Model, and 66AK2H06 Power Consumption Model.

5.5 Electrical Characteristics

over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
VOH (2) High-level output voltage LVCMOS (1.8 V) IO = IOH DVDD18 – 0.45 V
DDR3A, DDR3B DVDD15 – 0.4
I2C(3)
VOL(2) Low-level output voltage LVCMOS (1.8 V) IO = IOL 0.45 V
DDR3A, DDR3B 0.4
I2C IO = 3 mA, pulled up to 1.8 V 0.4
II(4) Input current [DC] LVCMOS (1.8 V) No IPD/IPU –10 10 µA
Internal pullup 50 100 170
Internal pulldown –170 –100 –50
I2C 0.1 × DVDD18 V < VI < 0.9 × DVDD18 V –10 10
IOH High-level output current [DC] LVCMOS (1.8 V) –6 mA
DDR3A, DDR3B –8
I2C(5)
IOL Low-level output current [DC] LVCMOS (1.8 V) 6 mA
DDR3A, DDR3B 8
I2C 3
IOZ(6) Off-state output current [DC] LVCMOS (1.8 V) –10 10 µA
DDR3A, DDR3B –10 10
I2C –10 10
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) For USB High-Speed, Full-Speed, and Low-Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
(3) I2C uses open collector I/Os and does not have a VOH minimum.
(4) II applies to input-only pins and bidirectional pins. For input-only pins, II indicates the input leakage current. For bidirectional pins, II includes input leakage current and off-state (Hi-Z) output leakage current.
(5) I2C uses open collector I/Os and does not have a IOH maximum.
(6) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

5.6 Thermal Resistance Characteristics for PBGA Package [AAW]

NO. °C/W(1)(2)
1 RΘJC Junction-to-case 0.11
2 RΘJB Junction-to-board 1.65
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:
  • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
  • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) °C/W = degrees Celsius per watt.

5.7 Power Supply to Peripheral I/O Mapping

over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)(1)(2)
POWER SUPPLY I/O BUFFER TYPE ASSOCIATED PERIPHERAL
CVDD Supply core AVS voltage LJCB SYSCLK(P|N) PLL input buffer
ALTCORECLK(P|N) PLL input buffer
SRIOSGMIICLK(P|N) SerDes PLL input buffer
DDR3ACLK(P|N) PLL input buffer
DDR3BCLK(P|N) PLL input buffer
PASSCLK(P|N) PLL input buffer
ARMCLK(P|N) PLL input buffer
VDDALV LJCB SERDES low voltage
VDDAHV SerDes I/O voltage SerDes/CML PCIECLK(P|N) SerDes Clock Reference
HYP0CLK(P|N) SerDes Clock Reference
HYP1CLK(P|N) SerDes Clock Reference
USBCLK(P|M) SerDes Clock Reference
DVDD15 1.35-V / 1.5-V supply I/O voltage DDR3A, DDR3B (1.35 V / 1.5 V) All DDR3A, DDR3B memory controller peripheral I/O buffer
DVDD18 1.8-V supply I/O voltage LVCMOS (1.8 V) All GPIO peripheral I/O buffer
All JTAG and EMU peripheral I/O buffer
All TIMER peripheral I/O buffer
All SPI peripheral I/O buffer
All RESETs, NMI, control peripheral I/O buffer
All SmartReflex peripheral I/O buffer
All Hyperlink sideband peripheral I/O buffer
All MDIO peripheral I/O buffer
All UART peripheral I/O buffer
Open-drain (1.8 V) All I2C peripheral I/O buffer
(1) This table does not try to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and clock input buffers.
(2) See Hardware Design Guide for KeyStone II Devices for more information about individual peripheral I/O.