SPRS866G November   2012  – October 2017 66AK2H06 , 66AK2H12 , 66AK2H14

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
      1. 1.3.1 Enhancements in KeyStone II
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Package Terminals
    2. 4.2 Pin Map
    3. 4.3 Terminal Functions
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Power Consumption Summary
    5. 5.5 Electrical Characteristics
    6. 5.6 Thermal Resistance Characteristics for PBGA Package [AAW]
    7. 5.7 Power Supply to Peripheral I/O Mapping
  6. 6 C66x CorePac
    1. 6.1 C66x DSP CorePac
    2. 6.2 Memory Architecture
      1. 6.2.1 L1P Memory
      2. 6.2.2 L1D Memory
      3. 6.2.3 L2 Memory
      4. 6.2.4 Multicore Shared Memory SRAM
      5. 6.2.5 L3 Memory
    3. 6.3 Memory Protection
    4. 6.4 Bandwidth Management
    5. 6.5 Power-Down Control
    6. 6.6 C66x CorePac Revision
    7. 6.7 C66x CorePac Register Descriptions
  7. 7 ARM CorePac
    1. 7.1 Features
    2. 7.2 System Integration
    3. 7.3 ARM Cortex-A15 Processor
      1. 7.3.1 Overview
      2. 7.3.2 Features
      3. 7.3.3 ARM Interrupt Controller
      4. 7.3.4 Endianess
    4. 7.4 CFG Connection
    5. 7.5 Main TeraNet Connection
    6. 7.6 Clocking and Reset
      1. 7.6.1 Clocking
      2. 7.6.2 Reset
  8. 8 Memory, Interrupts, and EDMA for 66AK2Hxx
    1. 8.1 Memory Map Summary for 66AK2Hxx
    2. 8.2 Memory Protection Unit (MPU) for 66AK2Hxx
      1. 8.2.1 MPU Registers
        1. 8.2.1.1 MPU Register Map
        2. 8.2.1.2 Device-Specific MPU Registers
          1. 8.2.1.2.1 Configuration Register (CONFIG)
      2. 8.2.2 MPU Programmable Range Registers
        1. 8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
        2. 8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
        3. 8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
    3. 8.3 Interrupts for 66AK2Hxx
      1. 8.3.1 Interrupt Sources and Interrupt Controller
      2. 8.3.2 CIC Registers
        1. 8.3.2.1 CIC0 Register Map
        2. 8.3.2.2 CIC1 Register Map
        3. 8.3.2.3 CIC2 Register Map
      3. 8.3.3 Inter-Processor Register Map
      4. 8.3.4 NMI and LRESET
    4. 8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx
      1. 8.4.1 EDMA3 Device-Specific Information
      2. 8.4.2 EDMA3 Channel Controller Configuration
      3. 8.4.3 EDMA3 Transfer Controller Configuration
      4. 8.4.4 EDMA3 Channel Synchronization Events
  9. 9 System Interconnect
    1. 9.1 Internal Buses and Switch Fabrics
    2. 9.2 Switch Fabric Connections Matrix - Data Space
    3. 9.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
    4. 9.4 Bus Priorities
  10. 10Device Boot and Configuration
    1. 10.1 Device Boot
      1. 10.1.1 Boot Sequence
      2. 10.1.2 Boot Modes Supported
        1. 10.1.2.1 Boot Device Field
        2. 10.1.2.2 Device Configuration Field
          1. 10.1.2.2.1 Sleep Boot Mode Configuration
          2. 10.1.2.2.2 I2C Boot Device Configuration
            1. 10.1.2.2.2.1 I2C Passive Mode
            2. 10.1.2.2.2.2 I2C Master Mode
          3. 10.1.2.2.3 SPI Boot Device Configuration
          4. 10.1.2.2.4 EMIF Boot Device Configuration
          5. 10.1.2.2.5 NAND Boot Device Configuration
        3. 10.1.2.3 Serial Rapid I/O Boot Device Configuration
        4. 10.1.2.4 Ethernet (SGMII) Boot Device Configuration
          1. 10.1.2.4.1 PCIe Boot Device Configuration
          2. 10.1.2.4.2 HyperLink Boot Device Configuration
          3. 10.1.2.4.3 UART Boot Device Configuration
        5. 10.1.2.5 Boot Parameter Table
          1. 10.1.2.5.1  EMIF16 Boot Parameter Table
          2. 10.1.2.5.2  SRIO Boot Parameter Table
          3. 10.1.2.5.3  Ethernet Boot Parameter Table
          4. 10.1.2.5.4  PCIe Boot Parameter Table
          5. 10.1.2.5.5  I2C Boot Parameter Table
          6. 10.1.2.5.6  SPI Boot Parameter Table
          7. 10.1.2.5.7  HyperLink Boot Parameter Table
          8. 10.1.2.5.8  UART Boot Parameter Table
          9. 10.1.2.5.9  NAND Boot Parameter Table
          10. 10.1.2.5.10 DDR3 Configuration Table
        6. 10.1.2.6 Second-Level Bootloaders
      3. 10.1.3 SoC Security
      4. 10.1.4 System PLL Settings
        1. 10.1.4.1 ARM CorePac System PLL Settings
    2. 10.2 Device Configuration
      1. 10.2.1 Device Configuration at Device Reset
      2. 10.2.2 Peripheral Selection After Device Reset
      3. 10.2.3 Device State Control Registers
        1. 10.2.3.1  Device Status (DEVSTAT) Register
        2. 10.2.3.2  Device Configuration Register
        3. 10.2.3.3  JTAG ID (JTAGID) Register Description
        4. 10.2.3.4  Kicker Mechanism (KICK0 and KICK1) Register
        5. 10.2.3.5  DSP Boot Address Register (DSP_BOOT_ADDRn)
        6. 10.2.3.6  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
        7. 10.2.3.7  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
        8. 10.2.3.8  Reset Status (RESET_STAT) Register
        9. 10.2.3.9  Reset Status Clear (RESET_STAT_CLR) Register
        10. 10.2.3.10 Boot Complete (BOOTCOMPLETE) Register
        11. 10.2.3.11 Power State Control (PWRSTATECTL) Register
        12. 10.2.3.12 NMI Event Generation to C66x CorePac (NMIGRx) Register
        13. 10.2.3.13 IPC Generation (IPCGRx) Registers
        14. 10.2.3.14 IPC Acknowledgment (IPCARx) Registers
        15. 10.2.3.15 IPC Generation Host (IPCGRH) Register
        16. 10.2.3.16 IPC Acknowledgment Host (IPCARH) Register
        17. 10.2.3.17 Timer Input Selection Register (TINPSEL)
        18. 10.2.3.18 Timer Output Selection Register (TOUTPSEL)
        19. 10.2.3.19 Reset Mux (RSTMUXx) Register
        20. 10.2.3.20 Device Speed (DEVSPEED) Register
        21. 10.2.3.21 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
        22. 10.2.3.22 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
        23. 10.2.3.23 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
        24. 10.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
        25. 10.2.3.25 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
        26. 10.2.3.26 System Endian Status Register (SYSENDSTAT)
        27. 10.2.3.27 SYNECLK_PINCTL Register
        28. 10.2.3.28 USB PHY Control (USB_PHY_CTLx) Registers
  11. 1166AK2Hxx Peripheral Information
    1. 11.1  Recommended Clock and Control Signal Transition Behavior
    2. 11.2  Power Supplies
      1. 11.2.1 Power-Up Sequencing
        1. 11.2.1.1 Core-Before-IO Power Sequencing
        2. 11.2.1.2 IO-Before-Core Power Sequencing
        3. 11.2.1.3 Prolonged Resets
        4. 11.2.1.4 Clocking During Power Sequencing
      2. 11.2.2 Power-Down Sequence
      3. 11.2.3 Power Supply Decoupling and Bulk Capacitor
      4. 11.2.4 SmartReflex
    3. 11.3  Power Sleep Controller (PSC)
      1. 11.3.1 Power Domains
      2. 11.3.2 Clock Domains
      3. 11.3.3 PSC Register Memory Map
    4. 11.4  Reset Controller
      1. 11.4.1 Power-on Reset
      2. 11.4.2 Hard Reset
      3. 11.4.3 Soft Reset
      4. 11.4.4 Local Reset
      5. 11.4.5 ARM CorePac Reset
      6. 11.4.6 Reset Priority
      7. 11.4.7 Reset Controller Register
      8. 11.4.8 Reset Electrical Data and Timing
    5. 11.5  Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
      1. 11.5.1 Main PLL Controller Device-Specific Information
        1. 11.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 11.5.1.2 Local Clock Dividers
        3. 11.5.1.3 Module Clock Input
        4. 11.5.1.4 Main PLL Controller Operating Modes
        5. 11.5.1.5 Main PLL Stabilization, Lock, and Reset Times
      2. 11.5.2 PLL Controller Memory Map
        1. 11.5.2.1 PLL Secondary Control Register (SECCTL)
        2. 11.5.2.2 PLL Controller Divider Register (PLLDIV3 and PLLDIV4)
        3. 11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
        4. 11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
        5. 11.5.2.5 SYSCLK Status Register (SYSTAT)
        6. 11.5.2.6 Reset Type Status Register (RSTYPE)
        7. 11.5.2.7 Reset Control Register (RSTCTRL)
        8. 11.5.2.8 Reset Configuration Register (RSTCFG)
        9. 11.5.2.9 Reset Isolation Register (RSISO)
      3. 11.5.3 Main PLL Control Registers
      4. 11.5.4 ARM PLL Control Registers
      5. 11.5.5 Main PLL Controller, ARM, SRIO, HyperLink, PCIe, USB Clock Input Electrical Data and Timing
    6. 11.6  DDR3A PLL and DDR3B PLL
      1. 11.6.1 DDR3A PLL and DDR3B PLL Control Registers
      2. 11.6.2 DDR3A PLL and DDR3B PLL Device-Specific Information
      3. 11.6.3 DDR3 PLL Input Clock Electrical Data and Timing
    7. 11.7  PASS PLL
      1. 11.7.1 PASS PLL Local Clock Dividers
      2. 11.7.2 PASS PLL Control Registers
      3. 11.7.3 PASS PLL Device-Specific Information
      4. 11.7.4 PASS PLL Input Clock Electrical Data and Timing
    8. 11.8  External Interrupts
      1. 11.8.1 External Interrupts Electrical Data and Timing
    9. 11.9  DDR3A and DDR3B Memory Controllers
      1. 11.9.1 DDR3 Memory Controller Device-Specific Information
      2. 11.9.2 DDR3 Slew Rate Control
      3. 11.9.3 DDR3 Memory Controller Electrical Data and Timing
    10. 11.10 I2C Peripheral
      1. 11.10.1 I2C Device-Specific Information
      2. 11.10.2 I2C Peripheral Register Description
      3. 11.10.3 I2C Electrical Data and Timing
    11. 11.11 SPI Peripheral
      1. 11.11.1 SPI Electrical Data and Timing
    12. 11.12 HyperLink Peripheral
    13. 11.13 UART Peripheral
    14. 11.14 PCIe Peripheral
    15. 11.15 Packet Accelerator
    16. 11.16 Security Accelerator
    17. 11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
    18. 11.18 SGMII and XFI Management Data Input/Output (MDIO)
    19. 11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
      1. 11.19.1 10GbE Supported Features
    20. 11.20 Timers
      1. 11.20.1 Timers Device-Specific Information
      2. 11.20.2 Timers Electrical Data and Timing
    21. 11.21 Serial RapidIO (SRIO) Port
      1. 11.21.1 Serial RapidIO Device-Specific Information
    22. 11.22 General-Purpose Input/Output (GPIO)
      1. 11.22.1 GPIO Device-Specific Information
      2. 11.22.2 GPIO Peripheral Register Description
      3. 11.22.3 GPIO Electrical Data and Timing
    23. 11.23 Semaphore2
    24. 11.24 Universal Serial Bus 3.0 (USB 3.0)
    25. 11.25 EMIF16 Peripheral
      1. 11.25.1 EMIF16 Electrical Data and Timing
    26. 11.26 Emulation Features and Capability
      1. 11.26.1 Chip-Level Features
        1. 11.26.1.1 ARM Subsystem Features
        2. 11.26.1.2 DSP Features
      2. 11.26.2 ICEPick Module
        1. 11.26.2.1 ICEPick Dynamic Tap Insertion
    27. 11.27 Debug Port (EMUx)
      1. 11.27.1 Concurrent Use of Debug Port
      2. 11.27.2 Master ID for Hardware and Software Messages
      3. 11.27.3 SoC Cross-Triggering Connection
      4. 11.27.4 Peripherals-Related Debug Requirement
      5. 11.27.5 Advanced Event Triggering (AET)
      6. 11.27.6 Trace
        1. 11.27.6.1 Trace Electrical Data and Timing
      7. 11.27.7 IEEE 1149.1 JTAG
        1. 11.27.7.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 11.27.7.2 JTAG Electrical Data and Timing
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Related Links
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AAW|1517
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Memory, Interrupts, and EDMA for 66AK2Hxx

8.1 Memory Map Summary for 66AK2Hxx

Table 8-1 shows the memory map address ranges of the device.

Table 8-1 Device Memory Map Summary for 66AK2Hxx

PHYSICAL 40-BIT ADDRESS BYTES ARM VIEW DSP VIEW SOC VIEW
START END
00 0000 0000 00 0003 FFFF 256K ARM ROM Reserved ARM ROM
00 0004 0000 00 007F FFFF 8M-256K Reserved Reserved Reserved
00 0080 0000 00 008F FFFF 1M Reserved L2 SRAM L2 SRAM
00 0090 0000 00 00DF FFFF 5M Reserved Reserved Reserved
00 00E0 0000 00 00E0 7FFF 32K Reserved L1P SRAM L1P SRAM
00 00E0 8000 00 00EF FFFF 1M-32K Reserved Reserved Reserved
00 00F0 0000 00 00F0 7FFF 32K Reserved L1D SRAM L1D SRAM
00 00F0 8000 00 00FF FFFF 1M-32K Reserved Reserved Reserved
00 0100 0000 00 0100 FFFF 64K ARM AXI2VBUSM Master Registers C66x CorePac registers C66x CorePac registers
00 0101 0000 00 010F FFFF 1M-64K Reserved C66x CorePac registers C66x CorePac registers
00 0110 0000 00 0110 FFFF 64K ARM STM stimulus ports C66x CorePac registers C66x CorePac registers
00 0111 0000 00 01BF FFFF 11M-64K Reserved C66x CorePac registers C66x CorePac registers
00 01C0 0000 00 01CF FFFF 1M Reserved Reserved Reserved
00 01D0 0000 00 01D0 007F 128 Tracer_MSMC0_CFG Tracer_MSMC0_CFG Tracer_MSMC0_CFG
00 01D0 0080 00 01D0 7FFF 32K-128 Reserved Reserved Reserved
00 01D0 8000 00 01D0 807F 128 Tracer_MSMC1_CFG Tracer_MSMC1_CFG Tracer_MSMC1_CFG
00 01D0 8080 00 01D0 FFFF 32K-128 Reserved Reserved Reserved
00 01D1 0000 00 01D1 007F 128 Tracer_MSMC2_CFG Tracer_MSMC2_CFG Tracer_MSMC2_CFG
00 01D1 0080 00 01D1 7FFF 32K-128 Reserved Reserved Reserved
00 01D1 8000 00 01D1 807F 128 Tracer_MSMC3_CFG Tracer_MSMC3_CFG Tracer_MSMC3_CFG
00 01D1 8080 00 01D1 FFFF 32K-128 Reserved Reserved Reserved
00 01D2 0000 00 01D2 007F 128 Tracer_QM_M_CFG Tracer_QM_M_CFG Tracer_QM_M_CFG
00 01D2 0080 00 01D2 7FFF 32K-128 Reserved Reserved Reserved
00 01D2 8000 00 01D2 807F 128 Tracer_DDR3A_CFG Tracer_DDR3A_CFG Tracer_DDR3A_CFG
00 01D2 8080 00 01D2 FFFF 32K-128 Reserved Reserved Reserved
00 01D3 0000 00 01D3 007F 128 Tracer_SM_CFG Tracer_SM_CFG Tracer_SM_CFG
00 01D3 0080 00 01D3 7FFF 32K-128 Reserved Reserved Reserved
00 01D3 8000 00 01D3 807F 128 Tracer_QM_CFG1_CFG Tracer_QM_CFG1_CFG Tracer_QM_CFG1_CFG
00 01D3 8080 00 01D3 FFFF 32K-128 Reserved Reserved Reserved
00 01D4 0000 00 01D4 007F 128 Tracer_CFG_CFG Tracer_CFG_CFG Tracer_CFG_CFG
00 01D4 0080 00 01D4 7FFF 32K-128 Reserved Reserved Reserved
00 01D4 8000 00 01D4 807F 128 Tracer_L2_0_CFG Tracer_L2_0_CFG Tracer_L2_0_CFG
00 01D4 8080 00 01D4 FFFF 32K-128 Reserved Reserved Reserved
00 01D5 0000 00 01D5 007F 128 Tracer_L2_1_CFG Tracer_L2_1_CFG Tracer_L2_1_CFG
00 01D5 0080 00 01D5 7FFF 32K-128 Reserved Reserved Reserved
00 01D5 8000 00 01D5 807F 128 Tracer_L2_2_CFG Tracer_L2_2_CFG Tracer_L2_2_CFG
00 01D5 8080 00 01D5 FFFF 32K-128 Reserved Reserved Reserved
00 01D6 0000 00 01D6 007F 128 Tracer_L2_3_CFG Tracer_L2_3_CFG Tracer_L2_3_CFG
00 01D6 0080 00 01D6 7FFF 32K-128 Reserved Reserved Reserved
00 01D6 8000 00 01D6 807F 128 Tracer_L2_4_CFG Tracer_L2_4_CFG Tracer_L2_4_CFG
00 01D6 8080 00 01D6 FFFF 32K-128 Reserved Reserved Reserved
00 01D7 0000 00 01D7 007F 128 Tracer_L2_5_CFG Tracer_L2_5_CFG Tracer_L2_5_CFG
00 01D7 0080 00 01D7 7FFF 32K-128 Reserved Reserved Reserved
00 01D7 8000 00 01D7 807F 128 Tracer_L2_6_CFG Tracer_L2_6_CFG Tracer_L2_6_CFG
00 01D7 8080 00 01D7 FFFF 32K-128 Reserved Reserved Reserved
00 01D8 0000 00 01D8 007F 128 Tracer_L2_7_CFG Tracer_L2_7_CFG Tracer_L2_7_CFG
00 01D8 0080 00 01D8 7FFF 32K-128 Reserved Reserved Reserved
00 01D8 8000 00 01D8 807F 128 Reserved Reserved Reserved
00 01D8 8080 00 01D8 8FFF 32K-128 Reserved Reserved Reserved
00 01D9 0000 00 01D9 007F 128 Reserved Reserved Reserved
00 01D9 0080 00 01D9 7FFF 32K-128 Reserved Reserved Reserved
00 01D9 8000 00 01D9 807F 128 Reserved Reserved Reserved
00 01D9 8080 00 01D9 FFFF 32K-128 Reserved Reserved Reserved
00 01DA 0000 00 01DA 007F 128 Tracer_QM_CFG2_CFG Tracer_QM_CFG2_CFG Tracer_QM_CFG2_CFG
00 01DA 0080 00 01DA 7FFF 32K-128 Reserved Reserved Reserved
00 01DA 8000 00 01DA 807F 128 Reserved Reserved Reserved
00 01DA 8080 00 01DA FFFF 32K-128 Reserved Reserved Reserved
00 01DB 0000 00 01DB 007F 128 Tracer_DDR3B_CFG Tracer_DDR3B_CFG Tracer_DDR3B_CFG
00 01DB 0080 00 01DB 7FFF 32K-128 Reserved Reserved Reserved
00 01DB 8000 00 01DB 807F 128 Reserved Reserved Reserved
00 01DB 8080 00 01DB 8FFF 32K-128 Reserved Reserved Reserved
00 01DC 0000 00 01DC 007F 128 Tracer_TPCC0_4_CFG Tracer_TPCC0_4_CFG Tracer_TPCC0_4_CFG
00 01DC 0080 00 01DC 7FFF 32K-128 Reserved Reserved Reserved
00 01DC 8000 00 01DC 807F 128 Tracer_TPCC1_2_3_CFG Tracer_TPCC1_2_3_CFG Tracer_TPCC1_2_3_CFG
00 01DC 8080 00 01DC FFFF 32K-128 Reserved Reserved Reserved
00 01DD 0000 00 01DD 007F 128 Tracer_INTC_CFG Tracer_INTC_CFG Tracer_INTC_CFG
00 01DD 0080 00 01DD 7FFF 32K-128 Reserved Reserved Reserved
00 01DD 8000 00 01DD 807F 128 Tracer_MSMC4_CFG Tracer_MSMC4_CFG Tracer_MSMC4_CFG
00 01DD 8080 00 01DD FFFF 32K-128 Reserved Reserved Reserved
00 01DE 0000 00 01DE 007F 128 Tracer_MSMC5_CFG Tracer_MSMC5_CFG Tracer_MSMC5_CFG
00 01DE 0000 00 01DE 007F 128 Tracer_MSMC6_CFG Tracer_MSMC6_CFG Tracer_MSMC6_CFG
00 01DE 0000 00 01DE 007F 128 Tracer_MSMC7_CFG Tracer_MSMC7_CFG Tracer_MSMC7_CFG
00 01DE 0080 00 01DE 7FFF 32K-384 Reserved Reserved Reserved
00 01DE 8000 00 01DE 807F 128 Tracer_SPI_ROM_EMIF16_CFG Tracer_SPI_ROM_EMIF16_CFG Tracer_SPI_ROM_EMIF16_CFG
00 01DE 8080 00 01DF FFFF 64K-128 Reserved Reserved Reserved
00 01E0 0000 00 01E3 FFFF 256K Reserved Reserved Reserved
00 01E4 0000 00 01E4 3FFF 16K Reserved Reserved Reserved
00 01E4 4000 00 01E7 FFFF 240k Reserved Reserved Reserved
00 01E8 0000 00 01E8 3FFF 16K ARM CorePac VBUSP Memory Mapped Registers ARM CorePac VBUSP Memory Mapped Registers ARM CorePac VBUSP Memory Mapped Registers
00 01E8 4000 00 01EB FFFF 240k Reserved Reserved Reserved
00 01EC 0000 00 01EF FFFF 256K Reserved Reserved Reserved
00 01F0 0000 00 01F7 FFFF 512K Reserved Reserved Reserved
00 01F8 0000 00 01F8 FFFF 64K Reserved Reserved Reserved
00 01F9 0000 00 01F9 FFFF 64K Reserved Reserved Reserved
00 01FA 0000 00 01FB FFFF 128K Reserved Reserved Reserved
00 01FC 0000 00 01FD FFFF 128K Reserved Reserved Reserved
00 01FE 0000 00 01FF FFFF 128K Reserved Reserved Reserved
00 0200 0000 00 020F FFFF 1M Network Coprocessor (Packet Accelerator, 1-gigabit Ethernet switch subsystem and Security Accelerator) Network Coprocessor (Packet Accelerator, 1-gigabit Ethernet switch subsystem and Security Accelerator) Network Coprocessor (Packet Accelerator, 1-gigabit Ethernet switch subsystem and Security Accelerator)
00 0210 0000 00 0210 FFFF 64K Reserved Reserved Reserved
00 0211 0000 00 0211 FFFF 64K Reserved Reserved Reserved
00 0212 0000 00 0213 FFFF 128K Reserved Reserved Reserved
00 0214 0000 00 0215 FFFF 128K Reserved Reserved Reserved
00 0216 0000 00 0217 FFFF 128K Reserved Reserved Reserved
00 0218 0000 00 0218 7FFF 32k Reserved Reserved Reserved
00 0218 8000 00 0218 FFFF 32k Reserved Reserved Reserved
00 0219 0000 00 0219 FFFF 64k Reserved Reserved Reserved
00 021A 0000 00 021A FFFF 64K Reserved Reserved Reserved
00 021B 0000 00 021B FFFF 64K Reserved Reserved Reserved
00 021C 0000 00 021C 03FF 1K Reserved Reserved Reserved
00 021C 0400 00 021C 3FFF 15K Reserved Reserved Reserved
00 021C 4000 00 021C 43FF 1K Reserved Reserved Reserved
00 021C 4400 00 021C 5FFF 7K Reserved Reserved Reserved
00 021C 6000 00 021C 63FF 1K Reserved Reserved Reserved
00 021C 6400 00 021C 7FFF 7K Reserved Reserved Reserved
00 021C 8000 00 021C 83FF 1K Reserved Reserved Reserved
00 021C 8400 00 021C FFFF 31K Reserved Reserved Reserved
00 021D 0000 00 021D 00FF 256 Reserved Reserved Reserved
00 021D 0100 00 021D 3FFF 16K Reserved Reserved Reserved
00 021D 4000 00 021D 40FF 256 Reserved Reserved Reserved
00 021D 4100 00 021D 7FFF 16K Reserved Reserved Reserved
00 021D 8000 00 021D 80FF 256 Reserved Reserved Reserved
00 021D 8100 00 021D BFFF 16K Reserved Reserved Reserved
00 021D C000 00 021D C0FF 256 Reserved Reserved Reserved
00 021D C100 00 021D EFFF 12K-256 Reserved Reserved Reserved
00 021D F000 00 021D F07F 128 Reserved Reserved Reserved
00 021D F080 00 021D FFFF 4K-128 Reserved Reserved Reserved
00 021E 0000 00 021E FFFF 64K Reserved Reserved Reserved
00 021F 0000 00 021F 07FF 2K Reserved Reserved Reserved
00 021F 0800 00 021F 0FFF 2K Reserved Reserved Reserved
00 021F 1000 00 021F 17FF 2K Reserved Reserved Reserved
00 021F 1800 00 021F 3FFF 10K Reserved Reserved Reserved
00 021F 4000 00 021F 47FF 2K Reserved Reserved Reserved
00 021F 4800 00 021F 7FFF 14K Reserved Reserved Reserved
00 021F 8000 00 021F 87FF 2K Reserved Reserved Reserved
00 021F 8800 00 021F BFFF 14K Reserved Reserved Reserved
00 021F C000 00 021F C7FF 2K Reserved Reserved Reserved
00 021F C800 00 021F FFFF 14K Reserved Reserved Reserved
00 0220 0000 00 0220 007F 128 Timer0 Timer0 Timer0
00 0220 0080 00 0220 FFFF 64K-128 Reserved Reserved Reserved
00 0221 0000 00 0221 007F 128 Timer1 Timer1 Timer1
00 0221 0080 00 0221 FFFF 64K-128 Reserved Reserved Reserved
00 0222 0000 00 0222 007F 128 Timer2 Timer2 Timer2
00 0222 0080 00 0222 FFFF 64K-128 Reserved Reserved Reserved
00 0223 0000 00 0223 007F 128 Timer3 Timer3 Timer3
00 0223 0080 00 0223 FFFF 64K-128 Reserved Reserved Reserved
00 0224 0000 00 0224 007F 128 Timer4(1) Timer4(1) Timer4(1)
00 0224 0080 00 0224 FFFF 64K-128 Reserved Reserved Reserved
00 0225 0000 00 0225 007F 128 Timer5(1) Timer5(1) Timer5(1)
00 0225 0080 00 0225 FFFF 64K-128 Reserved Reserved Reserved
00 0226 0000 00 0226 007F 128 Timer6(1) Timer6(1) Timer6(1)
00 0226 0080 00 0226 FFFF 64K-128 Reserved Reserved Reserved
00 0227 0000 00 0227 007F 128 Timer7(1) Timer7(1) Timer7(1)
00 0227 0080 00 0227 FFFF 64K-128 Reserved Reserved Reserved
00 0228 0000 00 0228 007F 128 Timer 8 Timer 8 Timer 8
00 0228 0080 00 0228 FFFF 64K-128 Reserved Reserved Reserved
00 0229 0000 00 0229 007F 128 Timer 9 Timer 9 Timer 9
00 0229 0080 00 0229 FFFF 64K-128 Reserved Reserved Reserved
00 022A 0000 00 022A 007F 128 Timer 10 Timer 10 Timer 10
00 022A 0080 00 022A FFFF 64K-128 Reserved Reserved Reserved
00 022B 0000 00 022B 007F 128 Timer 11 Timer 11 Timer 11
00 022B 0080 00 022B FFFF 64K-128 Reserved Reserved Reserved
00 022C 0000 00 022C 007F 128 Timer 12 Timer 12 Timer 12
00 022C 0080 00 022C FFFF 64K-128 Reserved Reserved Reserved
00 022D 0000 00 022D 007F 128 Timer 13 Timer 13 Timer 13
00 022D 0080 00 022D FFFF 64K-128 Reserved Reserved Reserved
00 022E 0000 00 022E 007F 128 Timer 14 Timer 14 Timer 14
00 022E 0080 00 022E FFFF 64K-128 Reserved Reserved Reserved
00 022F 0000 00 022F 007F 128 Timer 15 Timer 15 Timer 15
00 022F 0080 00 022F 00FF 128 Timer 16 Timer 16 Timer 16
00 022F 0100 00 022F 017F 128 Timer 17 Timer 17 Timer 17
00 022F 0180 00 022F 01FF 128 Timer 18(1) Timer 18(1) Timer 18(1)
00 022F 0200 00 022F 027F 128 Timer 19(1) Timer 19(1) Timer 19(1)
00 0230 0000 00 0230 FFFF 64K Reserved Reserved Reserved
00 0231 0000 00 0231 01FF 512 PLL Controller PLL Controller PLL Controller
00 0231 0200 00 0231 9FFF 40K-512 Reserved Reserved Reserved
00 0231 A000 00 0231 BFFF 8K HyperLink0 SerDes Config HyperLink0 SerDes Config HyperLink0 SerDes Config
00 0231 C000 00 0231 DFFF 8K HyperLink1 SerDes Config HyperLink1 SerDes Config HyperLink1 SerDes Config
00 0231 E000 00 0231 FFFF 8K 10GbE SerDes Config (66AK2H14 only) 10GbE SerDes Config (66AK2H14 only) 10GbE SerDes Config (66AK2H14 only)
00 0232 0000 00 0232 3FFF 16K PCIE SerDes Config PCIE SerDes Config PCIE SerDes Config
00 0232 4000 00 0232 5FFF 8K Reserved Reserved Reserved
00 0232 6000 00 0232 7FFF 8K Reserved Reserved Reserved
00 0232 8000 00 0232 8FFF 4K DDRB PHY Config DDRB PHY Config DDRB PHY Config
00 0232 9000 00 0232 9FFF 4K DDRA PHY Config DDRA PHY Config DDRA PHY Config
00 0232 A000 00 0232 BFFF 8K PA SerDes Config PA SerDes Config PA SerDes Config
00 0232 C000 00 0232 DFFF 8K SRIO SerDes Config SRIO SerDes Config SRIO SerDes Config
00 0232 E000 00 0232 EFFF 4K Reserved Reserved Reserved
00 0232 F000 00 0232 FFFF 4K Reserved Reserved Reserved
00 0233 0000 00 0233 03FF 1K SmartReflex0 SmartReflex0 SmartReflex0
00 0233 0400 00 0233 07FF 1K SmartReflex1 SmartReflex1 SmartReflex1
00 0233 0400 00 0233 FFFF 62K Reserved Reserved Reserved
00 0234 0000 00 0234 00FF 256 Reserved Reserved Reserved
00 0234 0100 00 0234 3FFF 16K Reserved Reserved Reserved
00 0234 4000 00 0234 40FF 256 Reserved Reserved Reserved
00 0234 4100 00 0234 7FFF 16K Reserved Reserved Reserved
00 0234 8000 00 0234 80FF 256 Reserved Reserved Reserved
00 0234 8100 00 0234 BFFF 16K Reserved Reserved Reserved
00 0234 C000 00 0234 C0FF 256 Reserved Reserved Reserved
00 0234 C100 00 0234 FFFF 16K Reserved Reserved Reserved
00 0235 0000 00 0235 0FFF 4K Power sleep controller (PSC) Power sleep controller (PSC) Power sleep controller (PSC)
00 0235 1000 00 0235 FFFF 64K-4K Reserved Reserved Reserved
00 0236 0000 00 0236 03FF 1K Memory protection unit (MPU) 0 Memory protection unit (MPU) 0 Memory protection unit (MPU) 0
00 0236 0400 00 0236 7FFF 31K Reserved Reserved Reserved
00 0236 8000 00 0236 83FF 1K Memory protection unit (MPU) 1 Memory protection unit (MPU) 1 Memory protection unit (MPU) 1
00 0236 8400 00 0236 FFFF 31K Reserved Reserved Reserved
00 0237 0000 00 0237 03FF 1K Memory protection unit (MPU) 2 Memory protection unit (MPU) 2 Memory protection unit (MPU) 2
00 0237 0400 00 0237 7FFF 31K Reserved Reserved Reserved
00 0237 8000 00 0237 83FF 1K Memory protection unit (MPU) 3 Memory protection unit (MPU) 3 Memory protection unit (MPU) 3
00 0237 8400 00 0237 FFFF 31K Reserved Reserved Reserved
00 0238 0000 00 0238 03FF 1K Memory protection unit (MPU) 4 Memory protection unit (MPU) 4 Memory protection unit (MPU) 4
00 0238 8000 00 0238 83FF 1K Memory protection unit (MPU) 5 Memory protection unit (MPU) 5 Memory protection unit (MPU) 5
00 0238 8400 00 0238 87FF 1K Memory protection unit (MPU) 6 Memory protection unit (MPU) 6 Memory protection unit (MPU) 6
00 0238 8800 00 0238 8BFF 1K Memory protection unit (MPU) 7 Memory protection unit (MPU) 7 Memory protection unit (MPU) 7
00 0238 8C00 00 0238 8FFF 1K Memory protection unit (MPU) 8 Memory protection unit (MPU) 8 Memory protection unit (MPU) 8
00 0238 9000 00 0238 93FF 1K Memory protection unit (MPU) 9 Memory protection unit (MPU) 9 Memory protection unit (MPU) 9
00 0238 9400 00 0238 97FF 1K Memory protection unit (MPU) 10 Memory protection unit (MPU) 10 Memory protection unit (MPU) 10
00 0238 9800 00 0238 9BFF 1K Memory protection unit (MPU) 11 Memory protection unit (MPU) 11 Memory protection unit (MPU) 11
00 0238 9C00 00 0238 9FFF 1K Memory protection unit (MPU) 12 Memory protection unit (MPU) 12 Memory protection unit (MPU) 12
00 0238 A000 00 0238 A3FF 1K Memory protection unit (MPU) 13 Memory protection unit (MPU) 13 Memory protection unit (MPU) 13
00 0238 A400 00 0238 A7FF 1K Memory protection unit (MPU) 14 Memory protection unit (MPU) 14 Memory protection unit (MPU) 14
00 0238 A800 00 023F FFFF 471K Reserved Reserved Reserved
00 0240 0000 00 0243 FFFF 256K Reserved Reserved Reserved
00 0244 0000 00 0244 3FFF 16K DSP trace formatter 0 DSP trace formatter 0 DSP trace formatter 0
00 0244 4000 00 0244 FFFF 48K Reserved Reserved Reserved
00 0245 0000 00 0245 3FFF 16K DSP trace formatter 1 DSP trace formatter 1 DSP trace formatter 1
00 0245 4000 00 0245 FFFF 48K Reserved Reserved Reserved
00 0246 0000 00 0246 3FFF 16K DSP trace formatter 2 DSP trace formatter 2 DSP trace formatter 2
00 0246 4000 00 0246 FFFF 48K Reserved Reserved Reserved
00 0247 0000 00 0247 3FFF 16K DSP trace formatter 3 DSP trace formatter 3 DSP trace formatter 3
00 0247 4000 00 0247 FFFF 48K Reserved Reserved Reserved
00 0248 0000 00 0248 3FFF 16K DSP trace formatter 4 DSP trace formatter 4 DSP trace formatter 4
00 0248 4000 00 0248 FFFF 48K Reserved Reserved Reserved
00 0249 0000 00 0249 3FFF 16K DSP trace formatter 5 DSP trace formatter 5 DSP trace formatter 5
00 0249 4000 00 0249 FFFF 48K Reserved Reserved Reserved
00 024A 0000 00 024A 3FFF 16K DSP trace formatter 6 DSP trace formatter 6 DSP trace formatter 6
00 024A 4000 00 024A FFFF 48K Reserved Reserved Reserved
00 024B 0000 00 024B 3FFF 16K DSP trace formatter 7 DSP trace formatter 7 DSP trace formatter 7
00 024B 4000 00 024B FFFF 48K Reserved Reserved Reserved
00 024C 0000 00 024C 01FF 512 Reserved Reserved Reserved
00 024C 0200 00 024C 03FF 1K-512 Reserved Reserved Reserved
00 024C 0400 00 024C 07FF 1K Reserved Reserved Reserved
00 024C 0800 00 024C FFFF 62K Reserved Reserved Reserved
00 024D 0000 00 024F FFFF 192K Reserved Reserved Reserved
00 0250 0000 00 0250 007F 128 Reserved Reserved Reserved
00 0250 0080 00 0250 7FFF 32K-128 Reserved Reserved Reserved
00 0250 8000 00 0250 FFFF 32K Reserved Reserved Reserved
00 0251 0000 00 0251 FFFF 64K Reserved Reserved Reserved
00 0252 0000 00 0252 03FF 1K Reserved Reserved Reserved
00 0252 0400 00 0252 FFFF 64K-1K Reserved Reserved Reserved
00 0253 0000 00 0253 007F 128 I2C0 I2C0 I2C0
00 0253 0080 00 0253 03FF 1K-128 Reserved Reserved Reserved
00 0253 0400 00 0253 047F 128 I2C1 I2C1 I2C1
00 0253 0480 00 0253 07FF 1K-128 Reserved Reserved Reserved
00 0253 0800 00 0253 087F 128 I2C2 I2C2 I2C2
00 0253 0880 00 0253 0BFF 1K-128 Reserved Reserved Reserved
00 0253 0C00 00 0253 0C3F 64 UART0 UART0 UART0
00 0253 0C40 00 0253 FFFF 1K-64 Reserved Reserved Reserved
00 0253 1000 00 0253 103F 64 UART1 UART1 UART1
00 0253 1040 00 0253 FFFF 60K-64 Reserved Reserved Reserved
00 0254 0000 00 0255 FFFF 128K Reserved Reserved Reserved
00 0256 0000 00 0257 FFFF 128K ARM CorePac INTC (GIC400) Memory Mapped Registers ARM CorePac INTC (GIC400) Memory Mapped Registers ARM CorePac INTC (GIC400) Memory Mapped Registers
00 0258 0000 00 025F FFFF 512K Reserved Reserved Reserved
00 0260 0000 00 0260 1FFF 8K Secondary interrupt controller (INTC) 0 Secondary interrupt controller (INTC) 0 Secondary interrupt controller (INTC) 0
00 0260 2000 00 0260 3FFF 8K Reserved Reserved Reserved
00 0260 4000 00 0260 5FFF 8K Secondary interrupt controller (INTC) 1 Secondary interrupt controller (INTC) 1 Secondary interrupt controller (INTC) 1
00 0260 6000 00 0260 7FFF 8K Reserved Reserved Reserved
00 0260 8000 00 0260 9FFF 8K Secondary interrupt controller (INTC) 2 Secondary interrupt controller (INTC) 2 Secondary interrupt controller (INTC) 2
00 0260 A000 00 0260 BEFF 8K-256 Reserved Reserved Reserved
00 0260 BF00 00 0260 BFFF 256 GPIO Config GPIO Config GPIO Config
00 0260 C000 00 0261 BFFF 64K Reserved Reserved Reserved
00 0261 C000 00 0261 FFFF 16K Reserved Reserved Reserved
00 0262 0000 00 0262 0FFF 4K BOOTCFG chip-level registers BOOTCFG chip-level registers BOOTCFG chip-level registers
00 0262 1000 00 0262 FFFF 60K Reserved Reserved Reserved
00 0263 0000 00 0263 FFFF 64K USB PHY Config USB PHY Config USB PHY Config
00 0264 0000 00 0264 07FF 2K Semaphore Config Semaphore Config Semaphore Config
00 0264 0800 00 0264 FFFF 62K Reserved Reserved Reserved
00 0265 0000 00 0267 FFFF 192K Reserved Reserved Reserved
00 0268 0000 00 0268 FFFF 512K USB MMR Config USB MMR Config USB MMR Config
00 0270 0000 00 0270 7FFF 32K EDMA channel controller (TPCC) 0 EDMA channel controller (TPCC) 0 EDMA channel controller (TPCC) 0
00 0270 8000 00 0270 FFFF 32K EDMA channel controller (TPCC) 4 EDMA channel controller (TPCC) 4 EDMA channel controller (TPCC) 4
00 0271 0000 00 0271 FFFF 64K Reserved Reserved Reserved
00 0272 0000 00 0272 7FFF 32K EDMA channel controller (TPCC) 1 EDMA channel controller (TPCC) 1 EDMA channel controller (TPCC) 1
00 0272 8000 00 0272 FFFF 32K EDMA channel controller (TPCC) 3 EDMA channel controller (TPCC) 3 EDMA channel controller (TPCC) 3
00 0273 0000 00 0273 FFFF 64K Reserved Reserved Reserved
00 0274 0000 00 0274 7FFF 32K EDMA channel controller (TPCC) 2 EDMA channel controller (TPCC) 2 EDMA channel controller (TPCC) 2
00 0274 8000 00 0275 FFFF 96K Reserved Reserved Reserved
00 0276 0000 00 0276 03FF 1K EDMA TPCC0 transfer controller (TPTC) 0 EDMA TPCC0 transfer controller (TPTC) 0 EDMA TPCC0 transfer controller (TPTC) 0
00 0276 0400 00 0276 7FFF 31K Reserved Reserved Reserved
00 0276 8000 00 0276 83FF 1K EDMA TPCC0 transfer controller (TPTC) 1 EDMA TPCC0 transfer controller (TPTC) 1 EDMA TPCC0 transfer controller (TPTC) 1
00 0276 8400 00 0276 FFFF 31K Reserved Reserved Reserved
00 0277 0000 00 0277 03FF 1K EDMA TPCC1 transfer controller (TPTC) 0 EDMA TPCC1 transfer controller (TPTC) 0 EDMA TPCC1 transfer controller (TPTC) 0
00 0277 0400 00 0277 7FFF 31K Reserved Reserved Reserved
00 0277 8000 00 0277 83FF 1K EDMA TPCC1 transfer controller (TPTC) 1 EDMA TPCC1 transfer controller (TPTC) 1 EDMA TPCC1 transfer controller (TPTC) 1
00 0278 0400 00 0277 FFFF 31K Reserved Reserved Reserved
00 0278 0000 00 0278 03FF 1K EDMA TPCC1 transfer controller (TPTC) 2 EDMA TPCC1 transfer controller (TPTC) 2 EDMA TPCC1 transfer controller (TPTC) 2
00 0278 0400 00 0278 7FFF 31K Reserved Reserved Reserved
00 0278 8000 00 0278 83FF 1K EDMA TPCC1 transfer controller (TPTC) 3 EDMA TPCC1 transfer controller (TPTC) 3 EDMA TPCC1 transfer controller (TPTC) 3
00 0278 8400 00 0278 FFFF 31K Reserved Reserved Reserved
00 0279 0000 00 0279 03FF 1K EDMA TPCC2 transfer controller (TPTC) 0 EDMA TPCC2 transfer controller (TPTC) 0 EDMA TPCC2 transfer controller (TPTC) 0
00 0279 0400 00 0279 7FFF 31K Reserved Reserved Reserved
00 0279 8000 00 0279 83FF 1K EDMA TPCC2 transfer controller (TPTC) 1 EDMA TPCC2 transfer controller (TPTC) 1 EDMA TPCC2 transfer controller (TPTC) 1
00 0279 8400 00 0279 FFFF 31K Reserved Reserved Reserved
00 027A 0000 00 027A 03FF 1K EDMA TPCC2 transfer controller (TPTC) 2 EDMA TPCC2 transfer controller (TPTC) 2 EDMA TPCC2 transfer controller (TPTC) 2
00 027A 0400 00 027A 7FFF 31K Reserved Reserved Reserved
00 027A 8000 00 027A 83FF 1K EDMA TPCC2 transfer controller (TPTC) 3 EDMA TPCC2 transfer controller (TPTC) 3 EDMA TPCC2 transfer controller (TPTC) 3
00 027A 8400 00 027A FFFF 31K Reserved Reserved Reserved
00 027B 0000 00 027B 03FF 1K EDMA TPCC3 transfer controller (TPTC) 0 EDMA TPCC3 transfer controller (TPTC) 0 EDMA TPCC3 transfer controller (TPTC) 0
00 027B 0400 00 027B 7FFF 31K Reserved Reserved Reserved
00 027B 8000 00 027B 83FF 1K EDMA TPCC3 transfer controller (TPTC) 1 EDMA TPCC3 transfer controller (TPTC) 1 EDMA TPCC3 transfer controller (TPTC) 1
00 027B 8400 00 027B 87FF 1K EDMA TPCC4 transfer controller (TPTC) 0 EDMA TPCC4 transfer controller (TPTC) 0 EDMA TPCC4 transfer controller (TPTC) 0
00 027B 8800 00 027B 8BFF 1K EEDMA TPCC4 transfer controller (TPTC) 1 EEDMA TPCC4 transfer controller (TPTC) 1 EEDMA TPCC4 transfer controller (TPTC) 1
00 027B 8C00 00 027B FFFF 29K Reserved Reserved Reserved
00 027C 0000 00 027C 03FF 1K Reserved Reserved Reserved
00 027C 0400 00 027C FFFF 63K Reserved Reserved Reserved
00 027D 0000 00 027D 3FFF 16K TI embedded trace buffer (TETB) - CorePac0 TI embedded trace buffer (TETB) - CorePac0 TI embedded trace buffer (TETB) - CorePac0
00 027D 4000 00 027D 7FFF 16K TBR_SYS_ARM CorePac - Trace buffer - ARM CorePac TBR_SYS_ARM CorePac - Trace buffer - ARM CorePac TBR_SYS_ARM CorePac - Trace buffer - ARM CorePac
00 027D 8000 00 027D FFFF 32K Reserved Reserved Reserved
00 027E 0000 00 027E 3FFF 16K TI embedded trace buffer (TETB) - CorePac1 TI embedded trace buffer (TETB) - CorePac1 TI embedded trace buffer (TETB) - CorePac1
00 027E 4000 00 027E FFFF 48K Reserved Reserved Reserved
00 027F 0000 00 027F 3FFF 16K TI embedded trace buffer (TETB) - CorePac2 TI embedded trace buffer (TETB) - CorePac2 TI embedded trace buffer (TETB) - CorePac2
00 027F 4000 00 027F FFFF 48K Reserved Reserved Reserved
00 0280 0000 00 0280 3FFF 16K TI embedded trace buffer (TETB) - CorePac3 TI embedded trace buffer (TETB) - CorePac3 TI embedded trace buffer (TETB) - CorePac3
00 0280 4000 00 0280 FFFF 48K Reserved Reserved Reserved
00 0281 0000 00 0281 3FFF 16K TI embedded trace buffer (TETB) - CorePac4 (66AK2H12/14 only) TI embedded trace buffer (TETB) - CorePac4 (66AK2H12/14 only) TI embedded trace buffer (TETB) - CorePac4 (66AK2H12/14 only)
00 0281 4000 00 0281 FFFF 48K Reserved Reserved Reserved
00 0282 0000 00 0282 3FFF 16K TI embedded trace buffer (TETB) - CorePac5 (66AK2H12/14 only) TI embedded trace buffer (TETB) - CorePac5 (66AK2H12/14 only) TI embedded trace buffer (TETB) - CorePac5 (66AK2H12/14 only)
00 0282 4000 00 0282 FFFF 48K Reserved Reserved Reserved
00 0283 0000 00 0283 3FFF 16K TI embedded trace buffer (TETB) - CorePac6 (66AK2H12/14 only) TI embedded trace buffer (TETB) - CorePac6 (66AK2H12/14 only) TI embedded trace buffer (TETB) - CorePac6 (66AK2H12/14 only)
00 0283 4000 00 0283 FFFF 48K Reserved Reserved Reserved
00 0284 0000 00 0284 3FFF 16K TI embedded trace buffer (TETB) - CorePac7 (66AK2H12/14 only) TI embedded trace buffer (TETB) - CorePac7 (66AK2H12/14 only) TI embedded trace buffer (TETB) - CorePac7 (66AK2H12/14 only)
00 0284 4000 00 0284 FFFF 48K Reserved Reserved Reserved
00 0285 0000 00 0285 7FFF 32K TI embedded trace buffer (TETB) - system TI embedded trace buffer (TETB) - system TI embedded trace buffer (TETB) - system
00 0285 8000 00 0285 FFFF 32K Reserved Reserved Reserved
00 0286 0000 00 028F FFFF 640K Reserved Reserved Reserved
00 0290 0000 00 0293 FFFF 256K Serial RapidIO configuration (SRIO) Serial RapidIO configuration (SRIO) Serial RapidIO configuration (SRIO)
00 0294 0000 00 029F FFFF 768K Reserved Reserved Reserved
00 02A0 0000 00 02AF FFFF 1M Navigator configuration Navigator configuration Navigator configuration
00 02B0 0000 00 02BF FFFF 1M Navigator linking RAM Navigator linking RAM Navigator linking RAM
00 02C0 0000 00 02C0 FFFF 64K Reserved Reserved Reserved
00 02C1 0000 00 02C1 FFFF 64K Reserved Reserved Reserved
00 02C2 0000 00 02C3 FFFF 128K Reserved Reserved Reserved
00 02C4 0000 00 02C5 FFFF 128K Reserved Reserved Reserved
00 02C6 0000 00 02C7 FFFF 128K Reserved Reserved Reserved
00 02C8 0000 00 02C8 FFFF 64K Reserved Reserved Reserved
00 02C9 0000 00 02C9 FFFF 64K Reserved Reserved Reserved
00 02CA 0000 00 02CB FFFF 128K Reserved Reserved Reserved
00 02CC 0000 00 02CD FFFF 128K Reserved Reserved Reserved
00 02CE 0000 00 02EF FFFF 15M-896K Reserved Reserved Reserved
00 02F0 0000 00 02FF FFFF 1M 10GbE Config (66AK2H14 only) 10GbE Config (66AK2H14 only) 10GbE Config (66AK2H14 only)
00 0300 0000 00 030F FFFF 1M Debug_SS Configuration Debug_SS Configuration Debug_SS Configuration
00 0310 0000 00 07FF FFFF 79M Reserved Reserved Reserved
00 0800 0000 00 0801 FFFF 128K Reserved Extended memory controller (XMC) configuration Reserved
00 0802 0000 00 0BBF FFFF 60M-128K Reserved Reserved Reserved
00 0BC0 0000 00 0BCF FFFF 1M Multicore shared memory controller (MSMC) config Multicore shared memory controller (MSMC) config Multicore shared memory controller (MSMC) config
00 0BD0 0000 00 0BFF FFFF 3M Reserved Reserved Reserved
00 0C00 0000 00 0C5F FFFF 6M Multicore shared memory (MSM) Multicore shared memory (MSM) Multicore shared memory (MSM)
00 0C60 0000 00 0FFF FFFF 58M Reserved Reserved Reserved
00 1000 0000 00 107F FFFF 8M Reserved Reserved Reserved
00 1080 0000 00 108F FFFF 1M CorePac0 L2 SRAM CorePac0 L2 SRAM CorePac0 L2 SRAM
00 1090 0000 00 10DF FFFF 5M Reserved Reserved Reserved
00 10E0 0000 00 10E0 7FFF 32K CorePac0 L1P SRAM CorePac0 L1P SRAM CorePac0 L1P SRAM
00 10E0 8000 00 10EF FFFF 1M-32K Reserved Reserved Reserved
00 10F0 0000 00 10F0 7FFF 32K CorePac0 L1D SRAM CorePac0 L1D SRAM CorePac0 L1D SRAM
00 10F0 8000 00 117F FFFF 9M-32K Reserved Reserved Reserved
00 1180 0000 00 118F FFFF 1M CorePac1 L2 SRAM CorePac1 L2 SRAM CorePac1 L2 SRAM
00 1190 0000 00 11DF FFFF 5M Reserved Reserved Reserved
00 11E0 0000 00 11E0 7FFF 32K CorePac1 L1P SRAM CorePac1 L1P SRAM CorePac1 L1P SRAM
00 11E0 8000 00 11EF FFFF 1M-32K Reserved Reserved Reserved
00 11F0 0000 00 11F0 7FFF 32K CorePac1 L1D SRAM CorePac1 L1D SRAM CorePac1 L1D SRAM
00 11F0 8000 00 127F FFFF 9M-32K Reserved Reserved Reserved
00 1280 0000 00 128F FFFF 1M CorePac2 L2 SRAM CorePac2 L2 SRAM CorePac2 L2 SRAM
00 1290 0000 00 12DF FFFF 5M Reserved Reserved Reserved
00 12E0 0000 00 12E0 7FFF 32K CorePac2 L1P SRAM CorePac2 L1P SRAM CorePac2 L1P SRAM
00 12E0 8000 00 12EF FFFF 1M-32K Reserved Reserved Reserved
00 12F0 0000 00 12F0 7FFF 32K CorePac2 L1D SRAM CorePac2 L1D SRAM CorePac2 L1D SRAM
00 12F0 8000 00 137F FFFF 9M-32K Reserved Reserved Reserved
00 1380 0000 00 1388 FFFF 1M CorePac3 L2 SRAM CorePac3 L2 SRAM CorePac3 L2 SRAM
00 1390 0000 00 13DF FFFF 5M Reserved Reserved Reserved
00 13E0 0000 00 13E0 7FFF 32K CorePac3 L1P SRAM CorePac3 L1P SRAM CorePac3 L1P SRAM
00 13E0 8000 00 13EF FFFF 1M-32K Reserved Reserved Reserved
00 13F0 0000 00 13F0 7FFF 32K CorePac3 L1D SRAM CorePac3 L1D SRAM CorePac3 L1D SRAM
00 13F0 8000 00 147F FFFF 9M-32K Reserved Reserved Reserved
00 1480 0000 00 148F FFFF 1M CorePac4 L2 SRAM (66AK2H12/14 only) CorePac4 L2 SRAM (66AK2H12/14 only) CorePac4 L2 SRAM (66AK2H12/14 only)
00 1490 0000 00 14DF FFFF 5M Reserved Reserved Reserved
00 14E0 0000 00 14E0 7FFF 32K CorePac4 L1P SRAM (66AK2H12/14 only) CorePac4 L1P SRAM (66AK2H12/14 only) CorePac4 L1P SRAM (66AK2H12/14 only)
00 14E0 8000 00 14EF FFFF 1M-32K Reserved Reserved Reserved
00 14F0 0000 00 14F0 7FFF 32K CorePac4 L1D SRAM (66AK2H12/14 only) CorePac4 L1D SRAM (66AK2H12/14 only) CorePac4 L1D SRAM (66AK2H12/14 only)
00 14F0 8000 00 157F FFFF 9M-32K Reserved Reserved Reserved
00 1580 0000 00 158F FFFF 1M CorePac5 L2 SRAM (66AK2H12/14 only) CorePac5 L2 SRAM (66AK2H12/14 only) CorePac5 L2 SRAM (66AK2H12/14 only)
00 1590 0000 00 15DF FFFF 5M Reserved Reserved Reserved
00 15E0 0000 00 15E0 7FFF 32K CorePac5 L1P SRAM (66AK2H12/14 only) CorePac5 L1P SRAM (66AK2H12/14 only) CorePac5 L1P SRAM (66AK2H12/14 only)
00 15E0 8000 00 15EF FFFF 1M-32K Reserved Reserved Reserved
00 15F0 0000 00 15F0 7FFF 32K CorePac5 L1D SRAM (66AK2H12/14 only) CorePac5 L1D SRAM (66AK2H12/14 only) CorePac5 L1D SRAM (66AK2H12/14 only)
00 15F0 8000 00 167F FFFF 9M-32K Reserved Reserved Reserved
00 1680 0000 00 168F FFFF 1M CorePac6 L2 SRAM (66AK2H12/14 only) CorePac6 L2 SRAM (66AK2H12/14 only) CorePac6 L2 SRAM (66AK2H12/14 only)
00 1690 0000 00 16DF FFFF 5M Reserved Reserved Reserved
00 16E0 0000 00 16E0 7FFF 32K CorePac6 L1P SRAM (66AK2H12/14 only) CorePac6 L1P SRAM (66AK2H12/14 only) CorePac6 L1P SRAM (66AK2H12/14 only)
00 16E0 8000 00 16EF FFFF 1M-32K Reserved Reserved Reserved
00 16F0 0000 00 16F0 7FFF 32K CorePac6 L1D SRAM (66AK2H12/14 only) CorePac6 L1D SRAM (66AK2H12/14 only) CorePac6 L1D SRAM (66AK2H12/14 only)
00 16F0 8000 00 177F FFFF 9M-32K Reserved Reserved Reserved
00 1780 0000 00 178F FFFF 1M CorePac7 L2 SRAM (66AK2H12/14 only) CorePac7 L2 SRAM (66AK2H12/14 only) CorePac7 L2 SRAM (66AK2H12/14 only)
00 1790 0000 00 17DF FFFF 5M Reserved Reserved Reserved
00 17E0 0000 00 17E0 7FFF 32K CorePac7 L1P SRAM (66AK2H12/14 only) CorePac7 L1P SRAM (66AK2H12/14 only) CorePac7 L1P SRAM (66AK2H12/14 only)
00 17E0 8000 00 17EF FFFF 1M-32K Reserved Reserved Reserved
00 17F0 0000 00 17F0 7FFF 32K CorePac7 L1D SRAM (66AK2H12/14 only) CorePac7 L1D SRAM (66AK2H12/14 only) CorePac7 L1D SRAM (66AK2H12/14 only)
00 17F0 8000 00 1FFF FFFF 129M-32K Reserved Reserved Reserved
00 2000 0000 00 200F FFFF 1M System trace manager (STM) configuration System trace manager (STM) configuration System trace manager (STM) configuration
00 2010 0000 00 201F FFFF 1M Reserved Reserved Reserved
00 2020 0000 00 205F FFFF 4M Reserved Reserved Reserved
00 2060 0000 00 206F FFFF 1M Reserved Reserved Reserved
00 2070 0000 00 207F FFFF 1M Reserved Reserved Reserved
00 2080 0000 00 208F FFFF 1M Reserved Reserved Reserved
00 2090 0000 00 209F FFFF 1M Reserved Reserved Reserved
00 20A0 0000 00 20A3 FFFF 256K Reserved Reserved Reserved
00 20A4 0000 00 20A4 FFFF 64K Reserved Reserved Reserved
00 20A5 0000 00 20AF FFFF 704K Reserved Reserved Reserved
00 20B0 0000 00 20B3 FFFF 256K Boot ROM Boot ROM Boot ROM
00 20B4 0000 00 20BE FFFF 704K Reserved Reserved Reserved
00 20BF 0000 00 20BF 01FF 64K Reserved Reserved Reserved
00 20C0 0000 00 20FF FFFF 4M Reserved Reserved Reserved
00 2100 0000 00 2100 03FF 1K Reserved Reserved Reserved
00 2100 0400 00 2100 05FF 512 SPI0 SPI0 SPI0
00 2100 0600 00 2100 07FF 512 SPI1 SPI1 SPI1
00 2100 0800 00 2100 09FF 512 SPI2 SPI2 SPI2
00 2100 0A00 00 2100 0AFF 256 EMIF Config EMIF Config EMIF Config
00 2100 0B00 00 2100 FFFF 62K-768 Reserved Reserved Reserved
00 2101 0000 00 2101 01FF 512 DDR3A EMIF Config DDR3A EMIF Config DDR3A EMIF Config
00 2101 0200 00 2101 07FF 2K-512 Reserved Reserved Reserved
00 2101 0800 00 2101 09FF 512 Reserved Reserved Reserved
00 2101 0A00 00 2101 0FFF 2K-512 Reserved Reserved Reserved
00 2101 1000 00 2101 FFFF 60K Reserved Reserved Reserved
00 2102 0000 00 2103 FFFF 128K DDR3B EMIF configuration DDR3B EMIF configuration DDR3B EMIF configuration
00 2104 0000 00 217F FFFF 4M-256K Reserved Reserved Reserved
00 2140 0000 00 2140 00FF 256 HyperLink0 config HyperLink0 config HyperLink0 config
00 2140 0100 00 2140 01FF 256 HyperLink1 config HyperLink1 config HyperLink1 config
00 2140 0400 00 217F FFFF 4M-512 Reserved Reserved Reserved
00 2180 0000 00 2180 7FFF 32K PCIe config PCIe config PCIe config
00 2180 8000 00 21BF FFFF 4M-32K Reserved Reserved Reserved
00 21C0 0000 00 21FF FFFF 4M Reserved Reserved Reserved
00 2200 0000 00 229F FFFF 10M Reserved Reserved Reserved
00 22A0 0000 00 22A0 FFFF 64K Reserved Reserved Reserved
00 22A1 0000 00 22AF FFFF 1M-64K Reserved Reserved Reserved
00 22B0 0000 00 22B0 FFFF 64K Reserved Reserved Reserved
00 22B1 0000 00 22BF FFFF 1M-64K Reserved Reserved Reserved
00 22C0 0000 00 22C0 FFFF 64K Reserved Reserved Reserved
00 22C1 0000 00 22CF FFFF 1M-64K Reserved Reserved Reserved
00 22D0 0000 00 22D0 FFFF 64K Reserved Reserved Reserved
00 22D1 0000 00 22DF FFFF 1M-64K Reserved Reserved Reserved
00 22E0 0000 00 22E0 FFFF 64K Reserved Reserved Reserved
00 22E1 0000 00 22EF FFFF 1M-64K Reserved Reserved Reserved
00 22F0 0000 00 22F0 FFFF 64K Reserved Reserved Reserved
00 22F1 0000 00 22FF FFFF 1M-64K Reserved Reserved Reserved
00 2300 0000 00 2300 FFFF 64K Reserved Reserved Reserved
00 2301 0000 00 230F FFFF 1M-64K Reserved Reserved Reserved
00 2310 0000 00 2310 FFFF 64K Reserved Reserved Reserved
00 2311 0000 00 231F FFFF 1M-64K Reserved Reserved Reserved
00 2320 0000 00 2324 FFFF 384K Reserved Reserved Reserved
00 2325 0000 00 239F FFFF 8M-384K Reserved Reserved Reserved
00 23A0 0000 00 23BF FFFF 2M Navigator Navigator Navigator
00 23C0 0000 00 23FF FFFF 4M Reserved Reserved Reserved
00 2400 0000 00 27FF FFFF 64M Reserved Reserved Reserved
00 2800 0000 00 2FFF FFFF 128M HyperLink1 data HyperLink1 data HyperLink1 data
00 3000 0000 00 33FF FFFF 64M EMIF16 CE0 EMIF16 CE0 EMIF16 CE0
00 3400 0000 00 37FF FFFF 64M EMIF16 CE1 EMIF16 CE1 EMIF16 CE1
00 3800 0000 00 3BFF FFFF 64M EMIF16 CE2 EMIF16 CE2 EMIF16 CE2
00 3C00 0000 00 3FFF FFFF 64M EMIF16 CE3 EMIF16 CE3 EMIF16 CE3
00 4000 0000 00 4FFF FFFF 256M HyperLink0 data HyperLink0 data HyperLink0 data
00 5000 0000 00 5FFF FFFF 256M PCIe data PCIe data PCIe data
00 6000 0000 00 7FFF FFFF 512M DDR3B data(2)(3) DDR3B data(4) DDR3B data
00 8000 0000 00 FFFF FFFF 2G DDR3A data/DDR3B data(2)(5) DDR3B data DDR3A data(6)
01 0000 0000 01 2100 FFFF 528M+64K Reserved Reserved Reserved
01 2101 0000 01 2101 01FF 512 DDR3A EMIF configuration(7) DDR3A EMIF configuration(8) DDR3A EMIF configuration(9)
01 2101 0200 07 FFFF FFFF 32G-512 Reserved Reserved Reserved
08 0000 0000 09 FFFF FFFF 8G DDR3A data DDR3A data(8) DDR3A data(9)
0A 0000 0000 FF FFFF FFFF 984G Reserved Reserved Reserved
(1) 66AK2H12/14 only.
(2) No IO coherency supported for this region (see the KeyStone II Architecture ARM CorePac User's Guide).
(3) This region is mapped to DDR3B. It is aliased of 00 8000 0000 to 00 9FFF FFFF (the first 512MB of DDR3B) if the state of DDR3A_REMAP_EN pin at boot time is ‘0’.
(4) This region is aliased of 00 8000 0000 to 00 9FFF FFFF (the first 512MB of DDR3B).
(5) This region is mapped to DDR3A or DDR3B depending on the state of DDR3A_REMAP_EN pin at boot time. If the pin is ‘1’, this region is mapped to the first 2GB of DDR3A which is aliased of 08 0000 0000 to 08 7FFF FFFF. If the pin is ‘0’, this region is mapped as 2GB of DDR3B.
(6) MPAX from SES port extends the address to this region.
(7) This region is aliased to 00 2101 0000-00 2101 01FF.
(8) Access to 40-bit address requires XMC MPAX programmation.
(9) Access to 40-bit address requires MSMC MPAX programmation. MPAX from SES port need to remap the region of 00 2101 0000-00 2101 01FF to this region.

8.2 Memory Protection Unit (MPU) for 66AK2Hxx

CFG (configuration) space of all slave devices on the TeraNet is protected by the MPU. The 66AK2Hxx contains 15 MPUs:

  • MPU0 is used for main TeraNet_3P_B (SCR_3P (B)) CFG.
  • MPU1/2/5 are used for QM_SS (one for VBUSM port and one each for the two configuration VBUSP ports).
  • MPU3/4/6 are reserved.
  • MPU7 is used for DDR3_B.
  • MPU8 is used for EMIF16.
  • MPU9 is used for interrupt controllers connected to TeraNet_3P (SCR_3P).
  • MPU10 is used for semaphore.
  • MPU11 is used to protect TeraNet_6P_B (SCR_6P (B)) CPU/6 CFG TeraNet.
  • MPU12/13/14 are used for SPI0/1/2.

This section contains MPU register map and details of device-specific MPU registers only. For MPU features and details of generic MPU registers, see the KeyStone Architecture Memory Protection Unit (MPU) User's Guide.

Table 8-2, Table 8-3, and Table 8-4 show the configuration of each MPU and the memory regions protected by each MPU.

Table 8-2 MPU0-MPU5 Default Configuration

SETTING MPU0 MAIN SCR_3P (B) MPU1 (QM_SS DATA PORT) MPU2 (QM_SS CFG1 PORT) MPU3 MPU4 MPU5 (QM_SS CFG2 PORT)
Default permission Assume allowed Assume allowed Assume allowed Reserved Reserved Assume allowed
Number of allowed IDs supported 16 16 16 16
Number of programmable ranges supported 16 16 16 16
Compare width 1KB granularity 1KB granularity 1KB granularity 1KB granularity

Table 8-3 MPU6-MPU11 Default Configuration

SETTING MPU6 MPU7 DDR3B MPU8 EMIF16 MPU9 INTC MPU10 SM MPU11 SCR_6P (B)
Default permission Reserved Assume allowed Assume allowed Assume allowed Assume allowed Assume allowed
Number of allowed IDs supported 16 16 16 16 16
Number of programmable ranges supported 16 8 4 2 16
Compare width 1KB granularity 1KB granularity 1KB granularity 1KB granularity 1KB granularity

Table 8-4 MPU12-MPU14 Default Configuration

SETTING MPU12 SPI0 MPU13 SPI1 MPU14 SPI2
Default permission Assume allowed Assume allowed Assume allowed
Number of allowed IDs supported 16 16 16
Number of programmable ranges supported 2 2 2
Compare width 1KB granularity 1KB granularity 1KB granularity

Table 8-5 MPU Memory Regions

MEMORY PROTECTION START ADDRESS END ADDRESS
MPU0 Main CFG SCR 0x01D0_0000 0x01E7_FFFF
MPU1 QM_SS DATA PORT 0x23A0_0000 0x23BF_FFFF
MPU2 QM_SS CFG1 PORT 0x02A0_0000 0x02AF_FFFF
MPU3 Reserved 0x027C_0000 0x027C_03FF
MPU4 Reserved 0x0210_0000 0x0215_FFFF
MPU5 QM_SS CFG2 PORT 0x02A0_4000 0x02BF_FFFF
MPU6 Reserved 0x02C0_0000 0x02CD_FFFF
MPU7 DDR3B 0x2101_0000 0xFFFF_FFFF
MPU8 SPIROM/EMIF16 0x20B0_0000 0x3FFF_FFFF
MPU9 INTC/AINTC 0x0264_0000 0x0264_07FF
MPU10 Semaphore 0x0260_0000 0x0260_9FFF
MPU11 SCR_6 and CPU/6 CFG SCR 0x0220_0000 0x03FF_FFFF
MPU12 SPI0 0x2100_0400 0x2100_07FF
MPU13 SPI1 0x2100_0400 0x2100_07FF
MPU14 SPI2 0x2100_0800 0x2100_0AFF

Table 8-6 shows the unique Master ID assigned to each CorePac and peripherals on the device.

Table 8-6 Master ID Settings

MASTER ID 66AK2H12/14 66AK2H06
0 C66x CorePac0 Data
1 C66x CorePac1 Data
2 C66x CorePac2 Data
3 C66x CorePac3 Data
4 C66x CorePac4 Data Reserved
5 C66x CorePac5 Data Reserved
6 C66x CorePac6 Data Reserved
7 C66x CorePac7 Data Reserved
8 ARM CorePac 0 noncache accesses and cache accesses for all ARM cores
9 ARM CorePac 1 noncache accesses
10 ARM CorePac 2 noncache accesses Reserved
11 ARM CorePac 3 noncache accesses Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
16 C66x CorePac0 CFG
17 C66x CorePac1 CFG
18 C66x CorePac2 CFG
19 C66x CorePac3 CFG
20 C66x CorePac4 CFG Reserved
21 C66x CorePac5 CFG Reserved
22 C66x CorePac6 CFG Reserved
23 C66x CorePac7 CFG Reserved
24 Reserved
25 EDMA0_TC0 read
26 EDMA0_TC0 write
27 EDMA0_TC1 read
28 Hyperlink0
29 Hyperlink1
30 SRIO
31 PCIE
32 EDMA0_TC1 write
33 EDMA1_TC0 read
34 EDMA1_TC0 write
35 EDMA1_TC1 read
36 EDMA1_TC1write
37 EDMA1_TC2 read
38 EDMA1_TC2 write
39 EDMA1_TC3 read
40 EDMA1_TC3 write
41 EDMA2_TC0 read
42 EDMA2_TC0 write
43 EDMA2_TC1 read
44 EDMA2_TC1 write
45 EDMA2_TC2 read
46 EDMA2_TC2 write
47 EDMA2_TC3 read
48 EDMA2_TC3 write
49 EDMA3_TC0 read
50 EDMA3_TC0 write
51 EDMA3_TC1 read
52 MSMC(1)
53 EDMA3_TC1 write
54 to 55 SRIO PKTDMA
56 Reserved
57 Reserved
58 Reserved
59 Reserved
60 Reserved
61 Reserved
62 EDMA3CC0
63 EDMA3CC1
64 EDMA3CC2
65 Reserved
66 Reserved
67 Reserved
68 to 71 Queue Manager
72 to 79 Reserved
80 Reserved
81 Reserved
82 Reserved
83 EDMA3_CC_TR
84 to 87 10GbE (66AK2H14 only)
88 to 91 Reserved
92 to 95 Packet Coprocessor MST2
96 to 99 Packet Coprocessor MST1
100 to 101 Reserved
102 Reserved
103 Reserved
104 Reserved
105 Reserved
106 Reserved
107 DBG_DAP
108-139 Reserved
140 CPT_L2_0
141 CPT_L2_1
142 CPT_L2_2
143 CPT_L2_3
144 CPT_L2_4
145 CPT_L2_5
146 CPT_L2_6
147 CPT_L2_7
148 CPT_MSMC0
149 CPT_MSMC1
150 CPT_MSMC2
151 CPT_MSMC3
152 CPT_DDR3A
153 CPT_SM
154 CPT_QM_CFG1
155 CPT_QM_M
156 CPT_CFG
157 Reserved
158 Reserved
159 Reserved
160 CPT_QM_CFG2
161 CPT_DDR3B
162 Reserved
163 Reserved
164 CPT_EDMA3CC0_4
165 CPT_EDMA3CC1_2_3
166 CPT_INTC
167 CPT_SPI_ROM_EMIP16
168 USB
169 EDMA4_TC0 read
170 EDMA4_TC0 write
171 EDMA4_TC1 read
172 EDMA4_TC1 write
173 EDMA4_CC_TR
174 CPT_MSMC5
175 CPT_MSMC6
176 CPT_MSMC7
177 CPT_MSMC4
178 Reserved
179 Reserved
180-183 NETCP
184-255 Reserved
(1) The master ID for MSMC is for the transaction initiated by MSMC internally and sent to the DDR.

NOTE

There are two master ID values assigned to the Queue Manager_second master port, one master ID for external linking RAM and the other one for the PDSP/MCDM accesses.

Table 8-7 shows the privilege ID of each C66x CorePac and every mastering peripheral. The table also shows the privilege level (supervisor vs. user), security level (secure vs. nonsecure), and access type (instruction read vs. data/DMA read or write) of each master on the device. In some cases, a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral.

Table 8-7 Privilege ID Settings

PRIVILEGE ID MASTER PRIVILEGE LEVEL SECURITY LEVEL ACCESS TYPE
0 C66x CorePac0 SW dependant, driven by MSMC Nonsecure DMA
1 C66x CorePac1 SW dependant, driven by MSMC Nonsecure DMA
2 C66x CorePac2 SW dependant, driven by MSMC Nonsecure DMA
3 C66x CorePac3 SW dependant, driven by MSMC Nonsecure DMA
4 C66x CorePac4 SW dependant, driven by MSMC Nonsecure DMA
5 C66x CorePac5 SW dependant, driven by MSMC Nonsecure DMA
6 C66x CorePac6 SW dependant, driven by MSMC Nonsecure DMA
7 C66x CorePac7 SW dependant, driven by MSMC Nonsecure DMA
8 ARM CorePac SW dependent Nonsecure DMA
9 SRIO_M and all Packet DMA masters (NetCP, Both QM_CDMA, SRIO_CDMA, 10GbE(1)), USB User/driven by SRIO block, user mode and supervisor mode is determined by per transaction basis. Only the transaction with source ID matching the value in SupervisorID register is granted supervisor mode. Nonsecure DMA
10 QM_Second(2) User Nonsecure DMA
11 PCIe Supervisor Nonsecure DMA
12 DAP Driven by Emulation SW Nonsecure DMA
13 Reserved
14 HyperLink Supervisor Nonsecure DMA
15 Reserved
(1) 66AK2H14 only.
(2) QM_Second provides a path that PDSP uses to access the system memory.

8.2.1 MPU Registers

This section includes the offsets for MPU registers and definitions for device-specific MPU registers. For Number of Programmable Ranges supported (PROGx_MPSA, PROGxMPEA) refer to the following tables.

8.2.1.1 MPU Register Map

Table 8-8 MPU Registers

OFFSET NAME DESCRIPTION
0h REVID Revision ID
4h CONFIG Configuration
10h IRAWSTAT Interrupt raw status/set
14h IENSTAT Interrupt enable status/clear
18h IENSET Interrupt enable
1Ch IENCLR Interrupt enable clear
20h EOI End of interrupt
200h PROG0_MPSAR Programmable range 0, start address
204h PROG0_MPEAR Programmable range 0, end address
208h PROG0_MPPAR Programmable range 0, memory page protection attributes
210h PROG1_MPSAR Programmable range 1, start address
214h PROG1_MPEAR Programmable range 1, end address
218h PROG1_MPPAR Programmable range 1, memory page protection attributes
220h PROG2_MPSAR Programmable range 2, start address
224h PROG2_MPEAR Programmable range 2, end address
228h PROG2_MPPAR Programmable range 2, memory page protection attributes
230h PROG3_MPSAR Programmable range 3, start address
234h PROG3_MPEAR Programmable range 3, end address
238h PROG3_MPPAR Programmable range 3, memory page protection attributes
240h PROG4_MPSAR Programmable range 4, start address
244h PROG4_MPEAR Programmable range 4, end address
248h PROG4_MPPAR Programmable range 4, memory page protection attributes
250h PROG5_MPSAR Programmable range 5, start address
254h PROG5_MPEAR Programmable range 5, end address
258h PROG5_MPPAR Programmable range 5, memory page protection attributes
260h PROG6_MPSAR Programmable range 6, start address
264h PROG6_MPEAR Programmable range 6, end address
268h PROG6_MPPAR Programmable range 6, memory page protection attributes
270h PROG7_MPSAR Programmable range 7, start address
274h PROG7_MPEAR Programmable range 7, end address
278h PROG7_MPPAR Programmable range 7, memory page protection attributes
280h PROG8_MPSAR Programmable range 8, start address
284h PROG8_MPEAR Programmable range 8, end address
288h PROG8_MPPAR Programmable range 8, memory page protection attributes
290h PROG9_MPSAR Programmable range 9, start address
294h PROG9_MPEAR Programmable range 9, end address
298h PROG9_MPPAR Programmable range 9, memory page protection attributes
2A0h PROG10_MPSAR Programmable range 10, start address
2A4h PROG10_MPEAR Programmable range 10, end address
2A8h PROG10_MPPAR Programmable range 10, memory page protection attributes
2B0h PROG11_MPSAR Programmable range 11, start address
2B4h PROG11_MPEAR Programmable range 11, end address
2B8h PROG11_MPPAR Programmable range 11, memory page protection attributes
2C0h PROG12_MPSAR Programmable range 12, start address
2C4h PROG12_MPEAR Programmable range 12, end address
2C8h PROG12_MPPAR Programmable range 12, memory page protection attributes
2D0h PROG13_MPSAR Programmable range 13, start address
2D4h PROG13_MPEAR Programmable range 13, end address
2Dh PROG13_MPPAR Programmable range 13, memory page protection attributes
2E0h PROG14_MPSAR Programmable range 14, start address
2E4h PROG14_MPEAR Programmable range 14, end address
2E8h PROG14_MPPAR Programmable range 14, memory page protection attributes
2F0h PROG15_MPSAR Programmable range 15, start address
2F4h PROG15_MPEAR Programmable range 15, end address
2F8h PROG15_MPPAR Programmable range 15, memory page protection attributes
300h FLTADDRR Fault address
304h FLTSTAT Fault status
308h FLTCLR Fault clear

8.2.1.2 Device-Specific MPU Registers

8.2.1.2.1 Configuration Register (CONFIG)

The configuration register (CONFIG) contains the configuration value of the MPU as described in Table 8-9.

Table 8-9 Configuration Register Field Descriptions

Bits Field Description
31-24 ADDR_WIDTH Address alignment for range checking
  • 0 = 1KB alignment
  • 6 = 64KB alignment
23-20 NUM_FIXED Number of fixed address ranges
19-16 NUM_PROG Number of programmable address ranges
15-12 NUM_AIDS Number of supported AIDs
11-1 Reserved Reserved. Always read as 0.
0 ASSUME_ALLOWED Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not.
  • 0 = Assume disallowed
  • 1 = Assume allowed

8.2.2 MPU Programmable Range Registers

8.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)

The Programmable Address Start Register holds the start address for the range. This register is writeable by a supervisor entity only. If NS = 0 (nonsecure mode) in the associated MPPAR register, then the register is also writeable only by a secure entity.

The start address must be aligned on a page boundary. The size of the page is 1KB. The size of the page determines the width of the address field in MPSAR and MPEAR. The PROGn_MPSAR register is shown in Figure 8-1 and described in Table 8-10. The reset values are listed in Table 8-11 for MPU0-MPU5, Table 8-12 for MPU6-MPU11, and Table 8-13 for MPU12-MPU14.

Figure 8-1 Programmable Range n Start Address Register (PROGn_MPSAR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
START_ADDR Reserved
R/W R
Legend: R = Read only; R/W = Read/Write

Table 8-10 Programmable Range n Start Address Register Field Descriptions

Bit Field Description
31-10 START_ADDR Start address for range n
9-0 Reserved Reserved. Always read as 0.

Table 8-11 MPU0-MPU5 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values

REGISTER MPU0 MPU1 MPU2 MPU3 MPU4 MPU5
PROG0_MPSAR 0x01D0_0000 0x23A0_0000 0x02A0_0000 Reserved Reserved 0x02A0_4000
PROG1_MPSAR 0x01F0_0000 0x23A0_2000 0x02A0_2000 Reserved Reserved 0x02A0_5000
PROG2_MPSAR 0x02F0_0000 0x023A_6000 0x02A0_6000 Reserved Reserved 0x02A0_6400
PROG3_MPSAR 0x0200_0000 0x23A0_6800 0x02A0_6800 Reserved Reserved 0x02A0_7400
PROG4_MPSAR 0x020C_0000 0x23A0_7000 0x02A0_7000 Reserved Reserved 0x02A0_A000
PROG5_MPSAR 0x021C_0000 0x23A0_8000 0x02A0_8000 Reserved Reserved 0x02A0_D000
PROG6_MPSAR 0x021D_0000 0x23A0_C000 0x02A0_C000 Reserved Reserved 0x02A0_E000
PROG7_MPSAR 0x021F_0000 0x23A0_E000 0x02A0_E000 Reserved Reserved 0x02A0_F000
PROG8_MPSAR 0x0234_0000 0x23A0_F000 0x02A0_F000 Reserved Reserved 0x02A0_F800
PROG9_MPSAR 0x0254_0000 0x23A0_F800 0x02A0_F800 Reserved Reserved 0x02A1_2000
PROG10_MPSAR 0x0258_0000 0x23A1_0000 0x02A1_0000 Reserved Reserved 0x02A1_C000
PROG11_MPSAR 0x0000_0000 0x23A1_C000 0x02A2_0000 Reserved Reserved 0x02A2_8000
PROG12_MPSAR 0x0290_0000 0x23A4_0000 0x02A4_0000 Reserved Reserved 0x02A6_0000
PROG13_MPSAR 0x01E8_0000 0x23A8_0000 0x02A8_0000 Reserved Reserved 0x02AA_0000
PROG14_MPSAR 0x01E8_0800 0x23B0_0000 0x02AC_0000 Reserved Reserved 0x02B0_0000
PROG15_MPSAR 0x01E0_0000 0x23B8_0000 0x02AE_0000 Reserved Reserved 0x02B8_0000

Table 8-12 MPU6-MPU11 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values

REGISTER MPU6 MPU7 MPU8 MPU9 MPU10 MPU11
PROG0_MPSAR Reserved 0x2101_0000 0x3000_0000 0x0260_0000 0x0264_0000 0x0220_0000
PROG1_MPSAR Reserved 0x0000_0000 0x3200_0000 0x0260_4000 0x0000_0000 0x0231_0000
PROG2_MPSAR Reserved 0x0800_0000 0x3400_0000 0x0260_8000 N/A 0x0231_A000
PROG3_MPSAR Reserved 0x1000_0000 0x3600_0000 0x0256_0000 N/A 0x0233_0000
PROG4_MPSAR Reserved 0x1800_0000 0x3800_0000 0x0000_0000 N/A 0x0235_0000
PROG5_MPSAR Reserved 0x2000_0000 0x3A00_0000 0x0000_0000 N/A 0x0263_0000
PROG6_MPSAR Reserved 0x2800_0000 0x3C00_0000 0x0000_0000 N/A 0x0244_0000
PROG7_MPSAR Reserved 0x3000_0000 0x2100_0800 0x0000_0000 N/A 0x024C_0000
PROG8_MPSAR Reserved 0x3800_0000 N/A 0x0000_0000 N/A 0x0250_0000
PROG9_MPSAR Reserved 0x4000_0000 N/A 0x0000_0000 N/A 0x0253_0000
PROG10_MPSAR Reserved 0x4800_0000 N/A 0x0000_0000 N/A 0x0253_0C00
PROG11_MPSAR Reserved 0x5000_0000 N/A 0x0000_0000 N/A 0x0260_B000
PROG12_MPSAR Reserved 0x5800_0000 N/A 0x0000_0000 N/A 0x0262_0000
PROG13_MPSAR Reserved 0x6000_0000 N/A 0x0000_0000 N/A 0x0300_0000
PROG14_MPSAR Reserved 0x6800_0000 N/A 0x0000_0000 N/A 0x021E_0000
PROG15_MPSAR Reserved 0x7000_0000 N/A 0x0000_0000 N/A 0x0268_0000

Table 8-13 MPU12-MPU14 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values

REGISTER MPU12 MPU13 MPU14
PROG0_MPSAR 0x2100_0400 0x2100_0400 0x2100_0800
PROG1_MPSAR 0x0000_0000 0x0000_0000 0x0000_0000
PROG2_MPSAR N/A N/A N/A
PROG3_MPSAR N/A N/A N/A
PROG4_MPSAR N/A N/A N/A
PROG5_MPSAR N/A N/A N/A
PROG6_MPSAR N/A N/A N/A
PROG7_MPSAR N/A N/A N/A
PROG8_MPSAR N/A N/A N/A
PROG9_MPSAR N/A N/A N/A
PROG10_MPSAR N/A N/A N/A
PROG11_MPSAR N/A N/A N/A
PROG12_MPSAR N/A N/A N/A
PROG13_MPSAR N/A N/A N/A
PROG14_MPSAR N/A N/A N/A
PROG15_MPSAR N/A N/A N/A

8.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)

The programmable address end register holds the end address for the range. This register is writeable by a supervisor entity only. If NS = 0 (nonsecure mode) in the associated MPPAR register then the register is also writeable only by a secure entity.

The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page size for MPU1 is 1KB and for MPU2 it is 64KB. The size of the page determines the width of the address field in MPSAR and MPEAR. The PROGn_MPEAR register is shown in Figure 8-2 and described in Table 8-14. The reset values are listed in Table 8-15 for MPU0-MPU5, Table 8-16 for MPU6-MPU11, and Table 8-17 for MPU12-MPU14.

Figure 8-2 Programmable Range n End Address Register (PROGn_MPEAR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
END_ADDR Reserved
R/W R
Legend: R = Read only; R/W = Read/Write

Table 8-14 Programmable Range n End Address Register Field Descriptions

Bit Field Description
31-10 END_ADDR End address for range n
9-0 Reserved Reserved. Always read as 3FFh.

Table 8-15 MPU0-MPU5 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values

REGISTER MPU0 MPU1 MPU2 MPU3 MPU4 MPU5
PROG0_MPEAR 0x01DF_FFFF 0x23A0_1FFF 0x02A0_00FF Reserved Reserved 0x02A0_4FFF
PROG1_MPEAR 0x01F7_FFFF 0x23A0_5FFF 0x02A0_3FFF Reserved Reserved 0x02A0_5FFF
PROG2_MPEAR 0x02FF_FFFF 0x23A0_67FF 0x02A0_63FF Reserved Reserved 0x02A0_67FF
PROG3_MPEAR 0x020B_FFFF 0x23A0_6FFF 0x02A0_6FFF Reserved Reserved 0x02A0_7FFF
PROG4_MPEAR 0x020F_FFFF 0x23A0_7FFF 0x02A0_73FF Reserved Reserved 0x02A0_BFFF
PROG5_MPEAR 0x021C_83FF 0x23A0_BFFF 0x02A0_9FFF Reserved Reserved 0x02A0_DFFF
PROG6_MPEAR 0x021D_C0FF 0x23A0_DFFF 0x02A0_CFFF Reserved Reserved 0x02A0_E7FF
PROG7_MPEAR 0x021F_C7FF 0x23A0_EFFF 0x02A0_E7FF Reserved Reserved 0x02A0_F7FF
PROG8_MPEAR 0x0234_C0FF 0x23A0_F7FF 0x02A0_F7FF Reserved Reserved 0x02A0_FFFF
PROG9_MPEAR 0x0255_FFFF 0x23A0_FFFF 0x02A0_FFFF Reserved Reserved 0x02A1_7FFF
PROG10_MPEAR 0x025F_FFFF 0x23A1_BFFF 0x02A1_1FFF Reserved Reserved 0x02A1_FFFF
PROG11_MPEAR 0x0000_0000 0x23A3_FFFF 0x02A2_5FFF Reserved Reserved 0x02A3_FFFF
PROG12_MPEAR 0x029F_FFFF 0x23A7_FFFF 0x02A5_FFFF Reserved Reserved 0x02A7_FFFF
PROG13_MPEAR 0x01E8_07FF 0x23AF_FFFF 0x02A9_FFFF Reserved Reserved 0x02AB_FFFF
PROG14_MPEAR 0x01E8_43FF 0x23B7_FFFF 0x02AD_FFFF Reserved Reserved 0x02B7_FFFF
PROG15_MPEAR 0x01E7_FFFF 0x23BF_FFFF 0x02AF_FFFF Reserved Reserved 0x02BF_FFFF

Table 8-16 MPU6-MPU11 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values

REGISTER MPU6 MPU7 MPU8 MPU9 MPU10 MPU11
PROG0_MPEAR Reserved 0x2103_FFFF 0x31FF_FFFF 0x0260_1FFF 0x0264_07FF 0x022F_027F
PROG1_MPEAR Reserved 0x07FF_FFFF 0x33FF_FFFF 0x0260_5FFF 0x0000_0000 0x0231_01FF
PROG2_MPEAR Reserved 0x0FFF_FFFF 0x35FF_FFFF 0x0260_9FFF N/A 0x0232_FFFF
PROG3_MPEAR Reserved 0x17FF_FFFF 0x37FF_FFFF 0x0257_FFFF N/A 0x0233_07FF
PROG4_MPEAR Reserved 0x1FFF_FFFF 0x39FF_FFFF Reserved N/A 0x0235_0FFF
PROG5_MPEAR Reserved 0x27FF_FFFF 0x3BFF_FFFF Reserved N/A 0x0263_FFFF
PROG6_MPEAR Reserved 0x2FFF_FFFF 0x3FFF_FFFF Reserved N/A 0x024B_3FFF
PROG7_MPEAR Reserved 0x37FF_FFFF 0x2100_0AFF Reserved N/A 0x024C_0BFF
PROG8_MPEAR Reserved 0x3FFF_FFFF N/A Reserved N/A 0x0250_7FFF
PROG9_MPEAR Reserved 0x47FF_FFFF N/A Reserved N/A 0x0253_0BFF
PROG10_MPEAR Reserved 0x4FFF_FFFF N/A Reserved N/A 0x0253_FFFF
PROG11_MPEAR Reserved 0x57FF_FFFF N/A Reserved N/A 0x0260_BFFF
PROG12_MPEAR Reserved 0x5FFF_FFFF N/A Reserved N/A 0x0262_0FFF
PROG13_MPEAR Reserved 0x67FF_FFFF N/A Reserved N/A 0x03FF_FFFF
PROG14_MPEAR Reserved 0x6FFF_FFFF N/A Reserved N/A 0x021E_1FFF
PROG15_MPEAR Reserved 0x7FFF_FFFF N/A Reserved N/A 0x026F_FFFF

Table 8-17 MPU12-MPU14 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values

REGISTER MPU12 MPU13 MPU14
PROG0_MPEAR 0x2100_07FF 0x2100_07FF 0x2100_0AFF
PROG1_MPEAR 0x0000_0000 0x0000_0000 0x0000_0000
PROG2_MPEAR N/A N/A N/A
PROG3_MPEAR N/A N/A N/A
PROG4_MPEAR N/A N/A N/A
PROG5_MPEAR N/A N/A N/A
PROG6_MPEAR N/A N/A N/A
PROG7_MPEAR N/A N/A N/A
PROG8_MPEAR N/A N/A N/A
PROG9_MPEAR N/A N/A N/A
PROG10_MPEAR N/A N/A N/A
PROG11_MPEAR N/A N/A N/A
PROG12_MPEAR N/A N/A N/A
PROG13_MPEAR N/A N/A N/A
PROG14_MPEAR N/A N/A N/A
PROG15_MPEAR N/A N/A N/A

8.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)

The programmable address memory protection page attribute register holds the permissions for the region. This register is writeable only by a nondebug supervisor entity. If NS = 0 (secure mode) then the register is also writeable only by a nondebug secure entity. The NS bit is writeable only by a nondebug secure entity. For debug accesses, the register is writeable only when NS = 1 or EMU = 1. The PROGn_MPPAR register is shown in Figure 8-3 and described in Table 8-18. The reset values are listed in Table 8-19 for MPU0-MPU5, Table 8-20 for MPU6-MPU11, and Table 8-21 for MPU12-MPU14.

Figure 8-3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved AID15 AID14 AID13 AID12 AID11 AID10 AID9 AID8 AID7 AID6
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AID5 AID4 AID3 AID2 AID1 AID0 AIDX Rsvd NS EMU SR SW SX UR UW UX
R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W

Table 8-18 Programmable Range n Memory Protection Page Attribute Register Field Descriptions

Bits Name Description
31-26 Reserved Reserved. Always read as 0.
25 AID15 Controls access from ID = 15
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
24 AID14 Controls access from ID = 14
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
23 AID13 Controls access from ID = 13
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
22 AID12 Controls access from ID = 12
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
21 AID11 Controls access from ID = 11
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
20 AID10 Controls access from ID = 10
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
19 AID9 Controls access from ID = 9
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
18 AID8 Controls access from ID = 8
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
17 AID7 Controls access from ID = 7
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
16 AID6 Controls access from ID = 6
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
15 AID5 Controls access from ID = 5
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
14 AID4 Controls access from ID = 4
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
13 AID3 Controls access from ID = 3
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
12 AID2 Controls access from ID = 2
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
11 AID1 Controls access from ID = 1
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
10 AID0 Controls access from ID = 0
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
9 AIDX Controls access from ID > 15
  • 0 = Access is not checked for permissions
  • 1 = Access is checked for permissions
8 Reserved Reserved. Always reads as 0.
7 NS Nonsecure access permission
  • 0 = Only secure access allowed
  • 1 = Nonsecure access allowed
6 EMU Emulation (debug) access permission. This bit is ignored if NS = 1
  • 0 = Debug access not allowed
  • 1 = Debug access allowed
5 SR Supervisor Read permission
  • 0 = Access not allowed
  • 1 = Access allowed
4 SW Supervisor Write permission
  • 0 = Access not allowed
  • 1 = Access allowed
3 SX Supervisor Execute permission
  • 0 = Access not allowed
  • 1 = Access allowed
2 UR User Read permission
  • 0 = Access not allowed
  • 1 = Access allowed
1 UW User Write permission
  • 0 = Access not allowed
  • 1 = Access allowed
0 UX User Execute permission
  • 0 = Access not allowed
  • 1 = Access allowed

Table 8-19 MPU0-MPU5 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) Reset Values

Register MPU0 MPU1 MPU2 MPU3 MPU4 MPU5
PROG0_MPPAR 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 Reserved Reserved 0x03FF_FCB4
PROG1_MPPAR 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCB4 Reserved Reserved 0x03FF_FCB4
PROG2_MPPAR 0x03FF_FCB6 0x03FF_FCA4 0x03FF_FCA4 Reserved Reserved 0x03FF_FCA4
PROG3_MPPAR 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCB4 Reserved Reserved 0x03FF_FCF4
PROG4_MPPAR 0x03FF_FCB6 0x03FF_FCF4 0x03FF_FCF4 Reserved Reserved 0x03FF_FCB4
PROG5_MPPAR 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCB4 Reserved Reserved 0x03FF_FCB4
PROG6_MPPAR 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCB4 Reserved Reserved 0x03FF_FCB4
PROG7_MPPAR 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCB4 Reserved Reserved 0x03FF_FCB4
PROG8_MPPAR 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCB4 Reserved Reserved 0x03FF_FCF4
PROG9_MPPAR 0x03FF_FCB6 0x03FF_FCF4 0x03FF_FCF4 Reserved Reserved 0x03FF_FCB4
PROG10_MPPAR 0x03FF_FCB6 0x03FF_FCB4 0x03FF_FCB4 Reserved Reserved 0x03FF_FCF4
PROG11_MPPAR 0x03FF_FCB6 0x03FF_FCF4 0x03FF_FCF4 Reserved Reserved 0x03FF_FCF4
PROG12_MPPAR 0x03FF_FCB4 0x03FF_FCA4 0x03FF_FCA4 Reserved Reserved 0x03FF_FCA4
PROG13_MPPAR 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6 Reserved Reserved 0x03FF_FCB6
PROG14_MPPAR 0x03FF_FCB0 0x03FF_FCA4 0x03FF_FCB6 Reserved Reserved 0x03FF_FCA4
PROG15_MPPAR 0x03FF_FCB6 0x03FF_FCA4 0x03FF_FCB6 Reserved Reserved 0x03FF_FCA4

Table 8-20 MPU6-MPU11 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) Reset Values

Register MPU6 MPU7 MPU8 MPU9 MPU10 MPU11
PROG0_MPPAR Reserved 0x03FF_FCB6 0x03FF_FCBF 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB6
PROG1_MPPAR Reserved 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCB6 0x03FF_FCB6 0x03FF_FCB0
PROG2_MPPAR Reserved 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCB6 N/A 0x03FF_FCB6
PROG3_MPPAR Reserved 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCB6 N/A 0x03FF_FCB0
PROG4_MPPAR Reserved 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCB6 N/A 0x03FF_FCB0
PROG5_MPPAR Reserved 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCB6 N/A 0x03FF_FCB6
PROG6_MPPAR Reserved 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCB6 N/A 0x03FF_FCB6
PROG7_MPPAR Reserved 0x03FF_FCBF 0x03FF_FCB6 0x03FF_FCB6 N/A 0x03FF_FCB0
PROG8_MPPAR Reserved 0x03FF_FCBF N/A 0x03FF_FCB6 N/A 0x03FF_FCB0
PROG9_MPPAR Reserved 0x03FF_FCBF N/A 0x03FF_FCB6 N/A 0x03FF_FCB6
PROG10_MPPAR Reserved 0x03FF_FCBF N/A 0x03FF_FCB6 N/A 0x03FF_FCB6
PROG11_MPPAR Reserved 0x03FF_FCBF N/A 0x03FF_FCB6 N/A 0x03FF_FCB6
PROG12_MPPAR Reserved 0x03FF_FCBF N/A 0x03FF_FCB6 N/A 0x03FF_FCB0
PROG13_MPPAR Reserved 0x03FF_FCBF N/A 0x03FF_FCB6 N/A 0x03FF_FCB6
PROG14_MPPAR Reserved 0x03FF_FCBF N/A 0x03FF_FCB6 N/A 0x03FF_FCB0
PROG15_MPPAR Reserved 0x03FF_FCBF N/A 0x03FF_FCB6 N/A 0x03FF_FCB6

Table 8-21 MPU12-MPU14 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR) Reset Values

Register MPU12 MPU13 MPU14
PROG0_MPPAR 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF
PROG1_MPPAR 0x03FF_FCBF 0x03FF_FCBF 0x03FF_FCBF
PROG2_MPPAR 0x0000_0000 0x0000_0000 0x0000_0000
PROG3_MPPAR N/A N/A N/A
PROG4_MPPAR N/A N/A N/A
PROG5_MPPAR N/A N/A N/A
PROG6_MPPAR N/A N/A N/A
PROG7_MPPAR N/A N/A N/A
PROG8_MPPAR N/A N/A N/A
PROG9_MPPAR N/A N/A N/A
PROG10_MPPAR N/A N/A N/A
PROG11_MPPAR N/A N/A N/A
PROG12_MPPAR N/A N/A N/A
PROG13_MPPAR N/A N/A N/A
PROG14_MPPAR N/A N/A N/A
PROG15_MPPAR N/A N/A N/A

8.3 Interrupts for 66AK2Hxx

This section discusses the interrupt sources, controller, and topology. Also provided are tables describing the interrupt events.

8.3.1 Interrupt Sources and Interrupt Controller

The CPU interrupts on the 66AK2Hxx device are configured through the C66x CorePac Interrupt Controller. The Interrupt Controller allows for up to 128 system events to be programmed to any of the 12 CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the CorePac) and chip-level events.

Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required as CPU interrupts/exceptions to be routed to the Interrupt Controller as emulation events. In addition, error-class events or infrequently used events are also routed through the system event router to offload the C66x CorePac interrupt selector. This is accomplished through the CorePac Interrupt Controller blocks, CIC[2:0]. This is clocked using CPU/6.

The event controllers consist of simple combination logic to provide additional events to each C66x CorePac, ARM GIC (ARM Generic Interrupt Controller) plus the EDMA3CC. CIC0 has 104 event outputs which provides 20 broadcast events and 18 additional events to each of the C66x CorePacs, 0 through 3. Similarly, CIC1 has 104 event outputs which provides 20 broadcast events and 18 additional events to each of the C66x CorePacs, 4 through 7 (66AK2H12/14 only). CIC2 has 103 event outputs which provides 8, 20, 8, 8, 8, and 16 events to EDMA3CC0, EDMA3CC1, EDMA3C2, EDMA3CC3, EDMA3CC4, and HyperLinks respectively.

The events that are routed to the C66x CorePacs for Advanced Event Triggering (AET) purposes from those EDMA3CC and FSYNC events that are not otherwise provided to each C66x CorePac.

Modules such as CP_MPU, BOOT_CFG, and CP_Tracer have level interrupts and EOI handshaking interface. The EOI value is 0 for CP_MPU, BOOT_CFG, and CP_Tracer.

Figure 8-4 and Figure 8-5 show the 66AK2Hxx interrupt topologies.

66AK2H14 66AK2H12 66AK2H06 Interrupt_Topology_B_D_66AK2H12-14.gif Figure 8-4 66AK2H14/12 Interrupt Topology
66AK2H14 66AK2H12 66AK2H06 Interrupt_Topology_B_D_66AK2H06.gif Figure 8-5 66AK2H06 Interrupt Topology

Table 8-22 shows the mapping of primary events to C66x Corepac.

Table 8-22 System Event Mapping — C66x CorePac Primary Interrupts

EVENT NO. EVENT NAME DESCRIPTION
0 EVT0 Event combiner 0 output
1 EVT1 Event combiner 1 output
2 EVT2 Event combiner 2 output
3 EVT3 Event combiner 3 output
4 TETB_HFULLINTN TETB is half full
5 TETB_FULLINTN TETB is full
6 TETB_ACQINTN TETB Acquisition complete interrupt
7 TETB_OVFLINTN TETB Overflow condition interrupt
8 TETB_UNFLINTN TETB Underflow condition interrupt
9 EMU_DTDMA Emulation interrupt for host scan, DTDMA transfer complete and AET
10 MSMC_MPF_ERRORN Memory protection fault indicators for system master PrivID = 0 (C66x CorePac)
11 Reserved Reserved
12 Reserved Reserved
13 IDMA0 IDMA channel 0 interrupt
14 IDMA1 IDMA channel 1 interrupt
15 SEM_ERRN Semaphore error interrupt
16 SEM_INTN Semaphore interrupt
17 PCIE_INT4_PLUS_N PCIE0 MSI interrupt
18 Reserved Reserved
19 Reserved Reserved
20 SRIO_INTDST16_PLUS_N SRIO interrupt
21 Reserved Reserved
22 Reserved Reserved
23 CIC_OUT35 CIC Interrupt Controller output(1)
24 CIC_2_OUT102 CIC Interrupt Controller output
25 CIC_2_OUT94_PLUS_N(2) CIC Interrupt Controller output
26 CIC_OUT68_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
27 CIC_OUT69_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
28 CIC_OUT70_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
29 CIC_OUT71_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
30 CIC_OUT72_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
31 CIC_OUT73_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
32 CIC_OUT16 CIC Interrupt Controller output(1)
33 CIC_OUT17 CIC Interrupt Controller output(1)
34 CIC_OUT18 CIC Interrupt Controller output(1)
35 CIC_OUT19 CIC Interrupt Controller output(1)
36 CIC_OUT20 CIC Interrupt Controller output(1)
37 CIC_OUT21 CIC Interrupt Controller output(1)
38 CIC_OUT22 CIC Interrupt Controller output(1)
39 CIC_OUT23 CIC Interrupt Controller output(1)
40 CIC_OUT32 CIC Interrupt Controller output(1)
41 CIC_OUT33 CIC Interrupt Controller output(1)
42 CIC_OUT13_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
43 CIC_OUT14_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
44 CIC_OUT15_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
45 CIC_OUT64_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
46 CIC_OUT65_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
47 CIC_OUT66_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
48 QMSS_INTD_1_HIGH_N(2) Navigator 1 accumulated hi-priority interrupt 0
49 QMSS_INTD_1_HIGH_8_PLUS_N(2) Navigator 1 accumulated hi-priority interrupt 8
50 QMSS_INTD_1_HIGH_16_PLUS_N(2) Navigator 1 accumulated hi-priority interrupt 16
51 QMSS_INTD_1_HIGH_24_PLUS_N(2) Navigator 1 accumulated hi-priority interrupt 24
52 QMSS_INTD_2_HIGH_N(2) Navigator 2 accumulated hi-priority interrupt 0
53 QMSS_INTD_2_HIGH_8_PLUS_N(2) Navigator 2 accumulated hi-priority interrupt 8
54 QMSS_INTD_2_HIGH_16_PLUS_N(2) Navigator 2 accumulated hi-priority interrupt 16
55 QMSS_INTD_2_HIGH_24_PLUS_N(2) Navigator 2 accumulated hi-priority interrupt 24
56 CIC_OUT0 CIC Interrupt Controller output(1)
57 CIC_OUT1 CIC Interrupt Controller output(1)
58 CIC_OUT2 CIC Interrupt Controller output(1)
59 CIC_OUT3 CIC Interrupt Controller output(1)
60 CIC_OUT4 CIC Interrupt Controller output(1)
61 CIC_OUT5 CIC Interrupt Controller output(1)
62 CIC_OUT6 CIC Interrupt Controller output(1)
63 CIC_OUT7 CIC Interrupt Controller output(1)
64 TIMER_N_INTL Local timer interrupt low
65 TIMER_N_INTH Local timer interrupt high
66 TIMER_8_INTL Timer interrupt low
67 TIMER_8_INTH Timer interrupt high
68 TIMER_9_INTL Timer interrupt low
69 TIMER_9_INTH Timer interrupt high
70 TIMER_10_INTL Timer interrupt low
71 TIMER_10_INTH Timer interrupt high
72 TIMER_11_INTL Timer interrupt low
73 TIMER_11_INTH Timer interrupt high
74 CIC_OUT8_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
75 CIC_OUT9_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
76 CIC_OUT10_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
77 CIC_OUT11_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
78 TIMER_14_INTL Timer interrupt low
79 TIMER_14_INTH Timer interrupt high
80 TIMER_15_INTL Timer interrupt low
81 TIMER_15_INTH Timer interrupt high
82 GPIO_INT8 Local GPIO interrupt
83 GPIO_INT9 Local GPIO interrupt
84 GPIO_INT10 Local GPIO interrupt
85 GPIO_INT11 Local GPIO interrupt
86 GPIO_INT12 Local GPIO interrupt
87 Reserved Reserved
88 Reserved Reserved
89 Reserved Reserved
90 Reserved Reserved
91 Reserved Reserved
92 Reserved Reserved
93 Reserved Reserved
94 Reserved Reserved
95 CIC_OUT67_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1)
96 INTERR Dropped C66x CorePac interrupt event
97 EMC_IDMAERR Invalid IDMA parameters
98 Reserved Reserved
99 CIC_2_SPECIAL_BROADCAST CIC Interrupt Controller output
100 EFIINT0 EFI interrupt from Side A
101 EFIINT1 EFI interrupt from Side B
102 GPIO_INT13 Local GPIO interrupt
103 GPIO_INT14 Local GPIO interrupt
104 GPIO_INT15 Local GPIO interrupt
105 IPC_GRN Boot CFG
106 GPIO_INTN GPIO interrupt
107 CIC_OUT12_PLUS_16_MUL_N(2) CIC Interrupt Controller output(1)
108 CIC_OUT34 CIC Interrupt Controller output(1)
109 CIC_2_OUT13 CIC Interrupt Controller output
110 MDMAERREVT DMA internal bus error event
111 Reserved Reserved
112 EDMACC_0_4_TC_AET_INT EDMA3CC0_4 AET event
113 PMC_ED Single bit error detected during DMA read
114 EDMACC_1_2_TC_AET_INT EDMA3CC1_2 AET event
115 EDMACC_1_3_TC_AET_INT EDMA3CC3_4 AET event
116 UMC_ED1 Corrected bit error detected
117 UMC_ED2 Uncorrected bit error detected
118 PDC_INT Power down sleep interrupt
119 SYS_CMPA SYS CPU MP fault event
120 PMC_CMPA CPU memory protection fault
121 PMC_DMPA DMA memory protection fault
122 DMC_CMPA CPU memory protection fault
123 DMC_DMPA DMA memory protection fault
124 UMC_CMPA CPU memory protection fault
125 UMC_DMPA DMA memory protection fault
126 EMC_CMPA CPU memory protection fault
127 EMC_BUSERR Bus error interrupt
(1) For C66x CorePac[0-3], this generic primary interrupt comes from CIC0 and for C66x CorePac[4-7], this generic primary interrupt comes from CIC1.
(2) N = core number.

NOTE

Event No. 0 is identical to ARM GIC interrupt ID 0.

Table 8-23 System Event Mapping — ARM CorePac Interrupts

EVENT NO. EVENT NAME DESCRIPTION
0 RSTMUX_INT8 Boot config watchdog timer expiration (timer 16) event for ARM Core 0
1 RSTMUX_INT9 Boot config watchdog timer expiration (timer 17) event for ARM Core 1
2 RSTMUX_INT10 Boot config watchdog timer expiration (timer 18) event for ARM Core 2(1)
3 RSTMUX_INT11 Boot config watchdog timer expiration (timer 19) event for ARM Core 3(1)
4 IPC_GR8 Boot config IPCG
5 IPC_GR9 Boot config IPCG
6 IPC_GR10 Boot config IPCG
7 IPC_GR11 Boot config IPCG
8 SEM_INT8 Semaphore interrupt
9 SEM_INT9 Semaphore interrupt
10 SEM_INT10 Semaphore interrupt
11 SEM_INT11 Semaphore interrupt
12 SEM_ERR8 Semaphore error interrupt
13 SEM_ERR9 Semaphore error interrupt
14 SEM_ERR10 Semaphore error interrupt
15 SEM_ERR11 Semaphore error interrupt
16 MSMC_MPF_ERROR8 Memory protection fault indicators for system master PrivID = 8
17 MSMC_MPF_ERROR9 Memory protection fault indicators for system master PrivID = 9
18 MSMC_MPF_ERROR10 Memory protection fault indicators for system master PrivID = 10
19 MSMC_MPF_ERROR11 Memory protection fault indicators for system master PrivID = 11
20 ARM_NPMUIRQ0 ARM performance monitoring unit interrupt request
21 ARM_NPMUIRQ1 ARM performance monitoring unit interrupt request
22 ARM_NPMUIRQ2 ARM performance monitoring unit interrupt request
23 ARM_NPMUIRQ3 ARM performance monitoring unit interrupt request
24 ARM_NINTERRIRQ ARM internal memory ECC error interrupt request
25 ARM_NAXIERRIRQ ARM bus error interrupt request
26 PCIE_INT0 PCIE legacy INTA interrupt
27 PCIE_INT1 PCIE legacy INTB interrupt
28 PCIE_INT2 PCIE legacy INTC interrupt
29 PCIE_INT3 PCIE legacy INTD interrupt
30 PCIE_INT4 PCIE MSI interrupt
31 PCIE_INT5 PCIE MSI interrupt
32 PCIE_INT6 PCIE MSI interrupt
33 PCIE_INT7 PCIE MSI interrupt
34 PCIE_INT8 PCIE MSI interrupt
35 PCIE_INT9 PCIE MSI interrupt
36 PCIE_INT10 PCIE MSI interrupt
37 PCIE_INT11 PCIE MSI interrupt
38 PCIE_INT12 PCIE error interrupt
39 PCIE_INT13 PCIE power management interrupt
40 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
41 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
42 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
43 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
44 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
45 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
46 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
47 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
48 QMSS_QUE_PEND_8704 Navigator transmit queue pending event for indicated queue
49 QMSS_QUE_PEND_8705 Navigator transmit queue pending event for indicated queue
50 QMSS_QUE_PEND_8706 Navigator transmit queue pending event for indicated queue
51 QMSS_QUE_PEND_8707 Navigator transmit queue pending event for indicated queue
52 QMSS_QUE_PEND_8708 Navigator transmit queue pending event for indicated queue
53 QMSS_QUE_PEND_8709 Navigator transmit queue pending event for indicated queue
54 QMSS_QUE_PEND_8710 Navigator transmit queue pending event for indicated queue
55 QMSS_QUE_PEND_8711 Navigator transmit queue pending event for indicated queue
56 QMSS_QUE_PEND_8712 Navigator transmit queue pending event for indicated queue
57 QMSS_QUE_PEND_8713 Navigator transmit queue pending event for indicated queue
58 QMSS_QUE_PEND_8714 Navigator transmit queue pending event for indicated queue
59 QMSS_QUE_PEND_8715 Navigator transmit queue pending event for indicated queue
60 QMSS_QUE_PEND_8716 Navigator transmit queue pending event for indicated queue
61 QMSS_QUE_PEND_8717 Navigator transmit queue pending event for indicated queue
62 QMSS_QUE_PEND_8718 Navigator transmit queue pending event for indicated queue
63 QMSS_QUE_PEND_8719 Navigator transmit queue pending event for indicated queue
64 QMSS_QUE_PEND_8720 Navigator transmit queue pending event for indicated queue
65 QMSS_QUE_PEND_8721 Navigator transmit queue pending event for indicated queue
66 QMSS_QUE_PEND_8722 Navigator transmit queue pending event for indicated queue
67 QMSS_QUE_PEND_8723 Navigator transmit queue pending event for indicated queue
68 QMSS_QUE_PEND_8724 Navigator transmit queue pending event for indicated queue
69 QMSS_QUE_PEND_8725 Navigator transmit queue pending event for indicated queue
70 QMSS_QUE_PEND_8726 Navigator transmit queue pending event for indicated queue
71 QMSS_QUE_PEND_8727 Navigator transmit queue pending event for indicated queue
72 QMSS_QUE_PEND_8728 Navigator transmit queue pending event for indicated queue
73 QMSS_QUE_PEND_8729 Navigator transmit queue pending event for indicated queue
74 QMSS_QUE_PEND_8730 Navigator transmit queue pending event for indicated queue
75 QMSS_QUE_PEND_8731 Navigator transmit queue pending event for indicated queue
76 QMSS_QUE_PEND_8732 Navigator transmit queue pending event for indicated queue
77 QMSS_QUE_PEND_8733 Navigator transmit queue pending event for indicated queue
78 QMSS_QUE_PEND_8734 Navigator transmit queue pending event for indicated queue
79 QMSS_QUE_PEND_8735 Navigator transmit queue pending event for indicated queue
80 TIMER_0_INTL Timer interrupt low
81 TIMER_0_INTH Timer interrupt high
82 TIMER_1_INTL Timer interrupt low
83 TIMER_1_INTH Timer interrupt high
84 TIMER_2_INTL Timer interrupt low
85 TIMER_2_INTH Timer interrupt high
86 TIMER_3_INTL Timer interrupt low
87 TIMER_3_INTH Timer interrupt high
88 TIMER_4_INTL Timer interrupt low(1)
89 TIMER_4_INTH Timer interrupt high(1)
90 TIMER_5_INTL Timer interrupt low(1)
91 TIMER_5_INTH Timer interrupt high(1)
92 TIMER_6_INTL Timer interrupt low(1)
93 TIMER_6_INTH Timer interrupt high(1)
94 TIMER_7_INTL Timer interrupt low(1)
95 TIMER_7_INTH Timer interrupt high(1)
96 TIMER_8_INTL Timer interrupt low
97 TIMER_8_INTH Timer interrupt high
98 TIMER_9_INTL Timer interrupt low
99 TIMER_9_INTH Timer interrupt high
100 TIMER_10_INTL Timer interrupt low
101 TIMER_10_INTH Timer interrupt high
102 TIMER_11_INTL Timer interrupt low
103 TIMER_11_INTH Timer interrupt high
104 TIMER_12_INTL Timer interrupt low
105 TIMER_12_INTH Timer interrupt high
106 TIMER_13_INTL Timer interrupt low
107 TIMER_13_INTH Timer interrupt high
108 TIMER_14_INTL Timer interrupt low
109 TIMER_14_INTH Timer interrupt high
110 TIMER_15_INTL Timer interrupt low
111 TIMER_15_INTH Timer interrupt high
112 TIMER_16_INTL Timer interrupt low
113 TIMER_16_INTH Timer interrupt high
114 TIMER_17_INTL Timer interrupt low
115 TIMER_17_INTH Timer interrupt high
116 TIMER_18_INTL Timer interrupt low(1)
117 TIMER_18_INTH Timer interrupt high(1)
118 TIMER_19_INTL Timer interrupt low(1)
119 TIMER_19_INTH Timer interrupt high(1)
120 GPIO_INT0 GPIO interrupt
121 GPIO_INT1 GPIO interrupt
122 GPIO_INT2 GPIO interrupt
123 GPIO_INT3 GPIO interrupt
124 GPIO_INT4 GPIO interrupt
125 GPIO_INT5 GPIO interrupt
126 GPIO_INT6 GPIO interrupt
127 GPIO_INT7 GPIO interrupt
128 GPIO_INT8 GPIO interrupt
129 GPIO_INT9 GPIO interrupt
130 GPIO_INT10 GPIO interrupt
131 GPIO_INT11 GPIO interrupt
132 GPIO_INT12 GPIO interrupt
133 GPIO_INT13 GPIO interrupt
134 GPIO_INT14 GPIO interrupt
135 GPIO_INT15 GPIO interrupt
136 GPIO_INT16 GPIO interrupt
137 GPIO_INT17 GPIO interrupt
138 GPIO_INT18 GPIO interrupt
139 GPIO_INT19 GPIO interrupt
140 GPIO_INT20 GPIO interrupt
141 GPIO_INT21 GPIO interrupt
142 GPIO_INT22 GPIO interrupt
143 GPIO_INT23 GPIO interrupt
144 GPIO_INT24 GPIO interrupt
145 GPIO_INT25 GPIO interrupt
146 GPIO_INT26 GPIO interrupt
147 GPIO_INT27 GPIO interrupt
148 GPIO_INT28 GPIO interrupt
149 GPIO_INT29 GPIO interrupt
150 GPIO_INT30 GPIO interrupt
151 GPIO_INT31 GPIO interrupt
152 SRIO_INT00 SRIO interrupt
153 SRIO_INT01 SRIO interrupt
154 SRIO_INT02 SRIO interrupt
155 SRIO_INT03 SRIO interrupt
156 SRIO_INT04 SRIO interrupt
157 SRIO_INT05 SRIO interrupt
158 SRIO_INT06 SRIO interrupt
159 SRIO_INT07 SRIO interrupt
160 SRIO_INT08 SRIO interrupt
161 SRIO_INT09 SRIO interrupt
162 SRIO_INT10 SRIO interrupt
163 SRIO_INT11 SRIO interrupt
164 SRIO_INT12 SRIO interrupt
165 SRIO_INT13 SRIO interrupt
166 SRIO_INT14 SRIO interrupt
167 SRIO_INT15 SRIO interrupt
168 SRIO_INT16 SRIO interrupt
169 SRIO_INT17 SRIO interrupt
170 SRIO_INT18 SRIO interrupt
171 SRIO_INT19 SRIO interrupt
172 SRIO_INT20 SRIO interrupt
173 SRIO_INT21 SRIO interrupt
174 SRIO_INT22 SRIO interrupt
175 SRIO_INT23 SRIO interrupt
176 SRIO_INT_PKTDMA_0 SRIO interrupt for Packet DMA starvation
177 QMSS_INTD_1_PKTDMA_0 Navigator interrupt for Packet DMA starvation
178 QMSS_INTD_1_PKTDMA_1 Navigator interrupt for Packet DMA starvation
179 QMSS_INTD_1_HIGH_0 Navigator hi interrupt
180 QMSS_INTD_1_HIGH_1 Navigator hi interrupt
181 QMSS_INTD_1_HIGH_2 Navigator hi interrupt
182 QMSS_INTD_1_HIGH_3 Navigator hi interrupt
183 QMSS_INTD_1_HIGH_4 Navigator hi interrupt
184 QMSS_INTD_1_HIGH_5 Navigator hi interrupt
185 QMSS_INTD_1_HIGH_6 Navigator hi interrupt
186 QMSS_INTD_1_HIGH_7 Navigator hi interrupt
187 QMSS_INTD_1_HIGH_8 Navigator hi interrupt
188 QMSS_INTD_1_HIGH_9 Navigator hi interrupt
189 QMSS_INTD_1_HIGH_10 Navigator hi interrupt
190 QMSS_INTD_1_HIGH_11 Navigator hi interrupt
191 QMSS_INTD_1_HIGH_12 Navigator hi interrupt
192 QMSS_INTD_1_HIGH_13 Navigator hi interrupt
193 QMSS_INTD_1_HIGH_14 Navigator hi interrupt
194 QMSS_INTD_1_HIGH_15 Navigator hi interrupt
195 QMSS_INTD_1_HIGH_16 Navigator hi interrupt
196 QMSS_INTD_1_HIGH_17 Navigator hi interrupt
197 QMSS_INTD_1_HIGH_18 Navigator hi interrupt
198 QMSS_INTD_1_HIGH_19 Navigator hi interrupt
199 QMSS_INTD_1_HIGH_20 Navigator hi interrupt
200 QMSS_INTD_1_HIGH_21 Navigator hi interrupt
201 QMSS_INTD_1_HIGH_22 Navigator hi interrupt
202 QMSS_INTD_1_HIGH_23 Navigator hi interrupt
203 QMSS_INTD_1_HIGH_24 Navigator hi interrupt
204 QMSS_INTD_1_HIGH_25 Navigator hi interrupt
205 QMSS_INTD_1_HIGH_26 Navigator hi interrupt
206 QMSS_INTD_1_HIGH_27 Navigator hi interrupt
207 QMSS_INTD_1_HIGH_28 Navigator hi interrupt
208 QMSS_INTD_1_HIGH_29 Navigator hi interrupt
209 QMSS_INTD_1_HIGH_30 Navigator hi interrupt
210 QMSS_INTD_1_HIGH_31 Navigator hi interrupt
211 QMSS_INTD_1_LOW_0 Navigator interrupt
212 QMSS_INTD_1_LOW_1 Navigator interrupt
213 QMSS_INTD_1_LOW_2 Navigator interrupt
214 QMSS_INTD_1_LOW_3 Navigator interrupt
215 QMSS_INTD_1_LOW_4 Navigator interrupt
216 QMSS_INTD_1_LOW_5 Navigator interrupt
217 QMSS_INTD_1_LOW_6 Navigator interrupt
218 QMSS_INTD_1_LOW_7 Navigator interrupt
219 QMSS_INTD_1_LOW_8 Navigator interrupt
220 QMSS_INTD_1_LOW_9 Navigator interrupt
221 QMSS_INTD_1_LOW_10 Navigator interrupt
222 QMSS_INTD_1_LOW_11 Navigator interrupt
223 QMSS_INTD_1_LOW_12 Navigator interrupt
224 QMSS_INTD_1_LOW_13 Navigator interrupt
225 QMSS_INTD_1_LOW_14 Navigator interrupt
226 QMSS_INTD_1_LOW_15 Navigator interrupt
227 QMSS_INTD_2_PKTDMA_0 Navigator interrupt for Packet DMA starvation
228 QMSS_INTD_2_PKTDMA_1 Navigator interrupt for Packet DMA starvation
229 QMSS_INTD_2_HIGH_0 Navigator second hi interrupt
230 QMSS_INTD_2_HIGH_1 Navigator second hi interrupt
231 QMSS_INTD_2_HIGH_2 Navigator second hi interrupt
232 QMSS_INTD_2_HIGH_3 Navigator second hi interrupt
233 QMSS_INTD_2_HIGH_4 Navigator second hi interrupt
234 QMSS_INTD_2_HIGH_5 Navigator second hi interrupt
235 QMSS_INTD_2_HIGH_6 Navigator second hi interrupt
236 QMSS_INTD_2_HIGH_7 Navigator second hi interrupt
237 QMSS_INTD_2_HIGH_8 Navigator second hi interrupt
238 QMSS_INTD_2_HIGH_9 Navigator second hi interrupt
239 QMSS_INTD_2_HIGH_10 Navigator second hi interrupt
240 QMSS_INTD_2_HIGH_11 Navigator second hi interrupt
241 QMSS_INTD_2_HIGH_12 Navigator second hi interrupt
242 QMSS_INTD_2_HIGH_13 Navigator second hi interrupt
243 QMSS_INTD_2_HIGH_14 Navigator second hi interrupt
244 QMSS_INTD_2_HIGH_15 Navigator second hi interrupt
245 QMSS_INTD_2_HIGH_16 Navigator second hi interrupt
246 QMSS_INTD_2_HIGH_17 Navigator second hi interrupt
247 QMSS_INTD_2_HIGH_18 Navigator second hi interrupt
248 QMSS_INTD_2_HIGH_19 Navigator second hi interrupt
249 QMSS_INTD_2_HIGH_20 Navigator second hi interrupt
250 QMSS_INTD_2_HIGH_21 Navigator second hi interrupt
251 QMSS_INTD_2_HIGH_22 Navigator second hi interrupt
252 QMSS_INTD_2_HIGH_23 Navigator second hi interrupt
253 QMSS_INTD_2_HIGH_24 Navigator second hi interrupt
254 QMSS_INTD_2_HIGH_25 Navigator second hi interrupt
255 QMSS_INTD_2_HIGH_26 Navigator second hi interrupt
256 QMSS_INTD_2_HIGH_27 Navigator second hi interrupt
257 QMSS_INTD_2_HIGH_28 Navigator second hi interrupt
258 QMSS_INTD_2_HIGH_29 Navigator second hi interrupt
259 QMSS_INTD_2_HIGH_30 Navigator second hi interrupt
260 QMSS_INTD_2_HIGH_31 Navigator second hi interrupt
261 QMSS_INTD_2_LOW_0 Navigator second interrupt
262 QMSS_INTD_2_LOW_1 Navigator second interrupt
263 QMSS_INTD_2_LOW_2 Navigator second interrupt
264 QMSS_INTD_2_LOW_3 Navigator second interrupt
265 QMSS_INTD_2_LOW_4 Navigator second interrupt
266 QMSS_INTD_2_LOW_5 Navigator second interrupt
267 QMSS_INTD_2_LOW_6 Navigator second interrupt
268 QMSS_INTD_2_LOW_7 Navigator second interrupt
269 QMSS_INTD_2_LOW_8 Navigator second interrupt
270 QMSS_INTD_2_LOW_9 Navigator second interrupt
271 QMSS_INTD_2_LOW_10 Navigator second interrupt
272 QMSS_INTD_2_LOW_11 Navigator second interrupt
273 QMSS_INTD_2_LOW_12 Navigator second interrupt
274 QMSS_INTD_2_LOW_13 Navigator second interrupt
275 QMSS_INTD_2_LOW_14 Navigator second interrupt
276 QMSS_INTD_2_LOW_15 Navigator second interrupt
277 UART_0_UARTINT UART0 interrupt
278 UART_0_URXEVT UART0 receive event
279 UART_0_UTXEVT UART0 transmit event
280 UART_1_UARTINT UART1 interrupt
281 UART_1_URXEVT UART1 receive event
282 UART_1_UTXEVT UART1 transmit event
283 I2C_0_INT I2C interrupt
284 I2C_0_REVT I2C receive event
285 I2C_0_XEVT I2C transmit event
286 I2C_1_INT I2C interrupt
287 I2C_1_REVT I2C receive event
288 I2C_1_XEVT I2C transmit event
289 I2C_2_INT I2C interrupt
290 I2C_2_REVT I2C receive event
291 I2C_2_XEVT I2C transmit event
292 SPI_0_INT0 SPI interrupt
293 SPI_0_INT1 SPI interrupt
294 SPI_0_XEVT SPI DMA TX event
295 SPI_0_REVT SPI DMA RX event
296 SPI_1_INT0 SPI interrupt
297 SPI_1_INT1 SPI interrupt
298 SPI_1_XEVT SPI DMA TX event
299 SPI_1_REVT SPI DMA RX event
300 SPI_2_INT0 SPI interrupt
301 SPI_2_INT1 SPI interrupt
302 SPI_2_XEVT SPI DMA TX event
303 SPI_2_REVT SPI DMA RX event
304 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
305 DBGTBR_ACQCOMP Debug trace buffer (TBR) Acquisition has been completed
306 ARM_TBR_DMA ARM trace buffer (TBR) DMA event
307 ARM_TBR_ACQ ARM trace buffer (TBR) Acquisition has been completed
308 NETCP_MDIO_LINK_INT0 Packet Accelerator subsystem MDIO interrupt
309 NETCP_MDIO_LINK_INT1 Packet Accelerator subsystem MDIO interrupt
310 NETCP_MDIO_USER_INT0 Packet Accelerator subsystem MDIO interrupt
311 NETCP_MDIO_USER_INT1 Packet Accelerator subsystem MDIO interrupt
312 NETCP_MISC_INT Packet Accelerator subsystem MDIO interrupt
313 NETCP_PKTDMA_INT0 Packet Accelerator Packet DMA starvation interrupt
314 EDMACC_0_GINT EDMA3CC0 global completion interrupt
315 EDMACC_0_TC_0_INT EDMA3CC0 individual completion interrupt
316 EDMACC_0_TC_1_INT EDMA3CC0 individual completion interrupt
317 EDMACC_0_TC_2_INT EDMA3CC0 individual completion interrupt
318 EDMACC_0_TC_3_INT EDMA3CC0 individual completion interrupt
319 EDMACC_0_TC_4_INT EDMA3CC0 individual completion interrupt
320 EDMACC_0_TC_5_INT EDMA3CC0 individual completion interrupt
321 EDMACC_0_TC_6_INT EDMA3CC0 individual completion interrupt
322 EDMACC_0_TC_7_INT EDMA3CC0 individual completion interrupt
323 EDMACC_1_GINT EDMA3CC1 global completion interrupt
324 EDMACC_1_TC_0_INT EDMA3CC1 individual completion interrupt
325 EDMACC_1_TC_1_INT EDMA3CC1 individual completion interrupt
326 EDMACC_1_TC_2_INT EDMA3CC1 individual completion interrupt
327 EDMACC_1_TC_3_INT EDMA3CC1 individual completion interrupt
328 EDMACC_1_TC_4_INT EDMA3CC1 individual completion interrupt
329 EDMACC_1_TC_5_INT EDMA3CC1 individual completion interrupt
330 EDMACC_1_TC_6_INT EDMA3CC1 individual completion interrupt
331 EDMACC_1_TC_7_INT EDMA3CC1 individual completion interrupt
332 EDMACC_2_GINT EDMA3CC2 global completion interrupt
333 EDMACC_2_TC_0_INT EDMA3CC2 individual completion interrupt
334 EDMACC_2_TC_1_INT EDMA3CC2 individual completion interrupt
335 EDMACC_2_TC_2_INT EDMA3CC2 individual completion interrupt
336 EDMACC_2_TC_3_INT EDMA3CC2 individual completion interrupt
337 EDMACC_2_TC_4_INT EDMA3CC2 individual completion interrupt
338 EDMACC_2_TC_5_INT EDMA3CC2 individual completion interrupt
339 EDMACC_2_TC_6_INT EDMA3CC2 individual completion interrupt
340 EDMACC_2_TC_7_INT EDMA3CC2 individual completion interrupt
341 EDMACC_3_GINT EDMA3CC3 global completion interrupt
342 EDMACC_3_TC_0_INT EDMA3CC3 individual completion interrupt
343 EDMACC_3_TC_1_INT EDMA3CC3 individual completion interrupt
344 EDMACC_3_TC_2_INT EDMA3CC3 individual completion interrupt
345 EDMACC_3_TC_3_INT EDMA3CC3 individual completion interrupt
346 EDMACC_3_TC_4_INT EDMA3CC3 individual completion interrupt
347 EDMACC_3_TC_5_INT EDMA3CC3 individual completion interrupt
348 EDMACC_3_TC_6_INT EDMA3CC3 individual completion interrupt
349 EDMACC_3_TC_7_INT EDMA3CC3 individual completion interrupt
350 EDMACC_4_GINT EDMA3CC4 global completion interrupt
351 EDMACC_4_TC_0_INT EDMA3CC4 individual completion interrupt
352 EDMACC_4_TC_1_INT EDMA3CC4 individual completion interrupt
353 EDMACC_4_TC_2_INT EDMA3CC4 individual completion interrupt
354 EDMACC_4_TC_3_INT EDMA3CC4 individual completion interrupt
355 EDMACC_4_TC_4_INT EDMA3CC4 individual completion interrupt
356 EDMACC_4_TC_5_INT EDMA3CC4 individual completion interrupt
357 EDMACC_4_TC_6_INT EDMA3CC4 individual completion interrupt
358 EDMACC_4_TC_7_INT EDMA3CC4 individual completion interrupt
359 SR_0_PO_VCON_SMPSERR_INT SmartReflex SMPS Error interrupt
360 SR_0_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
361 SR_0_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
362 SR_0_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
363 SR_0_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
364 SR_0_VPNOSMPSACK SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval
365 SR_0_VPEQVALUE SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
366 SR_0_VPMAXVDD SmartReflex The new voltage required is equal to or greater than MaxVdd
367 SR_0_VPMINVDD SmartReflex The new voltage required is equal to or less than MinVdd
368 SR_0_VPINIDLE SmartReflex. Indicating that the FSM of voltage processor is in idle
369 SR_0_VPOPPCHANGEDONE SmartReflex Indicating that the average frequency error is within the desired limit
370 SR_0_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
371 SR_0_SR_TEMPSENSOR SmartReflex temperature threshold crossing interrupt
372 SR_0_SR_TIMERINT SmartReflex internal timer expiration interrupt
373 SR_1_PO_VCON_SMPSERR_INT SmartReflex SMPS Error interrupt
374 SR_1_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
375 SR_1_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
376 SR_1_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
377 SR_1_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
378 SR_1_VPNOSMPSACK SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval
379 SR_1_VPEQVALUE SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
380 SR_1_VPMAXVDD SmartReflex The new voltage required is equal to or greater than MaxVdd
381 SR_1_VPMINVDD SmartReflex The new voltage required is equal to or less than MinVdd
382 SR_1_VPINIDLE SmartReflex. Indicating that the FSM of voltage processor is in idle
383 SR_1_VPOPPCHANGEDONE SmartReflex Indicating that the average frequency error is within the desired limit
384 SR_1_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
385 SR_1_SR_TEMPSENSOR SmartReflex temperature threshold crossing interrupt
386 SR_1_SR_TIMERINT SmartReflex internal timer expiration interrupt
387 HyperLink_0_INT HyperLink 0 interrupt
388 HyperLink_1_INT HyperLink 1 interrupt
389 ARM_NCTIIRQ0 ARM cross trigger (CTI) IRQ interrupt
390 ARM_NCTIIRQ1 ARM cross trigger (CTI) IRQ interrupt
391 ARM_NCTIIRQ2 ARM cross trigger (CTI) IRQ interrupt
392 ARM_NCTIIRQ3 ARM cross trigger (CTI) IRQ interrupt
393 USB_INT00 USB event ring 0 interrupt
394 USB_INT01 USB event ring 1 interrupt
395 USB_INT02 USB event ring 2 interrupt
396 USB_INT03 USB event ring 3 interrupt
397 USB_INT04 USB event ring 4 interrupt
398 USB_OABSINT USB OABS interrupt
399 USB_MISCINT USB miscellaneous interrupt
400 Reserved Reserved
401 Reserved Reserved
402 10GbE_LINK_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
403 10GbE_USER_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
404 10GbE_LINK_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
405 10GbE_USER_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
406 10GbE_MISC_INT 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
407 10GbE_INT_PKTDMA_0 10 Gigabit Ethernet Packet DMA starvation interrupt (66AK2H14 only)
408 Reserved Reserved
409 Reserved Reserved
410 Reserved Reserved
411 Reserved Reserved
412 Reserved Reserved
413 Reserved Reserved
414 Reserved Reserved
415 Reserved Reserved
416 Reserved Reserved
417 Reserved Reserved
418 Reserved Reserved
419 Reserved Reserved
420 Reserved Reserved
421 Reserved Reserved
422 Reserved Reserved
423 Reserved Reserved
424 Reserved Reserved
425 Reserved Reserved
426 Reserved Reserved
427 Reserved Reserved
428 Reserved Reserved
429 Reserved Reserved
430 Reserved Reserved
431 Reserved Reserved
432 Reserved Reserved
433 Reserved Reserved
434 Reserved Reserved
435 Reserved Reserved
436 Reserved Reserved
437 Reserved Reserved
438 Reserved Reserved
439 Reserved Reserved
440 Reserved Reserved
441 Reserved Reserved
442 Reserved Reserved
443 Reserved Reserved
444 Reserved Reserved
445 Reserved Reserved
446 Reserved Reserved
447 Reserved Reserved
448 CIC_2_OUT29 CIC2 interrupt
449 CIC_2_OUT30 CIC2 interrupt
450 CIC_2_OUT31 CIC2 interrupt
451 CIC_2_OUT32 CIC2 interrupt
452 CIC_2_OUT33 CIC2 interrupt
453 CIC_2_OUT34 CIC2 interrupt
454 CIC_2_OUT35 CIC2 interrupt
455 CIC_2_OUT36 CIC2 interrupt
456 CIC_2_OUT37 CIC2 interrupt
457 CIC_2_OUT38 CIC2 interrupt
458 CIC_2_OUT39 CIC2 interrupt
459 CIC_2_OUT40 CIC2 interrupt
460 CIC_2_OUT41 CIC2 interrupt
461 CIC_2_OUT42 CIC2 interrupt
462 CIC_2_OUT43 CIC2 interrupt
463 CIC_2_OUT44 CIC2 interrupt
464 CIC_2_OUT45 CIC2 interrupt
465 CIC_2_OUT46 CIC2 interrupt
466 CIC_2_OUT47 CIC2 interrupt
467 CIC_2_OUT18 CIC2 interrupt
468 CIC_2_OUT19 CIC2 interrupt
469 CIC_2_OUT22 CIC2 interrupt
470 CIC_2_OUT23 CIC2 interrupt
471 CIC_2_OUT50 CIC2 interrupt
472 CIC_2_OUT51 CIC2 interrupt
473 CIC_2_OUT66 CIC2 interrupt
474 CIC_2_OUT67 CIC2 interrupt
475 CIC_2_OUT88 CIC2 interrupt
476 CIC_2_OUT89 CIC2 interrupt
477 CIC_2_OUT90 CIC2 interrupt
478 CIC_2_OUT91 CIC2 interrupt
479 CIC_2_OUT92 CIC2 interrupt
(1) 66AK2H12/14 only.

Table 8-24, Table 8-25, and Table 8-26 list the C66x CorePac Secondary interrupt inputs.

Table 8-24 CIC0 Event Inputs — C66x CorePac Secondary Interrupts

EVENT NO. EVENT NAME DESCRIPTION
0 EDMACC_1_ERRINT EDMA3CC1 error interrupt
1 EDMACC_1_MPINT EDMA3CC1 memory protection interrupt
2 EDMACC_1_TC_0_ERRINT EDMA3CC1 TPTC0 error interrupt
3 EDMACC_1_TC_1_ERRINT EDMA3CC1 TPTC1 error interrupt
4 EDMACC_1_TC_2_ERRINT EDMA3CC1 TPTC2 error interrupt
5 EDMACC_1_TC_3_ERRINT EDMA3CC1 TPTC3 error interrupt
6 EDMACC_1_GINT EDMA3CC1 GINT
7 Reserved Reserved
8 EDMACC_1_TC_0_INT EDMA3CC1 individual completion interrupt
9 EDMACC_1_TC_1_INT EDMA3CC1 individual completion interrupt
10 EDMACC_1_TC_2_INT EDMA3CC1 individual completion interrupt
11 EDMACC_1_TC_3_INT EDMA3CC1 individual completion interrupt
12 EDMACC_1_TC_4_INT EDMA3CC1 individual completion interrupt
13 EDMACC_1_TC_5_INT EDMA3CC1 individual completion interrupt
14 EDMACC_1_TC_6_INT EDMA3CC1 individual completion interrupt
15 EDMACC_1_TC_7_INT EDMA3CC1 individual completion interrupt
16 EDMACC_2_ERRINT EDMA3CC2 error interrupt
17 EDMACC_2_MPINT EDMA3CC2 memory protection interrupt
18 EDMACC_2_TC_0_ERRINT EDMA3CC2 TPTC0 error interrupt
19 EDMACC_2_TC_1_ERRINT EDMA3CC2 TPTC1 error interrupt
20 EDMACC_2_TC_2_ERRINT EDMA3CC2 TPTC2 error interrupt
21 EDMACC_2_TC_3_ERRINT EDMA3CC2 TPTC3 error interrupt
22 EDMACC_2_GINT EDMA3CC2 GINT
23 Reserved Reserved
24 EDMACC_2_TC_0_INT EDMA3CC2 individual completion interrupt
25 EDMACC_2_TC_1_INT EDMA3CC2 individual completion interrupt
26 EDMACC_2_TC_2_INT EDMA3CC2 individual completion interrupt
27 EDMACC_2_TC_3_INT EDMA3CC2 individual completion interrupt
28 EDMACC_2_TC_4_INT EDMA3CC2 individual completion interrupt
29 EDMACC_2_TC_5_INT EDMA3CC2 individual completion interrupt
30 EDMACC_2_TC_6_INT EDMA3CC2 individual completion interrupt
31 EDMACC_2_TC_7_INT EDMA3CC2 individual completion interrupt
32 EDMACC_0_ERRINT EDMA3CC0 error interrupt
33 EDMACC_0_MPINT EDMA3CC0 memory protection interrupt
34 EDMACC_0_TC_0_ERRINT EDMA3CC0 TPTC0 error interrupt
35 EDMACC_0_TC_1_ERRINT EDMA3CC0 TPTC1 error interrupt
36 EDMACC_0_GINT EDMA3CC0 global completion interrupt
37 Reserved Reserved
38 EDMACC_0_TC_0_INT EDMA3CC0 individual completion interrupt
39 EDMACC_0_TC_1_INT EDMA3CC0 individual completion interrupt
40 EDMACC_0_TC_2_INT EDMA3CC0 individual completion interrupt
41 EDMACC_0_TC_3_INT EDMA3CC0 individual completion interrupt
42 EDMACC_0_TC_4_INT EDMA3CC0 individual completion interrupt
43 EDMACC_0_TC_5_INT EDMA3CC0 individual completion interrupt
44 EDMACC_0_TC_6_INT EDMA3CC0 individual completion interrupt
45 EDMACC_0_TC_7_INT EDMA3CC0 individual completion interrupt
46 Reserved Reserved
47 QMSS_QUE_PEND_652 Navigator transmit queue pending event for indicated queue
48 PCIE_INT12 PCIE protocol error interrupt
49 PCIE_INT13 PCIE power management interrupt
50 PCIE_INT0 PCIE legacy INTA interrupt
51 PCIE_INT1 PCIE legacy INTB interrupt
52 PCIE_INT2 PCIE legacy INTC interrupt
53 PCIE_INT3 PCIE legacy INTD interrupt
54 SPI_0_INT0 SPI0 interrupt0
55 SPI_0_INT1 SPI0 interrupt1
56 SPI_0_XEVT SPI0 transmit event
57 SPI_0_REVT SPI0 receive event
58 I2C_0_INT I2C0 interrupt
59 I2C_0_REVT I2C0 receive event
60 I2C_0_XEVT I2C0 transmit event
61 Reserved Reserved
62 Reserved Reserved
63 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
64 MPU_12_INT MPU12 addressing violation interrupt and protection violation interrupt
65 DBGTBR_ACQCOMP Debug trace buffer (TBR) acquisition has been completed
66 MPU_13_INT MPU13 addressing violation interrupt and protection violation interrupt
67 MPU_14_INT MPU14 addressing violation interrupt and protection violation interrupt
68 NETCP_MDIO_LINK_INT0 Packet Accelerator 0 subsystem MDIO interrupt
69 NETCP_MDIO_LINK_INT1 Packet Accelerator 0 subsystem MDIO interrupt
70 NETCP_MDIO_USER_INT0 Packet Accelerator 0 subsystem MDIO interrupt
71 NETCP_MDIO_USER_INT1 Packet Accelerator 0 subsystem MDIO interrupt
72 NETCP_MISC_INT Packet Accelerator 0 subsystem misc interrupt
73 TRACER_CORE_0_INT Tracer sliding time window interrupt for DSP0 L2
74 TRACER_CORE_1_INT Tracer sliding time window interrupt for DSP1 L2
75 TRACER_CORE_2_INT Tracer sliding time window interrupt for DSP2 L2
76 TRACER_CORE_3_INT Tracer sliding time window interrupt for DSP3 L2
77 TRACER_DDR_INT Tracer sliding time window interrupt for MSMC-DDR3A
78 TRACER_MSMC_0_INT Tracer sliding time window interrupt for MSMC SRAM bank0
79 TRACER_MSMC_1_INT Tracer sliding time window interrupt for MSMC SRAM bank1
80 TRACER_MSMC_2_INT Tracer sliding time window interrupt for MSMC SRAM bank2
81 TRACER_MSMC_3_INT Tracer sliding time window interrupt for MSMC SRAM bank3
82 TRACER_CFG_INT Tracer sliding time window interrupt for CFG0 TeraNet
83 TRACER_QMSS_QM_CFG1_INT Tracer sliding time window interrupt for Navigator CFG1 slave port
84 TRACER_QMSS_DMA_INT Tracer sliding time window interrupt for Navigator DMA internal bus slave port
85 TRACER_SEM_INT Tracer sliding time window interrupt for Semaphore
86 PSC_ALLINT Power & Sleep Controller interrupt
87 MSMC_SCRUB_CERROR Correctable (1-bit) soft error detected during scrub cycle
88 BOOTCFG_INT Chip-level MMR Error Register
89 SR_0_PO_VCON_SMPSERR_INT SmartReflex SMPS error interrupt
90 MPU_0_INT MPU0 addressing violation interrupt and protection violation interrupt
91 QMSS_QUE_PEND_653 Navigator transmit queue pending event for indicated queue
92 MPU_1_INT MPU1 addressing violation interrupt and protection violation interrupt.
93 QMSS_QUE_PEND_654 Navigator transmit queue pending event for indicated queue
94 MPU_2_INT MPU2 addressing violation interrupt and protection violation interrupt.
95 QMSS_QUE_PEND_655 Navigator transmit queue pending event for indicated queue
96 MPU_3_INT MPU3 addressing violation interrupt and protection violation interrupt.
97 QMSS_QUE_PEND_656 Navigator transmit queue pending event for indicated queue
98 MSMC_DEDC_CERROR Correctable (1-bit) soft error detected on SRAM read
99 MSMC_DEDC_NC_ERROR Noncorrectable (2-bit) soft error detected on SRAM read
100 MSMC_SCRUB_NC_ERROR Noncorrectable (2-bit) soft error detected during scrub cycle
101 MSMC_MPF_ERROR0 Memory protection fault indicators for system master PrivID = 0
102 MSMC_MPF_ERROR8 Memory protection fault indicators for system master PrivID = 8
103 MSMC_MPF_ERROR9 Memory protection fault indicators for system master PrivID = 9
104 MSMC_MPF_ERROR10 Memory protection fault indicators for system master PrivID = 10
105 MSMC_MPF_ERROR11 Memory protection fault indicators for system master PrivID = 11
106 MSMC_MPF_ERROR12 Memory protection fault indicators for system master PrivID = 12
107 MSMC_MPF_ERROR13 Memory protection fault indicators for system master PrivID = 13
108 MSMC_MPF_ERROR14 Memory protection fault indicators for system master PrivID = 14
109 MSMC_MPF_ERROR15 Memory protection fault indicators for system master PrivID = 15
110 DDR3_0_ERR DDR3A_EMIF error interrupt
111 HYPERLINK_0_INT HyperLink 0 interrupt
112 SRIO_INTDST0 SRIO interrupt
113 SRIO_INTDST1 SRIO interrupt
114 SRIO_INTDST2 SRIO interrupt
115 SRIO_INTDST3 SRIO interrupt
116 SRIO_INTDST4 SRIO interrupt
117 SRIO_INTDST5 SRIO interrupt
118 SRIO_INTDST6 SRIO interrupt
119 SRIO_INTDST7 SRIO interrupt
120 SRIO_INTDST8 SRIO interrupt
121 SRIO_INTDST9 SRIO interrupt
122 SRIO_INTDST10 SRIO interrupt
123 SRIO_INTDST11 SRIO interrupt
124 SRIO_INTDST12 SRIO interrupt
125 SRIO_INTDST13 SRIO interrupt
126 SRIO_INTDST14 SRIO interrupt
127 SRIO_INTDST15 SRIO interrupt
128 AEMIF_EASYNCERR Asynchronous EMIF16 error interrupt
129 TRACER_CORE_4_INT Tracer sliding time window interrupt for DSP4 L2
130 TRACER_CORE_5_INT Tracer sliding time window interrupt for DSP5 L2
131 TRACER_CORE_6_INT Tracer sliding time window interrupt for DSP6 L2
132 TRACER_CORE_7_INT Tracer sliding time window interrupt for DSP7 L2
133 QMSS_INTD_1_PKTDMA_0 Navigator interrupt for Packet DMA starvation
134 QMSS_INTD_1_PKTDMA_1 Navigator interrupt for Packet DMA starvation
135 SRIO_INT_PKTDMA_0 IPC interrupt generation
136 NETCP_PKTDMA_INT0 Packet Accelerator0 Packet DMA starvation interrupt
137 SR_0_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
138 SR_0_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
139 SR_0_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
140 SR_0_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
141 SR_0_VPNOSMPSACK SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval
142 SR_0_VPEQVALUE SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
143 SR_0_VPMAXVDD SmartReflex. The new voltage required is equal to or greater than MaxVdd
144 SR_0_VPMINVDD SmartReflex. The new voltage required is equal to or less than MinVdd
145 SR_0_VPINIDLE SmartReflex indicating that the FSM of voltage processor is in idle
146 SR_0_VPOPPCHANGEDONE SmartReflex indicating that the average frequency error is within the desired limit
147 Reserved Reserved
148 UART_0_UARTINT UART0 interrupt
149 UART_0_URXEVT UART0 receive event
150 UART_0_UTXEVT UART0 transmit event
151 QMSS_QUE_PEND_657 Navigator transmit queue pending event for indicated queue
152 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
153 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
154 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
155 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
156 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
157 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
158 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
159 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
160 SR_0_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
161 ARM_TBR_DMA ARM trace buffer (TBR) DMA event
162 ARM_TBR_ACQ ARM trace buffer (TBR) acquisition has been completed
163 ARM_NINTERRIRQ ARM internal memory ECC error interrupt request
164 ARM_NAXIERRIRQ ARM bus error interrupt request
165 SR_0_SR_TEMPSENSOR SmartReflex temperature threshold crossing interrupt
166 SR_0_SR_TIMERINT SmartReflex internal timer expiration interrupt
167 Reserved Reserved
168 Reserved Reserved
169 Reserved Reserved
170 Reserved Reserved
171 Reserved Reserved
172 Reserved Reserved
173 Reserved Reserved
174 Reserved Reserved
175 TIMER_7_INTL Timer interrupt low(1)
176 TIMER_7_INTH Timer interrupt high(1)
177 TIMER_6_INTL Timer interrupt low(1)
178 TIMER_6_INTH Timer interrupt high(1)
179 TIMER_5_INTL Timer interrupt low(1)
180 TIMER_5_INTH Timer interrupt high(1)
181 TIMER_4_INTL Timer interrupt low(1)
182 TIMER_4_INTH Timer interrupt high(1)
183 TIMER_3_INTL Timer interrupt low
184 TIMER_3_INTH Timer interrupt high
185 TIMER_2_INTL Timer interrupt low
186 TIMER_2_INTH Timer interrupt high
187 TIMER_1_INTL Timer interrupt low
188 TIMER_1_INTH Timer interrupt high
189 TIMER_0_INTL Timer interrupt low
190 TIMER_0_INTH Timer interrupt high
191 Reserved Reserved
192 Reserved Reserved
193 Reserved Reserved
194 Reserved Reserved
195 Reserved Reserved
196 Reserved Reserved
197 Reserved Reserved
198 Reserved Reserved
199 Reserved Reserved
200 Reserved Reserved
201 Reserved Reserved
202 Reserved Reserved
203 Reserved Reserved
204 Reserved Reserved
205 Reserved Reserved
206 Reserved Reserved
207 EDMACC_4_ERRINT EDMA3CC4 error interrupt
208 EDMACC_4_MPINT EDMA3CC4 memory protection interrupt
209 EDMACC_4_TC_0_ERRINT EDMA3CC4 TPTC0 error interrupt
210 EDMACC_4_TC_1_ERRINT EDMA3CC4 TPTC1 error interrupt
211 EDMACC_4_GINT EDMA3CC4 GINT
212 EDMACC_4_TC_0_INT EDMA3CC4 individual completion interrupt
213 EDMACC_4_TC_1_INT EDMA3CC4 individual completion interrupt
214 EDMACC_4_TC_2_INT EDMA3CC4 individual completion interrupt
215 EDMACC_4_TC_3_INT EDMA3CC4 individual completion interrupt
216 EDMACC_4_TC_4_INT EDMA3CC4 individual completion interrupt
217 EDMACC_4_TC_5_INT EDMA3CC4 individual completion interrupt
218 EDMACC_4_TC_6_INT EDMA3CC4 individual completion interrupt
219 EDMACC_4_TC_7_INT EDMA3CC4 individual completion interrupt
220 EDMACC_3_ERRINT EDMA3CC3 error interrupt
221 EDMACC_3_MPINT EDMA3CC3 memory protection interrupt
222 EDMACC_3_TC_0_ERRINT EDMA3CC3 TPTC0 error interrupt
223 EDMACC_3_TC_1_ERRINT EDMA3CC3 TPTC1 error interrupt
224 EDMACC_3_GINT EDMA3CC3 GINT
225 EDMACC_3_TC_0_INT EDMA3CC3 individual completion interrupt
226 EDMACC_3_TC_1_INT EDMA3CC3 individual completion interrupt
227 EDMACC_3_TC_2_INT EDMA3CC3 individual completion interrupt
228 EDMACC_3_TC_3_INT EDMA3CC3 individual completion interrupt
229 EDMACC_3_TC_4_INT EDMA3CC3 individual completion interrupt
230 EDMACC_3_TC_5_INT EDMA3CC3 individual completion interrupt
231 EDMACC_3_TC_6_INT EDMA3CC3 individual completion interrupt
232 EDMACC_3_TC_7_INT EDMA3CC3 individual completion interrupt
233 UART_1_UARTINT UART1 interrupt
234 UART_1_URXEVT UART1 receive event
235 UART_1_UTXEVT UART1 transmit event
236 I2C_1_INT I2C1 interrupt
237 I2C_1_REVT I2C1 receive event
238 I2C_1_XEVT I2C1 transmit event
239 SPI_1_INT0 SPI1 interrupt0
240 SPI_1_INT1 SPI1 interrupt1
241 SPI_1_XEVT SPI1 transmit event
242 SPI_1_REVT SPI1 receive event
243 MPU_5_INT MPU5 addressing violation interrupt and protection violation interrupt
244 MPU_8_INT MPU8 addressing violation interrupt and protection violation interrupt
245 MPU_9_INT MPU9 addressing violation interrupt and protection violation interrupt
246 MPU_11_INT MPU11 addressing violation interrupt and protection violation interrupt
247 MPU_4_INT MPU4 addressing violation interrupt and protection violation interrupt
248 MPU_6_INT MPU6 addressing violation interrupt and protection violation interrupt
249 MPU_7_INT MPU7 addressing violation interrupt and protection violation interrupt
250 MPU_10_INT MPU10 addressing violation interrupt and protection violation interrupt
251 SPI_2_INT0 SPI2 interrupt0
252 SPI_2_INT1 SPI2 interrupt1
253 SPI_2_XEVT SPI2 transmit event
254 SPI_2_REVT SPI2 receive event
255 I2C_2_INT I2C2 interrupt
256 I2C_2_REVT I2C2 receive event
257 I2C_2_XEVT I2C2 transmit event
258 Reserved Reserved
259 Reserved Reserved
260 Reserved Reserved
261 Reserved Reserved
262 Reserved Reserved
263 Reserved Reserved
264 Reserved Reserved
265 Reserved Reserved
266 Reserved Reserved
267 Reserved Reserved
268 Reserved Reserved
269 Reserved Reserved
270 Reserved Reserved
271 Reserved Reserved
272 Reserved Reserved
273 Reserved Reserved
274 Reserved Reserved
275 Reserved Reserved
276 Reserved Reserved
277 Reserved Reserved
278 Reserved Reserved
279 Reserved Reserved
280 Reserved Reserved
281 Reserved Reserved
282 Reserved Reserved
283 Reserved Reserved
284 Reserved Reserved
285 Reserved Reserved
286 Reserved Reserved
287 Reserved Reserved
288 Reserved Reserved
289 Reserved Reserved
290 Reserved Reserved
291 Reserved Reserved
292 QMSS_QUE_PEND_666 Navigator transmit queue pending event for indicated queue
293 QMSS_QUE_PEND_667 Navigator transmit queue pending event for indicated queue
294 QMSS_QUE_PEND_668 Navigator transmit queue pending event for indicated queue
295 QMSS_QUE_PEND_669 Navigator transmit queue pending event for indicated queue
296 QMSS_QUE_PEND_670 Navigator transmit queue pending event for indicated queue
297 QMSS_QUE_PEND_671 Navigator transmit queue pending event for indicated queue
298 QMSS_QUE_PEND_8844 Navigator transmit queue pending event for indicated queue
299 QMSS_QUE_PEND_8845 Navigator transmit queue pending event for indicated queue
300 QMSS_QUE_PEND_8846 Navigator transmit queue pending event for indicated queue
301 QMSS_QUE_PEND_8847 Navigator transmit queue pending event for indicated queue
302 QMSS_QUE_PEND_8848 Navigator transmit queue pending event for indicated queue
303 QMSS_QUE_PEND_8849 Navigator transmit queue pending event for indicated queue
304 QMSS_QUE_PEND_8850 Navigator transmit queue pending event for indicated queue
305 QMSS_QUE_PEND_8851 Navigator transmit queue pending event for indicated queue
306 QMSS_QUE_PEND_8852 Navigator transmit queue pending event for indicated queue
307 QMSS_QUE_PEND_8853 Navigator transmit queue pending event for indicated queue
308 QMSS_QUE_PEND_8854 Navigator transmit queue pending event for indicated queue
309 QMSS_QUE_PEND_8855 Navigator transmit queue pending event for indicated queue
310 QMSS_QUE_PEND_8856 Navigator transmit queue pending event for indicated queue
311 QMSS_QUE_PEND_8857 Navigator transmit queue pending event for indicated queue
312 QMSS_QUE_PEND_8858 Navigator transmit queue pending event for indicated queue
313 QMSS_QUE_PEND_8859 Navigator transmit queue pending event for indicated queue
314 QMSS_QUE_PEND_8860 Navigator transmit queue pending event for indicated queue
315 QMSS_QUE_PEND_8861 Navigator transmit queue pending event for indicated queue
316 QMSS_QUE_PEND_8862 Navigator transmit queue pending event for indicated queue
317 QMSS_QUE_PEND_8863 Navigator transmit queue pending event for indicated queue
318 QMSS_INTD_2_PKTDMA_0 Navigator ECC error interrupt
319 QMSS_INTD_2_PKTDMA_1 Navigator ECC error interrupt
320 QMSS_INTD_1_LOW_0 Navigator interrupt low
321 QMSS_INTD_1_LOW_1 Navigator interrupt low
322 QMSS_INTD_1_LOW_2 Navigator interrupt low
323 QMSS_INTD_1_LOW_3 Navigator interrupt low
324 QMSS_INTD_1_LOW_4 Navigator interrupt low
325 QMSS_INTD_1_LOW_5 Navigator interrupt low
326 QMSS_INTD_1_LOW_6 Navigator interrupt low
327 QMSS_INTD_1_LOW_7 Navigator interrupt low
328 QMSS_INTD_1_LOW_8 Navigator interrupt low
329 QMSS_INTD_1_LOW_9 Navigator interrupt low
330 QMSS_INTD_1_LOW_10 Navigator interrupt low
331 QMSS_INTD_1_LOW_11 Navigator interrupt low
332 QMSS_INTD_1_LOW_12 Navigator interrupt low
333 QMSS_INTD_1_LOW_13 Navigator interrupt low
334 QMSS_INTD_1_LOW_14 Navigator interrupt low
335 QMSS_INTD_1_LOW_15 Navigator interrupt low
336 QMSS_INTD_2_LOW_0 Navigator second interrupt low
337 QMSS_INTD_2_LOW_1 Navigator second interrupt low
338 QMSS_INTD_2_LOW_2 Navigator second interrupt low
339 QMSS_INTD_2_LOW_3 Navigator second interrupt low
340 QMSS_INTD_2_LOW_4 Navigator second interrupt low
341 QMSS_INTD_2_LOW_5 Navigator second interrupt low
342 QMSS_INTD_2_LOW_6 Navigator second interrupt low
343 QMSS_INTD_2_LOW_7 Navigator second interrupt low
344 QMSS_INTD_2_LOW_8 Navigator second interrupt low
345 QMSS_INTD_2_LOW_9 Navigator second interrupt low
346 QMSS_INTD_2_LOW_10 Navigator second interrupt low
347 QMSS_INTD_2_LOW_11 Navigator second interrupt low
348 QMSS_INTD_2_LOW_12 Navigator second interrupt low
349 QMSS_INTD_2_LOW_13 Navigator second interrupt low
350 QMSS_INTD_2_LOW_14 Navigator second interrupt low
351 QMSS_INTD_2_LOW_15 Navigator second interrupt low
352 TRACER_EDMACC_0 Tracer sliding time window interrupt for EDMA3CC0
353 TRACER_EDMACC_123_INT Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2 and EDMA3CC3
354 TRACER_CIC_INT Tracer sliding time window interrupt for interrupt controllers (CIC)
355 TRACER_MSMC_4_INT Tracer sliding time window interrupt for MSMC SRAM bank4
356 TRACER_MSMC_5_INT Tracer sliding time window interrupt for MSMC SRAM bank5
357 TRACER_MSMC_6_INT Tracer sliding time window interrupt for MSMC SRAM bank6
358 TRACER_MSMC_7_INT Tracer sliding time window interrupt for MSMC SRAM bank7
359 TRACER_SPI_ROM_EMIF_INT Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules
360 TRACER_QMSS_QM_CFG2_INT Tracer sliding time window interrupt for QM2
361 Reserved Reserved
362 Reserved Reserved
363 TRACER_DDR_1_INT Tracer sliding time window interrupt for DDR3B
364 Reserved Reserved
365 HYPERLINK_1_INT HyperLink 1 interrupt
366 Reserved Reserved
367 Reserved Reserved
368 Reserved Reserved
369 Reserved Reserved
370 Reserved Reserved
371 Reserved Reserved
372 Reserved Reserved
373 Reserved Reserved
374 Reserved Reserved
375 Reserved Reserved
376 Reserved Reserved
377 Reserved Reserved
378 Reserved Reserved
379 Reserved Reserved
380 Reserved Reserved
381 Reserved Reserved
382 Reserved Reserved
383 Reserved Reserved
384 Reserved Reserved
385 Reserved Reserved
386 Reserved Reserved
387 Reserved Reserved
388 Reserved Reserved
389 Reserved Reserved
390 Reserved Reserved
391 Reserved Reserved
392 Reserved Reserved
393 Reserved Reserved
394 Reserved Reserved
395 Reserved Reserved
396 Reserved Reserved
397 Reserved Reserved
398 Reserved Reserved
399 Reserved Reserved
400 Reserved Reserved
401 Reserved Reserved
402 Reserved Reserved
403 Reserved Reserved
404 Reserved Reserved
405 Reserved Reserved
406 Reserved Reserved
407 Reserved Reserved
408 Reserved Reserved
409 Reserved Reserved
410 Reserved Reserved
411 Reserved Reserved
412 Reserved Reserved
413 Reserved Reserved
414 Reserved Reserved
415 Reserved Reserved
416 Reserved Reserved
417 Reserved Reserved
418 Reserved Reserved
419 Reserved Reserved
420 Reserved Reserved
421 Reserved Reserved
422 USB_INT00 USB interrupt
423 USB_INT04 USB interrupt
424 USB_INT05 USB interrupt
425 USB_INT06 USB interrupt
426 USB_INT07 USB interrupt
427 USB_INT08 USB interrupt
428 USB_INT09 USB interrupt
429 USB_INT10 USB interrupt
430 USB_INT11 USB interrupt
431 USB_MISCINT USB miscellaneous interrupt
432 USB_OABSINT USB OABS interrupt
433 TIMER_12_INTL Timer interrupt low
434 TIMER_12_INTH Timer interrupt high
435 TIMER_13_INTL Timer interrupt low
436 TIMER_13_INTH Timer interrupt high
437 TIMER_14_INTL Timer interrupt low
438 TIMER_14_INTH Timer interrupt high
439 TIMER_15_INTL Timer interrupt low
440 TIMER_15_INTH Timer interrupt high
441 TIMER_16_INTL Timer interrupt low
442 TIMER_17_INTL Timer interrupt high
443 TIMER_18_INTL Timer interrupt low(1)
444 TIMER_19_INTL Timer interrupt high(1)
445 DDR3_1_ERR DDR3B_EMIF error interrupt
446 GPIO_INT16 GPIO interrupt
447 GPIO_INT17 GPIO interrupt
448 GPIO_INT18 GPIO interrupt
449 GPIO_INT19 GPIO interrupt
450 GPIO_INT20 GPIO interrupt
451 GPIO_INT21 GPIO interrupt
452 GPIO_INT22 GPIO interrupt
453 GPIO_INT23 GPIO interrupt
454 GPIO_INT24 GPIO interrupt
455 GPIO_INT25 GPIO interrupt
456 GPIO_INT26 GPIO interrupt
457 GPIO_INT27 GPIO interrupt
458 GPIO_INT28 GPIO interrupt
459 GPIO_INT29 GPIO interrupt
460 GPIO_INT30 GPIO interrupt
461 GPIO_INT31 GPIO interrupt
462 SRIO_INTDST16 SRIOI interrupt
463 SRIO_INTDST17 SRIOI interrupt
464 SRIO_INTDST18 SRIOI interrupt
465 SRIO_INTDST19 SRIOI interrupt
466 PCIE_INT4 PCIE MSI interrupt
467 PCIE_INT5 PCIE MSI interrupt
468 PCIE_INT6 PCIE MSI interrupt
469 PCIE_INT7 PCIE MSI interrupt
470 SEM_INT12 Semaphore interrupt
471 SEM_INT13 Semaphore interrupt
472 SEM_ERR12 Semaphore error interrupt
473 SEM_ERR13 Semaphore error interrupt
(1) 66AK2H12/14 only.

Table 8-25 CIC1 Event Inputs — C66x CorePac Secondary Interrupts

EVENT NO. EVENT NAME DESCRIPTION
0 EDMACC_1_ERRINT EDMA3CC1 error interrupt
1 EDMACC_1_MPINT EDMA3CC1 memory protection interrupt
2 EDMACC_1_TC_0_ERRINT EDMA3CC1 TPTC0 error interrupt
3 EDMACC_1_TC_1_ERRINT EDMA3CC1 TPTC1 error interrupt
4 EDMACC_1_TC_2_ERRINT EDMA3CC1 TPTC2 error interrupt
5 EDMACC_1_TC_3_ERRINT EDMA3CC1 TPTC3 error interrupt
6 EDMACC_1_GINT EDMA3CC1 GINT
7 Reserved Reserved
8 EDMACC_1_TC_0_INT EDMA3CC1 individual completion interrupt
9 EDMACC_1_TC_1_INT EDMA3CC1 individual completion interrupt
10 EDMACC_1_TC_2_INT EDMA3CC1 individual completion interrupt
11 EDMACC_1_TC_3_INT EDMA3CC1 individual completion interrupt
12 EDMACC_1_TC_4_INT EDMA3CC1 individual completion interrupt
13 EDMACC_1_TC_5_INT EDMA3CC1 individual completion interrupt
14 EDMACC_1_TC_6_INT EDMA3CC1 individual completion interrupt
15 EDMACC_1_TC_7_INT EDMA3CC1 individual completion interrupt
16 EDMACC_2_ERRINT EDMA3CC2 error interrupt
17 EDMACC_2_MPINT EDMA3CC2 memory protection interrupt
18 EDMACC_2_TC_0_ERRINT EDMA3CC2 TPTC0 error interrupt
19 EDMACC_2_TC_1_ERRINT EDMA3CC2 TPTC1 error interrupt
20 EDMACC_2_TC_2_ERRINT EDMA3CC2 TPTC2 error interrupt
21 EDMACC_2_TC_3_ERRINT EDMA3CC2 TPTC3 error interrupt
22 EDMACC_2_GINT EDMA3CC2 GINT
23 Reserved Reserved
24 EDMACC_2_TC_0_INT EDMA3CC2 individual completion interrupt
25 EDMACC_2_TC_1_INT EDMA3CC2 individual completion interrupt
26 EDMACC_2_TC_2_INT EDMA3CC2 individual completion interrupt
27 EDMACC_2_TC_3_INT EDMA3CC2 individual completion interrupt
28 EDMACC_2_TC_4_INT EDMA3CC2 individual completion interrupt
29 EDMACC_2_TC_5_INT EDMA3CC2 individual completion interrupt
30 EDMACC_2_TC_6_INT EDMA3CC2 individual completion interrupt
31 EDMACC_2_TC_7_INT EDMA3CC2 individual completion interrupt
32 EDMACC_0_ERRINT EDMA3CC0 error interrupt
33 EDMACC_0_MPINT EDMA3CC0 memory protection interrupt
34 EDMACC_0_TC_0_ERRINT EDMA3CC0 TPTC0 error interrupt
35 EDMACC_0_TC_1_ERRINT EDMA3CC0 TPTC1 error interrupt
36 EDMACC_0_GINT EDMA3CC0 GINT
37 Reserved Reserved
38 EDMACC_0_TC_0_INT EDMA3CC0 individual completion interrupt
39 EDMACC_0_TC_1_INT EDMA3CC0 individual completion interrupt
40 EDMACC_0_TC_2_INT EDMA3CC0 individual completion interrupt
41 EDMACC_0_TC_3_INT EDMA3CC0 individual completion interrupt
42 EDMACC_0_TC_4_INT EDMA3CC0 individual completion interrupt
43 EDMACC_0_TC_5_INT EDMA3CC0 individual completion interrupt
44 EDMACC_0_TC_6_INT EDMA3CC0 individual completion interrupt
45 EDMACC_0_TC_7_INT EDMA3CC0 individual completion interrupt
46 Reserved Reserved
47 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
48 PCIE_INT12 PCIE interrupt
49 PCIE_INT13 PCIE interrupt
50 PCIE_INT0 PCIE interrupt
51 PCIE_INT1 PCIE interrupt
52 PCIE_INT2 PCIE interrupt
53 PCIE_INT3 PCIE interrupt
54 SPI_0_INT0 SPI0 interrupt
55 SPI_0_INT1 SPI0 interrupt
56 SPI_0_XEVT SPI0 transmit event
57 SPI_0_REVT SPI0 receive event
58 I2C_0_INT I2C0 interrupt
59 I2C_0_REVT I2C0 receive event
60 I2C_0_XEVT I2C0 transmit event
61 Reserved Reserved
62 Reserved Reserved
63 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
64 MPU_12_INT MPU12 interrupt
65 DBGTBR_ACQCOMP Debug trace buffer (TBR) acquisition has been completed
66 MPU_13_INT MPU13 interrupt
67 MPU_14_INT MPU14 interrupt
68 NETCP_MDIO_LINK_INT0 Packet Accelerator 0 subsystem MDIO interrupt
69 NETCP_MDIO_LINK_INT1 Packet Accelerator 0 subsystem MDIO interrupt
70 NETCP_MDIO_USER_INT0 Packet Accelerator 0 subsystem MDIO interrupt
71 NETCP_MDIO_USER_INT1 Packet Accelerator 0 subsystem MDIO interrupt
72 NETCP_MISC_INT Packet Accelerator 0 subsystem misc interrupt
73 TRACER_CORE_0_INT Tracer sliding time window interrupt for DSP0 L2
74 TRACER_CORE_1_INT Tracer sliding time window interrupt for DSP1 L2
75 TRACER_CORE_2_INT Tracer sliding time window interrupt for DSP2 L2
76 TRACER_CORE_3_INT Tracer sliding time window interrupt for DSP3 L2
77 TRACER_DDR_INT Tracer sliding time window interrupt for MSMC-DDR3A
78 TRACER_MSMC_0_INT Tracer sliding time window interrupt for MSMC SRAM bank0
79 TRACER_MSMC_1_INT Tracer sliding time window interrupt for MSMC SRAM bank1
80 TRACER_MSMC_2_INT Tracer sliding time window interrupt for MSMC SRAM bank2
81 TRACER_MSMC_3_INT Tracer sliding time window interrupt for MSMC SRAM bank3
82 TRACER_CFG_INT Tracer sliding time window interrupt for CFG0 TeraNet
83 TRACER_QMSS_QM_CFG1_INT Tracer sliding time window interrupt for Navigator CFG1 slave port
84 TRACER_QMSS_DMA_INT Tracer sliding time window interrupt for Navigator DMA internal bus slave port
85 TRACER_SEM_INT Tracer sliding time window interrupt for Semaphore
86 PSC_ALLINT Power & Sleep Controller interrupt
87 MSMC_SCRUB_CERROR Correctable (1-bit) soft error detected during scrub cycle
88 BOOTCFG_INT Chip-level MMR Error Register
89 SR_0_PO_VCON_SMPSERR_INT SmartReflex SMPS error interrupt
90 MPU_0_INT MPU0 addressing violation interrupt and protection violation interrupt.
91 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
92 MPU_1_INT MPU1 addressing violation interrupt and protection violation interrupt.
93 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
94 MPU_2_INT MPU2 addressing violation interrupt and protection violation interrupt.
95 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
96 MPU_3_INT MPU3 addressing violation interrupt and protection violation interrupt.
97 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
98 MSMC_DEDC_CERROR Correctable (1-bit) soft error detected on SRAM read
99 MSMC_DEDC_NC_ERROR Noncorrectable (2-bit) soft error detected on SRAM read
100 MSMC_SCRUB_NC_ERROR Noncorrectable (2-bit) soft error detected during scrub cycle
101 Reserved Reserved
102 MSMC_MPF_ERROR8 Memory protection fault indicators for system master PrivID = 8
103 MSMC_MPF_ERROR9 Memory protection fault indicators for system master PrivID = 9
104 MSMC_MPF_ERROR10 Memory protection fault indicators for system master PrivID = 10
105 MSMC_MPF_ERROR11 Memory protection fault indicators for system master PrivID = 11
106 MSMC_MPF_ERROR12 Memory protection fault indicators for system master PrivID = 12
107 MSMC_MPF_ERROR13 Memory protection fault indicators for system master PrivID = 13
108 MSMC_MPF_ERROR14 Memory protection fault indicators for system master PrivID = 14
109 MSMC_MPF_ERROR15 Memory protection fault indicators for system master PrivID = 15
110 DDR3_0_ERR DDR3A_EMIF Error interrupt
111 HYPERLINK_0_INT HyperLink 0 interrupt
112 SRIO_INTDST0 SRIO interrupt
113 SRIO_INTDST1 SRIO interrupt
114 SRIO_INTDST2 SRIO interrupt
115 SRIO_INTDST3 SRIO interrupt
116 SRIO_INTDST4 SRIO interrupt
117 SRIO_INTDST5 SRIO interrupt
118 SRIO_INTDST6 SRIO interrupt
119 SRIO_INTDST7 SRIO interrupt
120 SRIO_INTDST8 SRIO interrupt
121 SRIO_INTDST9 SRIO interrupt
122 SRIO_INTDST10 SRIO interrupt
123 SRIO_INTDST11 SRIO interrupt
124 SRIO_INTDST12 SRIO interrupt
125 SRIO_INTDST13 SRIO interrupt
126 SRIO_INTDST14 SRIO interrupt
127 SRIO_INTDST15 SRIO interrupt
128 AEMIF_EASYNCERR Asynchronous EMIF16 error interrupt
129 TRACER_CORE_4_INT Tracer sliding time window interrupt for DSP4 L2(1)
130 TRACER_CORE_5_INT Tracer sliding time window interrupt for DSP5 L2(1)
131 TRACER_CORE_6_INT Tracer sliding time window interrupt for DSP6 L2(1)
132 TRACER_CORE_7_INT Tracer sliding time window interrupt for DSP7 L2(1)
133 QMSS_INTD_1_PKTDMA_0 Navigator interrupt for Packet DMA starvation
134 QMSS_INTD_1_PKTDMA_1 Navigator interrupt for Packet DMA starvation
135 SRIO_INT_PKTDMA_0 IPC interrupt generation
136 NETCP_PKTDMA_INT0 Packet Accelerator0 Packet DMA starvation interrupt
137 SR_0_SMARTREFLEX_INTREQ0 SmartReflex controller interrupt
138 SR_0_SMARTREFLEX_INTREQ1 SmartReflex controller interrupt
139 SR_0_SMARTREFLEX_INTREQ2 SmartReflex controller interrupt
140 SR_0_SMARTREFLEX_INTREQ3 SmartReflex controller interrupt
141 SR_0_VPNOSMPSACK SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval
142 SR_0_VPEQVALUE SmartReflex SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage
143 SR_0_VPMAXVDD SmartReflex. The new voltage required is equal to or greater than MaxVdd
144 SR_0_VPMINVDD SmartReflex. The new voltage required is equal to or less than MinVdd
145 SR_0_VPINIDLE SmartReflex indicating that the FSM of voltage processor is in idle
146 SR_0_VPOPPCHANGEDONE SmartReflex indicating that the average frequency error is within the desired limit
147 Reserved Reserved
148 UART_0_UARTINT UART0 interrupt
149 UART_0_URXEVT UART0 receive event
150 UART_0_UTXEVT UART0 transmit event
151 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
152 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
153 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
154 QMSS_QUE_PEND_666 Navigator transmit queue pending event for indicated queue
155 QMSS_QUE_PEND_667 Navigator transmit queue pending event for indicated queue
156 QMSS_QUE_PEND_668 Navigator transmit queue pending event for indicated queue
157 QMSS_QUE_PEND_669 Navigator transmit queue pending event for indicated queue
158 QMSS_QUE_PEND_670 Navigator transmit queue pending event for indicated queue
159 QMSS_QUE_PEND_671 Navigator transmit queue pending event for indicated queue
160 SR_0_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
161 ARM_TBR_DMA ARM trace buffer (TBR) DMA event
162 ARM_TBR_ACQ ARM trace buffer (TBR) Acquisition has been completed
163 ARM_NINTERRIRQ ARM internal memory ECC error interrupt request
164 ARM_NAXIERRIRQ ARM bus error interrupt request
165 SR_0_SR_TEMPSENSOR SmartReflex temperature threshold crossing interrupt
166 SR_0_SR_TIMERINT SmartReflex internal timer expiration interrupt
167 Reserved Reserved
168 Reserved Reserved
169 Reserved Reserved
170 Reserved Reserved
171 Reserved Reserved
172 Reserved Reserved
173 Reserved Reserved
174 Reserved Reserved
175 TIMER_7_INTL Timer interrupt low(1)
176 TIMER_7_INTH Timer interrupt high(1)
177 TIMER_6_INTL Timer interrupt low(1)
178 TIMER_6_INTH Timer interrupt high(1)
179 TIMER_5_INTL Timer interrupt low(1)
180 TIMER_5_INTH Timer interrupt high(1)
181 TIMER_4_INTL Timer interrupt low(1)
182 TIMER_4_INTH Timer interrupt high(1)
183 TIMER_3_INTL Timer interrupt low
184 TIMER_3_INTH Timer interrupt high
185 TIMER_2_INTL Timer interrupt low
186 TIMER_2_INTH Timer interrupt high
187 TIMER_1_INTL Timer interrupt low
188 TIMER_1_INTH Timer interrupt high
189 TIMER_0_INTL Timer interrupt low
190 TIMER_0_INTH Timer interrupt high
191 Reserved Reserved
192 Reserved Reserved
193 Reserved Reserved
194 Reserved Reserved
195 Reserved Reserved
196 Reserved Reserved
197 Reserved Reserved
198 Reserved Reserved
199 Reserved Reserved
200 Reserved Reserved
201 Reserved Reserved
202 Reserved Reserved
203 Reserved Reserved
204 Reserved Reserved
205 Reserved Reserved
206 Reserved Reserved
207 EDMACC_4_ERRINT EDMA3CC4 error interrupt
208 EDMACC_4_MPINT EDMA3CC4 memory protection interrupt
209 EDMACC_4_TC_0_ERRINT EDMA3CC4 TPTC0 error interrupt
210 EDMACC_4_TC_1_ERRINT EDMA3CC4 TPTC1 error interrupt
211 EDMACC_4_GINT EDMA3CC4 GINT
212 EDMACC_4_TC_0_INT EDMA3CC4 individual completion interrupt
213 EDMACC_4_TC_1_INT EDMA3CC4 individual completion interrupt
214 EDMACC_4_TC_2_INT EDMA3CC4 individual completion interrupt
215 EDMACC_4_TC_3_INT EDMA3CC4 individual completion interrupt
216 EDMACC_4_TC_4_INT EDMA3CC4 individual completion interrupt
217 EDMACC_4_TC_5_INT EDMA3CC4 individual completion interrupt
218 EDMACC_4_TC_6_INT EDMA3CC4 individual completion interrupt
219 EDMACC_4_TC_7_INT EDMA3CC4 individual completion interrupt
220 EDMACC_3_ERRINT EDMA3CC3 error interrupt
221 EDMACC_3_MPINT EDMA3CC3 memory protection interrupt
222 EDMACC_3_TC_0_ERRINT EDMA3CC3 TPTC0 error interrupt
223 EDMACC_3_TC_1_ERRINT EDMA3CC3 TPTC1 error interrupt
224 EDMACC_3_GINT EDMA3CC3 GINT
225 EDMACC_3_TC_0_INT EDMA3CC3 individual completion interrupt
226 EDMACC_3_TC_1_INT EDMA3CC3 individual completion interrupt
227 EDMACC_3_TC_2_INT EDMA3CC3 individual completion interrupt
228 EDMACC_3_TC_3_INT EDMA3CC3 individual completion interrupt
229 EDMACC_3_TC_4_INT EDMA3CC3 individual completion interrupt
230 EDMACC_3_TC_5_INT EDMA3CC3 individual completion interrupt
231 EDMACC_3_TC_6_INT EDMA3CC3 individual completion interrupt
232 EDMACC_3_TC_7_INT EDMA3CC3 individual completion interrupt
233 UART_1_UARTINT UART1 interrupt
234 UART_1_URXEVT UART1 receive event
235 UART_1_UTXEVT UART1 transmit event
236 I2C_1_INT I2C1 interrupt
237 I2C_1_REVT I2C1 receive event
238 I2C_1_XEVT I2C1 transmit event
239 SPI_1_INT0 SPI1 interrupt0
240 SPI_1_INT1 SPI1 interrupt1
241 SPI_1_XEVT SPI1 transmit event
242 SPI_1_REVT SPI1 receive event
243 MPU_5_INT MPU5 addressing violation interrupt and protection violation interrupt
244 MPU_8_INT MPU8 addressing violation interrupt and protection violation interrupt
245 MPU_9_INT MPU9 addressing violation interrupt and protection violation interrupt
246 MPU_11_INT MPU11 addressing violation interrupt and protection violation interrupt
247 MPU_4_INT MPU4 addressing violation interrupt and protection violation interrupt
248 MPU_6_INT MPU6 addressing violation interrupt and protection violation interrupt
249 MPU_7_INT MPU7 addressing violation interrupt and protection violation interrupt
250 MPU_10_INT MPU10 addressing violation interrupt and protection violation interrupt
251 SPI_2_INT0 SPI2 interrupt0
252 SPI_2_INT1 SPI2 interrupt1
253 SPI_2_XEVT SPI2 transmit event
254 SPI_2_REVT SPI2 receive event
255 I2C_2_INT I2C2 interrupt
256 I2C_2_REVT I2C2 receive event
257 I2C_2_XEVT I2C2 transmit event
258 10GbE_LINK_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
259 10GbE_LINK_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
260 10GbE_USER_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
261 10GbE_USER_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
262 10GbE_MISC_INT 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
263 10GbE_INT_PKTDMA_0 10 Gigabit Ethernet Packet DMA starvation interrupt (66AK2H14 only)
264 Reserved Reserved
265 Reserved Reserved
266 Reserved Reserved
267 Reserved Reserved
268 Reserved Reserved
269 Reserved Reserved
270 Reserved Reserved
271 Reserved Reserved
272 Reserved Reserved
273 Reserved Reserved
274 Reserved Reserved
275 Reserved Reserved
276 Reserved Reserved
277 Reserved Reserved
278 Reserved Reserved
279 Reserved Reserved
280 Reserved Reserved
281 Reserved Reserved
282 Reserved Reserved
283 Reserved Reserved
284 Reserved Reserved
285 Reserved Reserved
286 Reserved Reserved
287 Reserved Reserved
288 Reserved Reserved
289 Reserved Reserved
290 Reserved Reserved
291 Reserved Reserved
292 QMSS_QUE_PEND_652 Navigator transmit queue pending event for indicated queue
293 QMSS_QUE_PEND_653 Navigator transmit queue pending event for indicated queue
294 QMSS_QUE_PEND_654 Navigator transmit queue pending event for indicated queue
295 QMSS_QUE_PEND_655 Navigator transmit queue pending event for indicated queue
296 QMSS_QUE_PEND_656 Navigator transmit queue pending event for indicated queue
297 QMSS_QUE_PEND_657 Navigator transmit queue pending event for indicated queue
298 QMSS_QUE_PEND_8844 Navigator transmit queue pending event for indicated queue
299 QMSS_QUE_PEND_8845 Navigator transmit queue pending event for indicated queue
300 QMSS_QUE_PEND_8846 Navigator transmit queue pending event for indicated queue
301 QMSS_QUE_PEND_8847 Navigator transmit queue pending event for indicated queue
302 QMSS_QUE_PEND_8848 Navigator transmit queue pending event for indicated queue
303 QMSS_QUE_PEND_8849 Navigator transmit queue pending event for indicated queue
304 QMSS_QUE_PEND_8850 Navigator transmit queue pending event for indicated queue
305 QMSS_QUE_PEND_8851 Navigator transmit queue pending event for indicated queue
306 QMSS_QUE_PEND_8852 Navigator transmit queue pending event for indicated queue
307 QMSS_QUE_PEND_8853 Navigator transmit queue pending event for indicated queue
308 QMSS_QUE_PEND_8854 Navigator transmit queue pending event for indicated queue
309 QMSS_QUE_PEND_8855 Navigator transmit queue pending event for indicated queue
310 QMSS_QUE_PEND_8856 Navigator transmit queue pending event for indicated queue
311 QMSS_QUE_PEND_8857 Navigator transmit queue pending event for indicated queue
312 QMSS_QUE_PEND_8858 Navigator transmit queue pending event for indicated queue
313 QMSS_QUE_PEND_8859 Navigator transmit queue pending event for indicated queue
314 QMSS_QUE_PEND_8860 Navigator transmit queue pending event for indicated queue
315 QMSS_QUE_PEND_8861 Navigator transmit queue pending event for indicated queue
316 QMSS_QUE_PEND_8862 Navigator transmit queue pending event for indicated queue
317 QMSS_QUE_PEND_8863 Navigator transmit queue pending event for indicated queue
318 QMSS_INTD_2_PKTDMA_0 Navigator ECC error interrupt
319 QMSS_INTD_2_PKTDMA_1 Navigator ECC error interrupt
320 QMSS_INTD_1_LOW_0 Navigator interrupt low
321 QMSS_INTD_1_LOW_1 Navigator interrupt low
322 QMSS_INTD_1_LOW_2 Navigator interrupt low
323 QMSS_INTD_1_LOW_3 Navigator interrupt low
324 QMSS_INTD_1_LOW_4 Navigator interrupt low
325 QMSS_INTD_1_LOW_5 Navigator interrupt low
326 QMSS_INTD_1_LOW_6 Navigator interrupt low
327 QMSS_INTD_1_LOW_7 Navigator interrupt low
328 QMSS_INTD_1_LOW_8 Navigator interrupt low
329 QMSS_INTD_1_LOW_9 Navigator interrupt low
330 QMSS_INTD_1_LOW_10 Navigator interrupt low
331 QMSS_INTD_1_LOW_11 Navigator interrupt low
332 QMSS_INTD_1_LOW_12 Navigator interrupt low
333 QMSS_INTD_1_LOW_13 Navigator interrupt low
334 QMSS_INTD_1_LOW_14 Navigator interrupt low
335 QMSS_INTD_1_LOW_15 Navigator interrupt low
336 QMSS_INTD_2_LOW_0 Navigator second interrupt low
337 QMSS_INTD_2_LOW_1 Navigator second interrupt low
338 QMSS_INTD_2_LOW_2 Navigator second interrupt low
339 QMSS_INTD_2_LOW_3 Navigator second interrupt low
340 QMSS_INTD_2_LOW_4 Navigator second interrupt low
341 QMSS_INTD_2_LOW_5 Navigator second interrupt low
342 QMSS_INTD_2_LOW_6 Navigator second interrupt low
343 QMSS_INTD_2_LOW_7 Navigator second interrupt low
344 QMSS_INTD_2_LOW_8 Navigator second interrupt low
345 QMSS_INTD_2_LOW_9 Navigator second interrupt low
346 QMSS_INTD_2_LOW_10 Navigator second interrupt low
347 QMSS_INTD_2_LOW_11 Navigator second interrupt low
348 QMSS_INTD_2_LOW_12 Navigator second interrupt low
349 QMSS_INTD_2_LOW_13 Navigator second interrupt low
350 QMSS_INTD_2_LOW_14 Navigator second interrupt low
351 QMSS_INTD_2_LOW_15 Navigator second interrupt low
352 TRACER_EDMACC_0 Tracer sliding time window interrupt for EDMA3CC0
353 TRACER_EDMACC_123_INT Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2 and EDMA3CC3
354 TRACER_CIC_INT Tracer sliding time window interrupt for interrupt controllers (CIC)
355 TRACER_MSMC_4_INT Tracer sliding time window interrupt for MSMC SRAM bank4
356 TRACER_MSMC_5_INT Tracer sliding time window interrupt for MSMC SRAM bank5
357 TRACER_MSMC_6_INT Tracer sliding time window interrupt for MSMC SRAM bank6
358 TRACER_MSMC_7_INT Tracer sliding time window interrupt for MSMC SRAM bank7
359 TRACER_SPI_ROM_EMIF_INT Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules
360 TRACER_QMSS_QM_CFG2_INT Tracer sliding time window interrupt for QM2
361 Reserved Reserved
362 Reserved Reserved
363 TRACER_DDR_1_INT Tracer sliding time window interrupt for DDR3B
364 Reserved Reserved
365 HYPERLINK_1_INT HyperLink 1 interrupt
366 Reserved Reserved
367 Reserved Reserved
368 Reserved Reserved
369 Reserved Reserved
370 Reserved Reserved
371 Reserved Reserved
372 Reserved Reserved
373 Reserved Reserved
374 Reserved Reserved
375 Reserved Reserved
376 Reserved Reserved
377 Reserved Reserved
378 Reserved Reserved
379 Reserved Reserved
380 Reserved Reserved
381 Reserved Reserved
382 Reserved Reserved
383 Reserved Reserved
384 Reserved Reserved
385 Reserved Reserved
386 Reserved Reserved
387 Reserved Reserved
388 Reserved Reserved
389 Reserved Reserved
390 Reserved Reserved
391 Reserved Reserved
392 Reserved Reserved
393 Reserved Reserved
394 Reserved Reserved
395 Reserved Reserved
396 Reserved Reserved
397 Reserved Reserved
398 Reserved Reserved
399 Reserved Reserved
400 Reserved Reserved
401 Reserved Reserved
402 Reserved Reserved
403 Reserved Reserved
404 Reserved Reserved
405 Reserved Reserved
406 Reserved Reserved
407 Reserved Reserved
408 Reserved Reserved
409 Reserved Reserved
410 Reserved Reserved
411 Reserved Reserved
412 Reserved Reserved
413 Reserved Reserved
414 Reserved Reserved
415 Reserved Reserved
416 Reserved Reserved
417 Reserved Reserved
418 Reserved Reserved
419 Reserved Reserved
420 Reserved Reserved
421 Reserved Reserved
422 USB_INT00 USB interrupt
423 USB_INT04 USB interrupt
424 USB_INT05 USB interrupt
425 USB_INT06 USB interrupt
426 USB_INT07 USB interrupt
427 USB_INT08 USB interrupt
428 USB_INT09 USB interrupt
429 USB_INT10 USB interrupt
430 USB_INT11 USB interrupt
431 USB_MISCINT USB miscellaneous interrupt
432 USB_OABSINT USB OABS interrupt
433 TIMER_12_INTL Timer interrupt low
434 TIMER_12_INTH Timer interrupt high
435 TIMER_13_INTL Timer interrupt low
436 TIMER_13_INTH Timer interrupt high
437 TIMER_14_INTL Timer interrupt low
438 TIMER_14_INTH Timer interrupt high
439 TIMER_15_INTL Timer interrupt low
440 TIMER_15_INTH Timer interrupt high
441 TIMER_16_INTL Timer interrupt low
442 TIMER_17_INTL Timer interrupt high
443 TIMER_18_INTL Timer interrupt low(1)
444 TIMER_19_INTL Timer interrupt high(1)
445 DDR3_1_ERR DDR3B_EMIF error interrupt
446 GPIO_INT16 GPIO interrupt
447 GPIO_INT17 GPIO interrupt
448 GPIO_INT18 GPIO interrupt
449 GPIO_INT19 GPIO interrupt
450 GPIO_INT20 GPIO interrupt
451 GPIO_INT21 GPIO interrupt
452 GPIO_INT22 GPIO interrupt
453 GPIO_INT23 GPIO interrupt
454 GPIO_INT24 GPIO interrupt
455 GPIO_INT25 GPIO interrupt
456 GPIO_INT26 GPIO interrupt
457 GPIO_INT27 GPIO interrupt
458 GPIO_INT28 GPIO interrupt
459 GPIO_INT29 GPIO interrupt
460 GPIO_INT30 GPIO interrupt
461 GPIO_INT31 GPIO interrupt
462 SRIO_INTDST20 SRIOI interrupt
463 SRIO_INTDST21 SRIOI interrupt
464 SRIO_INTDST22 SRIOI interrupt
465 SRIO_INTDST23 SRIOI interrupt
466 PCIE_INT8 PCIE MSI interrupt
467 PCIE_INT9 PCIE MSI interrupt
468 PCIE_INT10 PCIE MSI interrupt
469 PCIE_INT11 PCIE MSI interrupt
470 SEM_INT12 Semaphore interrupt
471 SEM_INT13 Semaphore interrupt
472 SEM_ERR12 Semaphore error interrupt
473 SEM_ERR13 Semaphore error interrupt
474 Reserved Reserved
(1) 66AK2H12/14 only.

Table 8-26 CIC2 Event Inputs (Secondary Events for EDMA3CC0 and Hyperlinks)

EVENT NO. EVENT NAME DESCRIPTION
0 GPIO_INT8 GPIO interrupt
1 GPIO_INT9 GPIO interrupt
2 GPIO_INT10 GPIO interrupt
3 GPIO_INT11 GPIO interrupt
4 GPIO_INT12 GPIO interrupt
5 GPIO_INT13 GPIO interrupt
6 GPIO_INT14 GPIO interrupt
7 GPIO_INT15 GPIO interrupt
8 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
9 Reserved Reserved
10 Reserved Reserved
11 TETB_FULLINT0 TETB0 is full
12 TETB_HFULLINT0 TETB0 is half full
13 TETB_ACQINT0 TETB0 acquisition has been completed
14 TETB_FULLINT1 TETB1 is full
15 TETB_HFULLINT1 TETB1 is half full
16 TETB_ACQINT1 TETB1 acquisition has been completed
17 TETB_FULLINT2 TETB2 is full
18 TETB_HFULLINT2 TETB2 is half full
19 TETB_ACQINT2 TETB2 acquisition has been completed
20 TETB_FULLINT3 TETB3 is full
21 TETB_HFULLINT3 TETB3 is half full
22 TETB_ACQINT3 TETB3 acquisition has been completed
23 Reserved Reserved
24 QMSS_INTD_1_HIGH_16 Navigator hi interrupt
25 QMSS_INTD_1_HIGH_17 Navigator hi interrupt
26 QMSS_INTD_1_HIGH_18 Navigator hi interrupt
27 QMSS_INTD_1_HIGH_19 Navigator hi interrupt
28 QMSS_INTD_1_HIGH_20 Navigator hi interrupt
29 QMSS_INTD_1_HIGH_21 Navigator hi interrupt
30 QMSS_INTD_1_HIGH_22 Navigator hi interrupt
31 QMSS_INTD_1_HIGH_23 Navigator hi interrupt
32 QMSS_INTD_1_HIGH_24 Navigator hi interrupt
33 QMSS_INTD_1_HIGH_25 Navigator hi interrupt
34 QMSS_INTD_1_HIGH_26 Navigator hi interrupt
35 QMSS_INTD_1_HIGH_27 Navigator hi interrupt
36 QMSS_INTD_1_HIGH_28 Navigator hi interrupt
37 QMSS_INTD_1_HIGH_29 Navigator hi interrupt
38 QMSS_INTD_1_HIGH_30 Navigator hi interrupt
39 QMSS_INTD_1_HIGH_31 Navigator hi interrupt
40 NETCP_MDIO_LINK_INT0 Packet Accelerator 0 subsystem MDIO interrupt
41 NETCP_MDIO_LINK_INT1 Packet Accelerator 0 subsystem MDIO interrupt
42 NETCP_MDIO_USER_INT0 Packet Accelerator 0 subsystem MDIO interrupt
43 NETCP_MDIO_USER_INT1 Packet Accelerator 0 subsystem MDIO interrupt
44 NETCP_MISC_INT Packet Accelerator 0 subsystem MDIO interrupt
45 TRACER_CORE_0_INT Tracer sliding time window interrupt for DSP0 L2
46 TRACER_CORE_1_INT Tracer sliding time window interrupt for DSP1 L2
47 TRACER_CORE_2_INT Tracer sliding time window interrupt for DSP2 L2
48 TRACER_CORE_3_INT Tracer sliding time window interrupt for DSP3 L2
49 TRACER_DDR_INT Tracer sliding time window interrupt for MSMC-DDR3A
50 TRACER_MSMC_0_INT Tracer sliding time window interrupt for MSMC SRAM bank0
51 TRACER_MSMC_1_INT Tracer sliding time window interrupt for MSMC SRAM bank1
52 TRACER_MSMC_2_INT Tracer sliding time window interrupt for MSMC SRAM bank2
53 TRACER_MSMC_3_INT Tracer sliding time window interrupt for MSMC SRAM bank3
54 TRACER_CFG_INT Tracer sliding time window interrupt for TeraNet CFG
55 TRACER_QMSS_QM_CFG1_INT Tracer sliding time window interrupt for Navigator CFG1 slave port
56 TRACER_QMSS_DMA_INT Tracer sliding time window interrupt for Navigator DMA internal bus slave port
57 TRACER_SEM_INT Tracer sliding time window interrupt for Semaphore interrupt
58 SEM_ERR0 Semaphore error interrupt
59 SEM_ERR1 Semaphore error interrupt
60 SEM_ERR2 Semaphore error interrupt
61 SEM_ERR3 Semaphore error interrupt
62 BOOTCFG_INT BOOTCFG error interrupt
63 NETCP_PKTDMA_INT0 Packet Accelerator0 Packet DMA starvation interrupt
64 MPU_0_INT MPU0 interrupt
65 MSMC_SCRUB_CERROR MSMC error interrupt
66 MPU_1_INT MPU1 interrupt
67 SRIO_INT_PKTDMA_0 Packet Accelerator0 Packet DMA interrupt
68 MPU_2_INT MPU2 interrupt
69 QMSS_INTD_1_PKTDMA_0 Navigator Packet DMA interrupt
70 MPU_3_INT MPU3 interrupt
71 QMSS_INTD_1_PKTDMA_1 Navigator Packet DMA interrupt
72 MSMC_DEDC_CERROR MSMC error interrupt
73 MSMC_DEDC_NC_ERROR MSMC error interrupt
74 MSMC_SCRUB_NC_ERROR MSMC error interrupt
75 Reserved Reserved
76 MSMC_MPF_ERROR0 Memory protection fault indicators for system master PrivID = 0
77 MSMC_MPF_ERROR1 Memory protection fault indicators for system master PrivID = 1
78 MSMC_MPF_ERROR2 Memory protection fault indicators for system master PrivID = 2
79 MSMC_MPF_ERROR3 Memory protection fault indicators for system master PrivID = 3
80 MSMC_MPF_ERROR4 Memory protection fault indicators for system master PrivID = 4
81 MSMC_MPF_ERROR5 Memory protection fault indicators for system master PrivID = 5
82 MSMC_MPF_ERROR6 Memory protection fault indicators for system master PrivID = 6
83 MSMC_MPF_ERROR7 Memory protection fault indicators for system master PrivID = 7
84 MSMC_MPF_ERROR8 Memory protection fault indicators for system master PrivID = 8
85 MSMC_MPF_ERROR9 Memory protection fault indicators for system master PrivID = 9
86 MSMC_MPF_ERROR10 Memory protection fault indicators for system master PrivID = 10
87 MSMC_MPF_ERROR11 Memory protection fault indicators for system master PrivID = 11
88 MSMC_MPF_ERROR12 Memory protection fault indicators for system master PrivID = 12
89 MSMC_MPF_ERROR13 Memory protection fault indicators for system master PrivID = 13
90 MSMC_MPF_ERROR14 Memory protection fault indicators for system master PrivID = 14
91 MSMC_MPF_ERROR15 Memory protection fault indicators for system master PrivID = 15
92 Reserved Reserved
93 SRIO_INTDST0 SRIO interrupt
94 SRIO_INTDST1 SRIO interrupt
95 SRIO_INTDST2 SRIO interrupt
96 SRIO_INTDST3 SRIO interrupt
97 SRIO_INTDST4 SRIO interrupt
98 SRIO_INTDST5 SRIO interrupt
99 SRIO_INTDST6 SRIO interrupt
100 SRIO_INTDST7 SRIO interrupt
101 SRIO_INTDST8 SRIO interrupt
102 SRIO_INTDST9 SRIO interrupt
103 SRIO_INTDST10 SRIO interrupt
104 SRIO_INTDST11 SRIO interrupt
105 SRIO_INTDST12 SRIO interrupt
106 SRIO_INTDST13 SRIO interrupt
107 SRIO_INTDST14 SRIO interrupt
108 SRIO_INTDST15 SRIO interrupt
109 SRIO_INTDST16 SRIO interrupt
110 SRIO_INTDST17 SRIO interrupt
111 SRIO_INTDST18 SRIO interrupt
112 SRIO_INTDST19 SRIO interrupt
113 SRIO_INTDST20 SRIO interrupt
114 SRIO_INTDST21 SRIO interrupt
115 SRIO_INTDST22 SRIO interrupt
116 SRIO_INTDST23 SRIO interrupt
117 AEMIF_EASYNCERR Asynchronous EMIF16 error interrupt
118 TETB_FULLINT4 TETB4 is full
119 TETB_HFULLINT4 TETB4 is half full
120 TETB_ACQINT4 TETB4 acquisition has been completed
121 TETB_FULLINT5 TETB5 is full
122 TETB_HFULLINT5 TETB5 is half full
123 TETB_ACQINT5 TETB5 acquisition has been completed
124 TETB_FULLINT6 TETB6 is full
125 TETB_HFULLINT6 TETB6 is half full
126 TETB_ACQINT6 TETB6 acquisition has been completed
127 TETB_FULLINT7 TETB7 is full
128 TETB_HFULLINT7 TETB7 is half full
129 TETB_ACQINT7 TETB7 acquisition has been completed
130 TRACER_CORE_4_INT Tracer sliding time window interrupt for DSP4 L2
131 TRACER_CORE_5_INT Tracer sliding time window interrupt for DSP5 L2
132 TRACER_CORE_6_INT Tracer sliding time window interrupt for DSP6 L2
133 TRACER_CORE_7_INT Tracer sliding time window interrupt for DSP7 L2
134 SEM_ERR4 Semaphore error interrupt
135 SEM_ERR5 Semaphore error interrupt
136 SEM_ERR6 Semaphore error interrupt
137 SEM_ERR7 Semaphore error interrupt
138 QMSS_INTD_1_HIGH_0 Navigator hi interrupt
139 QMSS_INTD_1_HIGH_1 Navigator hi interrupt
140 QMSS_INTD_1_HIGH_2 Navigator hi interrupt
141 QMSS_INTD_1_HIGH_3 Navigator hi interrupt
142 QMSS_INTD_1_HIGH_4 Navigator hi interrupt
143 QMSS_INTD_1_HIGH_5 Navigator hi interrupt
144 QMSS_INTD_1_HIGH_6 Navigator hi interrupt
145 QMSS_INTD_1_HIGH_7 Navigator hi interrupt
146 QMSS_INTD_1_HIGH_8 Navigator hi interrupt
147 QMSS_INTD_1_HIGH_9 Navigator hi interrupt
148 QMSS_INTD_1_HIGH_10 Navigator hi interrupt
149 QMSS_INTD_1_HIGH_11 Navigator hi interrupt
150 QMSS_INTD_1_HIGH_12 Navigator hi interrupt
151 QMSS_INTD_1_HIGH_13 Navigator hi interrupt
152 QMSS_INTD_1_HIGH_14 Navigator hi interrupt
153 QMSS_INTD_1_HIGH_15 Navigator hi interrupt
154 QMSS_INTD_2_HIGH_0 Navigator second hi interrupt
155 QMSS_INTD_2_HIGH_1 Navigator second hi interrupt
156 QMSS_INTD_2_HIGH_2 Navigator second hi interrupt
157 QMSS_INTD_2_HIGH_3 Navigator second hi interrupt
158 QMSS_INTD_2_HIGH_4 Navigator second hi interrupt
159 QMSS_INTD_2_HIGH_5 Navigator second hi interrupt
160 QMSS_INTD_2_HIGH_6 Navigator second hi interrupt
161 QMSS_INTD_2_HIGH_7 Navigator second hi interrupt
162 QMSS_INTD_2_HIGH_8 Navigator second hi interrupt
163 QMSS_INTD_2_HIGH_9 Navigator second hi interrupt
164 QMSS_INTD_2_HIGH_10 Navigator second hi interrupt
165 QMSS_INTD_2_HIGH_11 Navigator second hi interrupt
166 QMSS_INTD_2_HIGH_12 Navigator second hi interrupt
167 QMSS_INTD_2_HIGH_13 Navigator second hi interrupt
168 QMSS_INTD_2_HIGH_14 Navigator second hi interrupt
169 QMSS_INTD_2_HIGH_15 Navigator second hi interrupt
170 QMSS_INTD_2_HIGH_16 Navigator second hi interrupt
171 QMSS_INTD_2_HIGH_17 Navigator second hi interrupt
172 QMSS_INTD_2_HIGH_18 Navigator second hi interrupt
173 QMSS_INTD_2_HIGH_19 Navigator second hi interrupt
174 QMSS_INTD_2_HIGH_20 Navigator second hi interrupt
175 QMSS_INTD_2_HIGH_21 Navigator second hi interrupt
176 QMSS_INTD_2_HIGH_22 Navigator second hi interrupt
177 QMSS_INTD_2_HIGH_23 Navigator second hi interrupt
178 QMSS_INTD_2_HIGH_24 Navigator second hi interrupt
179 QMSS_INTD_2_HIGH_25 Navigator second hi interrupt
180 QMSS_INTD_2_HIGH_26 Navigator second hi interrupt
181 QMSS_INTD_2_HIGH_27 Navigator second hi interrupt
182 QMSS_INTD_2_HIGH_28 Navigator second hi interrupt
183 QMSS_INTD_2_HIGH_29 Navigator second hi interrupt
184 QMSS_INTD_2_HIGH_30 Navigator second hi interrupt
185 QMSS_INTD_2_HIGH_31 Navigator second hi interrupt
186 MPU_12_INT MPU12 addressing violation interrupt and protection violation interrupt
187 MPU_13_INT MPU13 addressing violation interrupt and protection violation interrupt
188 MPU_14_INT MPU14 addressing violation interrupt and protection violation interrupt
189 Reserved Reserved
190 Reserved Reserved
191 Reserved Reserved
192 Reserved Reserved
193 Reserved Reserved
194 Reserved Reserved
195 Reserved Reserved
196 Reserved Reserved
197 Reserved Reserved
198 Reserved Reserved
199 TRACER_QMSS_QM_CFG2_INT Tracer sliding time window interrupt for Navigator CFG2 slave port
200 TRACER_EDMACC_0 Tracer sliding time window interrupt foR EDMA3CC0
201 TRACER_EDMACC_123_INT Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2 and EDMA3CC3
202 TRACER_CIC_INT Tracer sliding time window interrupt for interrupt controllers (CIC)
203 Reserved Reserved
204 MPU_5_INT MPU5 addressing violation interrupt and protection violation interrupt
205 Reserved Reserved
206 MPU_7_INT MPU7 addressing violation interrupt and protection violation interrupt
207 MPU_8_INT MPU8 addressing violation interrupt and protection violation interrupt
208 QMSS_INTD_2_PKTDMA_0 Navigator ECC error interrupt
209 QMSS_INTD_2_PKTDMA_1 Navigator ECC error interrupt
210 SR_0_VPSMPSACK SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a defined time interval
211 DDR3_0_ERR DDR3A error interrupt
212 HYPERLINK_0_INT HyperLink 0 interrupt
213 EDMACC_0_ERRINT EDMA3CC0 error interrupt
214 EDMACC_0_MPINT EDMA3CC0 memory protection interrupt
215 EDMACC_0_TC_0_ERRINT EDMA3CC0 TPTC0 error interrupt
216 EDMACC_0_TC_1_ERRINT EDMA3CC0 TPTC1 error interrupt
217 EDMACC_1_ERRINT EDMA3CC1 error interrupt
218 EDMACC_1_MPINT EDMA3CC1 memory protection interrupt
219 EDMACC_1_TC_0_ERRINT EDMA3CC1 TPTC0 error interrupt
220 EDMACC_1_TC_1_ERRINT EDMA3CC1 TPTC1 error interrupt
221 EDMACC_1_TC_2_ERRINT EDMA3CC1 TPTC2 error interrupt
222 EDMACC_1_TC_3_ERRINT EDMA3CC1 TPTC3 error interrupt
223 EDMACC_2_ERRINT EDMA3CC2 error interrupt
224 EDMACC_2_MPINT EDMA3CC2 memory protection interrupt
225 EDMACC_2_TC_0_ERRINT EDMA3CC2 TPTC0 error interrupt
226 EDMACC_2_TC_1_ERRINT EDMA3CC2 TPTC1 error interrupt
227 EDMACC_2_TC_2_ERRINT EDMA3CC2 TPTC2 error interrupt
228 EDMACC_2_TC_3_ERRINT EDMA3CC2 TPTC3 error interrupt
229 EDMACC_3_ERRINT EDMA3CC3 error interrupt
230 EDMACC_3_MPINT EDMA3CC3 memory protection interrupt
231 EDMACC_3_TC_0_ERRINT EDMA3CC3 TPTC0 error interrupt
232 EDMACC_3_TC_1_ERRINT EDMA3CC3 TPTC1 error interrupt
233 EDMACC_4_ERRINT EDMA3CC4 error interrupt
234 EDMACC_4_MPINT EDMA3CC4 memory protection interrupt
235 EDMACC_4_TC_0_ERRINT EDMA3CC4 TPTC0 error interrupt
236 EDMACC_4_TC_1_ERRINT EDMA3CC4 TPTC1 error interrupt
237 QMSS_QUE_PEND_652 Navigator transmit queue pending event for indicated queue
238 QMSS_QUE_PEND_653 Navigator transmit queue pending event for indicated queue
239 QMSS_QUE_PEND_654 Navigator transmit queue pending event for indicated queue
240 QMSS_QUE_PEND_655 Navigator transmit queue pending event for indicated queue
241 QMSS_QUE_PEND_656 Navigator transmit queue pending event for indicated queue
242 QMSS_QUE_PEND_657 Navigator transmit queue pending event for indicated queue
243 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
244 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
245 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
246 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
247 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
248 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
249 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
250 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
251 QMSS_QUE_PEND_666 Navigator transmit queue pending event for indicated queue
252 QMSS_QUE_PEND_667 Navigator transmit queue pending event for indicated queue
253 QMSS_QUE_PEND_668 Navigator transmit queue pending event for indicated queue
254 QMSS_QUE_PEND_669 Navigator transmit queue pending event for indicated queue
255 QMSS_QUE_PEND_670 Navigator transmit queue pending event for indicated queue
256 QMSS_QUE_PEND_671 Navigator transmit queue pending event for indicated queue
257 QMSS_QUE_PEND_8844 Navigator transmit queue pending event for indicated queue
258 QMSS_QUE_PEND_8845 Navigator transmit queue pending event for indicated queue
259 QMSS_QUE_PEND_8846 Navigator transmit queue pending event for indicated queue
260 QMSS_QUE_PEND_8847 Navigator transmit queue pending event for indicated queue
261 QMSS_QUE_PEND_8848 Navigator transmit queue pending event for indicated queue
262 QMSS_QUE_PEND_8849 Navigator transmit queue pending event for indicated queue
263 QMSS_QUE_PEND_8850 Navigator transmit queue pending event for indicated queue
264 QMSS_QUE_PEND_8851 Navigator transmit queue pending event for indicated queue
265 QMSS_QUE_PEND_8852 Navigator transmit queue pending event for indicated queue
266 QMSS_QUE_PEND_8853 Navigator transmit queue pending event for indicated queue
267 QMSS_QUE_PEND_8854 Navigator transmit queue pending event for indicated queue
268 QMSS_QUE_PEND_8855 Navigator transmit queue pending event for indicated queue
269 QMSS_QUE_PEND_8856 Navigator transmit queue pending event for indicated queue
270 QMSS_QUE_PEND_8857 Navigator transmit queue pending event for indicated queue
271 QMSS_QUE_PEND_8858 Navigator transmit queue pending event for indicated queue
272 QMSS_QUE_PEND_8859 Navigator transmit queue pending event for indicated queue
273 QMSS_QUE_PEND_8860 Navigator transmit queue pending event for indicated queue
274 QMSS_QUE_PEND_8861 Navigator transmit queue pending event for indicated queue
275 QMSS_QUE_PEND_8862 Navigator transmit queue pending event for indicated queue
276 QMSS_QUE_PEND_8863 Navigator transmit queue pending event for indicated queue
277 10GbE_LINK_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
278 10GbE_LINK_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
279 10GbE_USER_INT0 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
280 10GbE_USER_INT1 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
281 10GbE_MISC_INT 10 Gigabit Ethernet subsystem MDIO interrupt (66AK2H14 only)
282 10GbE_INT_PKTDMA_0 10 Gigabit Ethernet Packet DMA starvation interrupt
283 SEM_INT0 Semaphore interrupt
284 SEM_INT1 Semaphore interrupt
285 SEM_INT2 Semaphore interrupt
286 SEM_INT3 Semaphore interrupt
287 SEM_INT4 Semaphore interrupt
288 SEM_INT5 Semaphore interrupt
289 SEM_INT6 Semaphore interrupt
290 SEM_INT7 Semaphore interrupt
291 SEM_INT8 Semaphore interrupt
292 SEM_INT9 Semaphore interrupt
293 SEM_INT10 Semaphore interrupt
294 SEM_INT11 Semaphore interrupt
295 SEM_INT12 Semaphore interrupt
296 SEM_INT13 Semaphore interrupt
297 SEM_INT14 Semaphore interrupt
298 SEM_INT15 Semaphore interrupt
299 SEM_ERR8 Semaphore error interrupt
300 SEM_ERR9 Semaphore error interrupt
301 SEM_ERR10 Semaphore error interrupt
302 SEM_ERR11 Semaphore error interrupt
303 SEM_ERR12 Semaphore error interrupt
304 SEM_ERR13 Semaphore error interrupt
305 SEM_ERR14 Semaphore error interrupt
306 SEM_ERR15 Semaphore error interrupt
307 DDR3_1_ERR DDR3B error interrupt
308 HYPERLINK_1_INT HyperLink 1 interrupt
309 Reserved Reserved
310 Reserved Reserved
311 Reserved Reserved
312 Reserved Reserved
313 Reserved Reserved
314 Reserved Reserved
315 Reserved Reserved
316 Reserved Reserved
317 Reserved Reserved
318 Reserved Reserved
319 Reserved Reserved
320 Reserved Reserved
321 Reserved Reserved
322 Reserved Reserved
323 Reserved Reserved
324 Reserved Reserved
325 Reserved Reserved
326 Reserved Reserved
327 Reserved Reserved
328 Reserved Reserved
329 Reserved Reserved
330 Reserved Reserved
331 Reserved Reserved
332 Reserved Reserved
333 Reserved Reserved
334 Reserved Reserved
335 Reserved Reserved
336 Reserved Reserved
337 Reserved Reserved
338 Reserved Reserved
339 Reserved Reserved
340 Reserved Reserved
341 Reserved Reserved
342 Reserved Reserved
343 Reserved Reserved
344 Reserved Reserved
345 Reserved Reserved
346 Reserved Reserved
347 Reserved Reserved
348 Reserved Reserved
349 Reserved Reserved
350 Reserved Reserved
351 Reserved Reserved
352 Reserved Reserved
353 Reserved Reserved
354 Reserved Reserved
355 Reserved Reserved
356 Reserved Reserved
357 Reserved Reserved
358 Reserved Reserved
359 Reserved Reserved
360 Reserved Reserved
361 Reserved Reserved
362 PSC_ALLINT PSC interrupt
363 Reserved Reserved
364 Reserved Reserved
365 Reserved Reserved
366 Reserved Reserved
367 Reserved Reserved
368 Reserved Reserved
369 Reserved Reserved
370 Reserved Reserved
371 Reserved Reserved
372 MPU_9_INT MPU9 addressing violation interrupt and protection violation interrupt
373 MPU_10_INT MPU10 addressing violation interrupt and protection violation interrupt
374 MPU_11_INT MPU11 addressing violation interrupt and protection violation interrupt
375 TRACER_MSMC_4_INT Tracer sliding time window interrupt for MSMC SRAM Bank 4
376 TRACER_MSMC_5_INT Tracer sliding time window interrupt for MSMC SRAM Bank 4
377 TRACER_MSMC_6_INT Tracer sliding time window interrupt for MSMC SRAM Bank 4
378 TRACER_MSMC_7_INT Tracer sliding time window interrupt for MSMC SRAM Bank 4
379 TRACER_DDR_1_INT Tracer sliding time window interrupt for DDR3B
380 Reserved Reserved
381 Reserved Reserved
382 Reserved Reserved
383 Reserved Reserved
384 TRACER_SPI_ROM_EMIF_INT Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules
385 Reserved Reserved
386 Reserved Reserved
387 TIMER_8_INTL Timer interrupt low
388 TIMER_8_INTH Timer interrupt high
389 TIMER_9_INTL Timer interrupt low
390 TIMER_9_INTH Timer interrupt high
391 TIMER_10_INTL Timer interrupt low
392 TIMER_10_INTH Timer interrupt high
393 TIMER_11_INTL Timer interrupt low
394 TIMER_11_INTH Timer interrupt high
395 TIMER_14_INTL Timer interrupt low
396 TIMER_14_INTH Timer interrupt high
397 TIMER_15_INTL Timer interrupt low
398 TIMER_15_INTH Timer interrupt high
399 USB_INT00 USB interrupt
400 USB_INT04 USB interrupt
401 USB_INT05 USB interrupt
402 USB_INT06 USB interrupt
403 USB_INT07 USB interrupt
404 USB_INT08 USB interrupt
405 USB_INT09 USB interrupt
406 USB_INT10 USB interrupt
407 USB_INT11 USB interrupt
408 USB_MISCINT USB miscellaneous interrupt
409 USB_OABSINT USB OABS interrupt
410 Reserved Reserved
411 Reserved Reserved
412 Reserved Reserved
413 Reserved Reserved
414 Reserved Reserved
415 Reserved Reserved
416 Reserved Reserved
417 Reserved Reserved
418 Reserved Reserved
419 Reserved Reserved
420 Reserved Reserved
421 Reserved Reserved
422 Reserved Reserved
423 Reserved Reserved
424 Reserved Reserved
425 Reserved Reserved
426 Reserved Reserved
427 Reserved Reserved
428 Reserved Reserved
429 Reserved Reserved
430 Reserved Reserved
431 Reserved Reserved
432 Reserved Reserved
433 Reserved Reserved
434 Reserved Reserved
435 Reserved Reserved
436 Reserved Reserved
437 Reserved Reserved
438 Reserved Reserved
439 Reserved Reserved
440 Reserved Reserved
441 Reserved Reserved
442 TETB_OVFLINT0 ETB0 overflow (emulation trace buffer)
443 TETB_UNFLINT0 ETB0 underflow
444 TETB_OVFLINT1 ETB1 overflow (emulation trace buffer)
445 TETB_UNFLINT1 ETB1 underflow
446 TETB_OVFLINT2 ETB2 overflow (emulation trace buffer)
447 TETB_UNFLINT2 ETB2 underflow
448 TETB_OVFLINT3 ETB3 overflow (emulation trace buffer)
449 TETB_UNFLINT3 ETB3 underflow
450 TETB_OVFLINT4 ETB4 overflow (emulation trace buffer)
451 TETB_UNFLINT4 ETB4 underflow
452 TETB_OVFLINT5 ETB5 overflow (emulation trace buffer)
453 TETB_UNFLINT5 ETB5 underflow
454 TETB_OVFLINT6 ETB6 overflow (emulation trace buffer)
455 TETB_UNFLINT6 ETB6 underflow
456 TETB_OVFLINT7 ETB7 overflow (emulation trace buffer)
457 TETB_UNFLINT7 ETB7 underflow
458 ARM_TBR_DMA ARM trace buffer
459 Reserved Reserved
460 Reserved Reserved
461 Reserved Reserved
462 Reserved Reserved
463 GPIO_INT0 GPIO interrupt
464 GPIO_INT1 GPIO interrupt
465 GPIO_INT2 GPIO interrupt
466 GPIO_INT3 GPIO interrupt
467 GPIO_INT4 GPIO interrupt
468 GPIO_INT5 GPIO interrupt
469 GPIO_INT6 GPIO interrupt
470 GPIO_INT7 GPIO interrupt
471 IPC_GR0 IPC interrupt generation
472 IPC_GR1 IPC interrupt generation
473 IPC_GR2 IPC interrupt generation
474 IPC_GR3 IPC interrupt generation
475 IPC_GR4 IPC interrupt generation
476 IPC_GR5 IPC interrupt generation
477 IPC_GR6 IPC interrupt generation
478 IPC_GR7 IPC interrupt generation

8.3.2 CIC Registers

This section includes the CIC memory map information and registers.

8.3.2.1 CIC0 Register Map

Table 8-27 CIC0 Registers

ADDRESS OFFSET REGISTER MNEMONIC REGISTER NAME
0x0 REVISION_REG Revision Register
0x4 CONTROL_REG Control Register
0xC HOST_CONTROL_REG Host Control Register
0x10 GLOBAL_ENABLE_HINT_REG Global Host Int Enable Register
0x20 STATUS_SET_INDEX_REG Status Set Index Register
0x24 STATUS_CLR_INDEX_REG Status Clear Index Register
0x28 ENABLE_SET_INDEX_REG Enable Set Index Register
0x2C ENABLE_CLR_INDEX_REG Enable Clear Index Register
0x34 HINT_ENABLE_SET_INDEX_REG Host Int Enable Set Index Register
0x38 HINT_ENABLE_CLR_INDEX_REG Host Int Enable Clear Index Register
0x200 RAW_STATUS_REG0 Raw Status Register 0
0x204 RAW_STATUS_REG1 Raw Status Register 1
0x208 RAW_STATUS_REG2 Raw Status Register 2
0x20C RAW_STATUS_REG3 Raw Status Register 3
0x210 RAW_STATUS_REG4 Raw Status Register 4
0x214 RAW_STATUS_REG5 Raw Status Register 5
0x218 RAW_STATUS_REG6 Raw Status Register 6
0x21C RAW_STATUS_REG7 Raw Status Register 7
0x220 RAW_STATUS_REG8 Raw Status Register 8
0x224 RAW_STATUS_REG9 Raw Status Register 9
0x228 RAW_STATUS_REG10 Raw Status Register 10
0x22C RAW_STATUS_REG11 Raw Status Register 11
0x230 RAW_STATUS_REG12 Raw Status Register 12
0x234 RAW_STATUS_REG13 Raw Status Register 13
0x238 RAW_STATUS_REG14 Raw Status Register 14
0x23C RAW_STATUS_REG15 Raw Status Register 15
0x280 ENA_STATUS_REG0 Enabled Status Register 0
0x284 ENA_STATUS_REG1 Enabled Status Register 1
0x288 ENA_STATUS_REG2 Enabled Status Register 2
0x28C ENA_STATUS_REG3 Enabled Status Register 3
0x290 ENA_STATUS_REG4 Enabled Status Register 4
0x294 ENA_STATUS_REG5 Enabled Status Register 5
0x298 ENA_STATUS_REG6 Enabled Status Register 6
0x29C ENA_STATUS_REG7 Enabled Status Register 7
0x2A0 ENA_STATUS_REG8 Enabled Status Register 8
0x2A4 ENA_STATUS_REG9 Enabled Status Register 9
0x2A8 ENA_STATUS_REG10 Enabled Status Register10
0x2AC ENA_STATUS_REG11 Enabled Status Register 11
0x2B0 ENA_STATUS_REG12 Enabled Status Register 12
0x2B4 ENA_STATUS_REG13 Enabled Status Register 13
0x2B8 ENA_STATUS_REG14 Enabled Status Register 14
0x2BC ENA_STATUS_REG15 Enabled Status Register 15
0x300 ENABLE_REG0 Enable Register 0
0x304 ENABLE_REG1 Enable Register 1
0x308 ENABLE_REG2 Enable Register 2
0x30C ENABLE_REG3 Enable Register 3
0x310 ENABLE_REG4 Enable Register 4
0x314 ENABLE_REG5 Enable Register 5
0x318 ENABLE_REG6 Enable Register 6
0x31C ENABLE_REG7 Enable Register 7
0x320 ENABLE_REG8 Enable Register 8
0x324 ENABLE_REG9 Enable Register 9
0x328 ENABLE_REG10 Enable Register 10
0x32C ENABLE_REG11 Enable Register 11
0x330 ENABLE_REG12 Enable Register 12
0x334 ENABLE_REG13 Enable Register 13
0x338 ENABLE_REG14 Enable Register 14
0x33C ENABLE_REG15 Enable Register 15
0x380 ENABLE_CLR_REG0 Enable Clear Register 0
0x384 ENABLE_CLR_REG1 Enable Clear Register 1
0x388 ENABLE_CLR_REG2 Enable Clear Register 2
0x38C ENABLE_CLR_REG3 Enable Clear Register 3
0x390 ENABLE_CLR_REG4 Enable Clear Register 4
0x394 ENABLE_CLR_REG5 Enable Clear Register 5
0x398 ENABLE_CLR_REG6 Enable Clear Register 6
0x39C ENABLE_CLR_REG7 Enable Clear Register 7
0x3A0 ENABLE_CLR_REG8 Enable Clear Register 8
0x3A4 ENABLE_CLR_REG9 Enable Clear Register 9
0x3A8 ENABLE_CLR_REG10 Enable Clear Register 10
0x3AC ENABLE_CLR_REG11 Enable Clear Register 11
0x3B0 ENABLE_CLR_REG12 Enable Clear Register 12
0x3B4 ENABLE_CLR_REG13 Enable Clear Register 13
0x3B8 ENABLE_CLR_REG14 Enable Clear Register 14
0x38C ENABLE_CLR_REG15 Enable Clear Register 15
0x400 CH_MAP_REG0 Interrupt Channel Map Register for 0 to 0+3
0x404 CH_MAP_REG1 Interrupt Channel Map Register for 4 to 4+3
0x408 CH_MAP_REG2 Interrupt Channel Map Register for 8 to 8+3
0x40C CH_MAP_REG3 Interrupt Channel Map Register for 12 to 12+3
0x410 CH_MAP_REG4 Interrupt Channel Map Register for 16 to 16+3
0x414 CH_MAP_REG5 Interrupt Channel Map Register for 20 to 20+3
0x418 CH_MAP_REG6 Interrupt Channel Map Register for 24 to 24+3
0x41C CH_MAP_REG7 Interrupt Channel Map Register for 28 to 28+3
0x420 CH_MAP_REG8 Interrupt Channel Map Register for 32 to 32+3
0x424 CH_MAP_REG9 Interrupt Channel Map Register for 36 to 36+3
0x428 CH_MAP_REG10 Interrupt Channel Map Register for 40 to 40+3
0x42C CH_MAP_REG11 Interrupt Channel Map Register for 44 to 44+3
0x430 CH_MAP_REG12 Interrupt Channel Map Register for 48 to 48+3
0x434 CH_MAP_REG13 Interrupt Channel Map Register for 52 to 52+3
0x438 CH_MAP_REG14 Interrupt Channel Map Register for 56 to 56+3
0x43C CH_MAP_REG15 Interrupt Channel Map Register for 60 to 60+3
0x440 CH_MAP_REG16 Interrupt Channel Map Register for 64 to 64+3
0x444 CH_MAP_REG17 Interrupt Channel Map Register for 68 to 68+3
0x448 CH_MAP_REG18 Interrupt Channel Map Register for 72 to 72+3
0x44C CH_MAP_REG19 Interrupt Channel Map Register for 76 to 76+3
0x450 CH_MAP_REG20 Interrupt Channel Map Register for 80 to 80+3
0x454 CH_MAP_REG21 Interrupt Channel Map Register for 84 to 84+3
0x458 CH_MAP_REG22 Interrupt Channel Map Register for 88 to 88+3
0x45C CH_MAP_REG23 Interrupt Channel Map Register for 92 to 92+3
0x460 CH_MAP_REG24 Interrupt Channel Map Register for 96 to 96+3
0x464 CH_MAP_REG25 Interrupt Channel Map Register for 100 to 100+3
0x468 CH_MAP_REG26 Interrupt Channel Map Register for 104 to 104+3
0x46C CH_MAP_REG27 Interrupt Channel Map Register for 108 to 108+3
0x470 CH_MAP_REG28 Interrupt Channel Map Register for 112 to 112+3
0x474 CH_MAP_REG29 Interrupt Channel Map Register for 116 to 116+3
0x478 CH_MAP_REG30 Interrupt Channel Map Register for 120 to 120+3
0x47C CH_MAP_REG31 Interrupt Channel Map Register for 124 to 124+3
0x480 CH_MAP_REG32 Interrupt Channel Map Register for 128 to 128+3
0x484 CH_MAP_REG33 Interrupt Channel Map Register for 132 to 132+3
0x488 CH_MAP_REG34 Interrupt Channel Map Register for 136 to 136+3
0x48C CH_MAP_REG35 Interrupt Channel Map Register for 140 to 140+3
0x490 CH_MAP_REG36 Interrupt Channel Map Register for 144 to 144+3
0x494 CH_MAP_REG37 Interrupt Channel Map Register for 148 to 148+3
0x498 CH_MAP_REG38 Interrupt Channel Map Register for 152 to 152+3
0x49C CH_MAP_REG39 Interrupt Channel Map Register for 156 to 156+3
0x4a0 CH_MAP_REG40 Interrupt Channel Map Register for 160 to 160+3
0x4a4 CH_MAP_REG41 Interrupt Channel Map Register for 164 to 164+3
0x4a8 CH_MAP_REG42 Interrupt Channel Map Register for 168 to 168+3
0x4AC CH_MAP_REG43 Interrupt Channel Map Register for 172 to 172+3
0x4b0 CH_MAP_REG44 Interrupt Channel Map Register for 176 to 176+3
0x4b4 CH_MAP_REG45 Interrupt Channel Map Register for 180 to 180+3
0x4b8 CH_MAP_REG46 Interrupt Channel Map Register for 184 to 184+3
0x4BC CH_MAP_REG47 Interrupt Channel Map Register for 188 to 188+3
0x4C0 CH_MAP_REG48 Interrupt Channel Map Register for 192 to 192+3
0x4C4 CH_MAP_REG49 Interrupt Channel Map Register for 196 to 196+3
0x4C8 CH_MAP_REG50 Interrupt Channel Map Register for 200 to 200+3
0x4CC CH_MAP_REG51 Interrupt Channel Map Register for 204 to 204+3
0x4D0 CH_MAP_REG52 Interrupt Channel Map Register for 208 to 208+3
0x4D4 CH_MAP_REG53 Interrupt Channel Map Register for 212 to 212+3
0x4D8 CH_MAP_REG54 Interrupt Channel Map Register for 216 to 216+3
0x4DC CH_MAP_REG55 Interrupt Channel Map Register for 220 to 220+3
0x4E0 CH_MAP_REG56 Interrupt Channel Map Register for 224 to 224+3
0x4E4 CH_MAP_REG57 Interrupt Channel Map Register for 228 to 228+3
0x4E8 CH_MAP_REG58 Interrupt Channel Map Register for 232 to 232+3
0x4FC CH_MAP_REG59 Interrupt Channel Map Register for 236 to 236+3
0x4F0 CH_MAP_REG60 Interrupt Channel Map Register for 240 to 240+3
0x4F4 CH_MAP_REG61 Interrupt Channel Map Register for 244 to 244+3
0x4F8 CH_MAP_REG62 Interrupt Channel Map Register for 248 to 248+3
0x4FC CH_MAP_REG63 Interrupt Channel Map Register for 252 to 252+3
0x500 CH_MAP_REG64 Interrupt Channel Map Register for 256 to 256+3
0x504 CH_MAP_REG65 Interrupt Channel Map Register for 260 to 260+3
0x508 CH_MAP_REG66 Interrupt Channel Map Register for 264 to 264+3
0x50C CH_MAP_REG67 Interrupt Channel Map Register for 268 to 268+3
0x510 CH_MAP_REG68 Interrupt Channel Map Register for 272 to 272+3
0x514 CH_MAP_REG69 Interrupt Channel Map Register for 276 to 276+3
0x518 CH_MAP_REG70 Interrupt Channel Map Register for 280 to 280+3
0x51C CH_MAP_REG71 Interrupt Channel Map Register for 284 to 284+3
0x520 CH_MAP_REG72 Interrupt Channel Map Register for 288 to 288+3
0x524 CH_MAP_REG73 Interrupt Channel Map Register for 292 to 292+3
0x528 CH_MAP_REG74 Interrupt Channel Map Register for 296 to 296+3
0x52C CH_MAP_REG75 Interrupt Channel Map Register for 300 to 300+3
0x520 CH_MAP_REG76 Interrupt Channel Map Register for 304 to 304+3
0x524 CH_MAP_REG77 Interrupt Channel Map Register for 308 to 308+3
0x528 CH_MAP_REG78 Interrupt Channel Map Register for 312 to 312+3
0x52C CH_MAP_REG79 Interrupt Channel Map Register for 316 to 316+3
0x530 CH_MAP_REG80 Interrupt Channel Map Register for 320 to 320+3
0x534 CH_MAP_REG81 Interrupt Channel Map Register for 324 to 324+3
0x538 CH_MAP_REG82 Interrupt Channel Map Register for 328 to 328+3
0x53C CH_MAP_REG83 Interrupt Channel Map Register for 332 to332+3
0x540 CH_MAP_REG84 Interrupt Channel Map Register for336 to 336+3
0x544 CH_MAP_REG85 Interrupt Channel Map Register for 340 to 340+3
0x548 CH_MAP_REG86 Interrupt Channel Map Register for 344 to 344+3
0x54C CH_MAP_REG87 Interrupt Channel Map Register for 348 to 348+3
0x550 CH_MAP_REG88 Interrupt Channel Map Register for 352 to 352+3
0x554 CH_MAP_REG89 Interrupt Channel Map Register for 356 to 356+3
0x558 CH_MAP_REG90 Interrupt Channel Map Register for 360 to 360+3
0x55C CH_MAP_REG91 Interrupt Channel Map Register for 364 to 364+3
0x560 CH_MAP_REG92 Interrupt Channel Map Register for 368 to 368+3
0x564 CH_MAP_REG93 Interrupt Channel Map Register for372 to 372+3
0x568 CH_MAP_REG94 Interrupt Channel Map Register for 376 to 376+3
0x56C CH_MAP_REG95 Interrupt Channel Map Register for 380 to 380+3
0x570 CH_MAP_REG96 Interrupt Channel Map Register for 384 to 384+3
0x574 CH_MAP_REG97 Interrupt Channel Map Register for 388 to 388+3
0x578 CH_MAP_REG98 Interrupt Channel Map Register for 392 to 392+3
0x57C CH_MAP_REG99 Interrupt Channel Map Register for 396 to 396+3
0x580 CH_MAP_REG100 Interrupt Channel Map Register for 400 to 400+3
0x584 CH_MAP_REG101 Interrupt Channel Map Register for 404 to 404+3
0x588 CH_MAP_REG102 Interrupt Channel Map Register for 408 to 408+3
0x58C CH_MAP_REG103 Interrupt Channel Map Register for 412 to412+3
0x590 CH_MAP_REG104 Interrupt Channel Map Register for 416 to 416+3
0x594 CH_MAP_REG105 Interrupt Channel Map Register for 420 to 420+3
0x598 CH_MAP_REG106 Interrupt Channel Map Register for 424 to 424+3
0x59C CH_MAP_REG107 Interrupt Channel Map Register for 428 to 428+3
0x5A0 CH_MAP_REG108 Interrupt Channel Map Register for 432 to 432+3
0x5A4 CH_MAP_REG109 Interrupt Channel Map Register for 436 to 436+3
0x5A8 CH_MAP_REG110 Interrupt Channel Map Register for 440 to 440+3
0x5AC CH_MAP_REG111 Interrupt Channel Map Register for 444 to 444+3
0x5B0 CH_MAP_REG112 Interrupt Channel Map Register for 448 to 448+3
0x5B4 CH_MAP_REG113 Interrupt Channel Map Register for 452 to 452+3
0x5B8 CH_MAP_REG114 Interrupt Channel Map Register for 456 to 456+3
0x5BC CH_MAP_REG115 Interrupt Channel Map Register for 460 to 460+3
0x5C0 CH_MAP_REG116 Interrupt Channel Map Register for 464 to 464+3
0x5C4 CH_MAP_REG117 Interrupt Channel Map Register for 468 to 468+3
0x5C8 CH_MAP_REG118 Interrupt Channel Map Register for 472 to 472+3
0x5CC CH_MAP_REG119 Interrupt Channel Map Register for 476 to 476+3
0x5D0 CH_MAP_REG120 Interrupt Channel Map Register for 480 to 480+3
0x5D4 CH_MAP_REG121 Interrupt Channel Map Register for 484 to 484+3
0x5D8 CH_MAP_REG122 Interrupt Channel Map Register for 488 to 488+3
0x5DC CH_MAP_REG123 Interrupt Channel Map Register for 482 to 492+3
0x5E0 CH_MAP_REG124 Interrupt Channel Map Register for 496 to 496+3
0x5E4 CH_MAP_REG125 Interrupt Channel Map Register for 500 to 500+3
0x5E8 CH_MAP_REG126 Interrupt Channel Map Register for 504 to 504+3
0x5EC CH_MAP_REG127 Interrupt Channel Map Register for 508 to 508+3
0x5F0 CH_MAP_REG128 Interrupt Channel Map Register for 512 to 512+3
0x5F4 CH_MAP_REG129 Interrupt Channel Map Register for 516 to 516+3
0x5F8 CH_MAP_REG130 Interrupt Channel Map Register for 520 to 520+3
0x5FC CH_MAP_REG131 Interrupt Channel Map Register for 524 to 524+3
0x600 CH_MAP_REG132 Interrupt Channel Map Register for 528 to 528+3
0x604 CH_MAP_REG133 Interrupt Channel Map Register for 532 to 532+3
0x608 CH_MAP_REG134 Interrupt Channel Map Register for 536 to 536+3
0x60C CH_MAP_REG135 Interrupt Channel Map Register for 540 to 540+3
0x610 CH_MAP_REG136 Interrupt Channel Map Register for 544 to 544+3
0x614 CH_MAP_REG137 Interrupt Channel Map Register for 548 to 548+3
0x618 CH_MAP_REG138 Interrupt Channel Map Register for 552 to 552+3
0x61C CH_MAP_REG139 Interrupt Channel Map Register for 556 to 556+3
0x620 CH_MAP_REG140 Interrupt Channel Map Register for 560 to 560+3
0x624 CH_MAP_REG141 Interrupt Channel Map Register for 564 to 564+3
0x628 CH_MAP_REG142 Interrupt Channel Map Register for 568 to 568+3
0x62C CH_MAP_REG143 Interrupt Channel Map Register for 572 to 572+3
0x630 CH_MAP_REG144 Interrupt Channel Map Register for 576 to 576+3
0x634 CH_MAP_REG145 Interrupt Channel Map Register for 580 to 580+3
0x638 CH_MAP_REG146 Interrupt Channel Map Register for 584 to 584+3
0x63C CH_MAP_REG147 Interrupt Channel Map Register for 588 to 588+3
0x640 CH_MAP_REG148 Interrupt Channel Map Register for 592 to 592+3
0x644 CH_MAP_REG149 Interrupt Channel Map Register for 596 to 596+3
0x648 CH_MAP_REG150 Interrupt Channel Map Register for 600 to 600+3
0x64C CH_MAP_REG151 Interrupt Channel Map Register for 604 to 604+3
0x650 CH_MAP_REG152 Interrupt Channel Map Register for 608 to 608+3
0x654 CH_MAP_REG153 Interrupt Channel Map Register for 612 to 612+3
0x658 CH_MAP_REG154 Interrupt Channel Map Register for 616 to 616+3
0x65C CH_MAP_REG155 Interrupt Channel Map Register for 620 to 620+3
0x660 CH_MAP_REG156 Interrupt Channel Map Register for 624 to 624+3
0x664 CH_MAP_REG157 Interrupt Channel Map Register for 628 to 628+3
0x668 CH_MAP_REG158 Interrupt Channel Map Register for 632 to 632+3
0x66C CH_MAP_REG159 Interrupt Channel Map Register for 636 to 636+3
0x670 CH_MAP_REG160 Interrupt Channel Map Register for 640 to 640+3
0x674 CH_MAP_REG161 Interrupt Channel Map Register for 644 to 644+3
0x678 CH_MAP_REG162 Interrupt Channel Map Register for 648 to 648+3
0x67C CH_MAP_REG163 Interrupt Channel Map Register for 652 to 652+3
0x680 CH_MAP_REG164 Interrupt Channel Map Register for 656 to 656+3
0x684 CH_MAP_REG165 Interrupt Channel Map Register for 660 to 660+3
0x688 CH_MAP_REG166 Interrupt Channel Map Register for 664 to 664+3
0x68C CH_MAP_REG167 Interrupt Channel Map Register for 668 to 668+3
0x690 CH_MAP_REG168 Interrupt Channel Map Register for 672 to 672+3
0x694 CH_MAP_REG169 Interrupt Channel Map Register for 676 to 676+3
0x698 CH_MAP_REG170 Interrupt Channel Map Register for 680 to 680+3
0x69C CH_MAP_REG171 Interrupt Channel Map Register for 684 to 684+3
0x800 HINT_MAP_REG0 Host Interrupt Map Register for 0 to 0+3
0x804 HINT_MAP_REG1 Host Interrupt Map Register for 4 to 4+3
0x808 HINT_MAP_REG2 Host Interrupt Map Register for 8 to 8+3
0x80C HINT_MAP_REG3 Host Interrupt Map Register for 12 to 12+3
0x810 HINT_MAP_REG4 Host Interrupt Map Register for 16 to 16+3
0x814 HINT_MAP_REG5 Host Interrupt Map Register for 20 to 20+3
0x818 HINT_MAP_REG6 Host Interrupt Map Register for 24 to 24+3
0x81C HINT_MAP_REG7 Host Interrupt Map Register for 28 to 28+3
0x820 HINT_MAP_REG8 Host Interrupt Map Register for 32 to 32+3
0x824 HINT_MAP_REG9 Host Interrupt Map Register for 36 to 36+3
0x828 HINT_MAP_REG10 Host Interrupt Map Register for 40 to 40+3
0x82C HINT_MAP_REG11 Host Interrupt Map Register for 44 to 44+3
0x830 HINT_MAP_REG12 Host Interrupt Map Register for 48 to 48+3
0x834 HINT_MAP_REG13 Host Interrupt Map Register for 52 to 52+3
0x838 HINT_MAP_REG14 Host Interrupt Map Register for 56 to 56+3
0x83C HINT_MAP_REG15 Host Interrupt Map Register for 60 to 60+3
0x840 HINT_MAP_REG16 Host Interrupt Map Register for 64 to 64+3
0x844 HINT_MAP_REG17 Host Interrupt Map Register for 68 to 68+3
0x848 HINT_MAP_REG18 Host Interrupt Map Register for 72 to 72+3
0x84C HINT_MAP_REG19 Host Interrupt Map Register for 76 to 76+3
0x1500 ENABLE_HINT_REG0 Host Int Enable Register 0
0x1504 ENABLE_HINT_REG1 Host Int Enable Register 1
0x1508 ENABLE_HINT_REG2 Host Int Enable Register 2

8.3.2.2 CIC1 Register Map

Table 8-28 CIC1 Registers

ADDRESS OFFSET REGISTER MNEMONIC REGISTER NAME
0x0 REVISION_REG Revision Register
0x10 GLOBAL_ENABLE_HINT_REG Global Host Interrupt Enable Register
0x20 STATUS_SET_INDEX_REG Status Set Index Register
0x24 STATUS_CLR_INDEX_REG Status Clear Index Register
0x28 ENABLE_SET_INDEX_REG Enable Set Index Register
0x2C ENABLE_CLR_INDEX_REG Enable Clear Index Register
0x34 HINT_ENABLE_SET_INDEX_REG Host Interrupt Enable Set Index Register
0x38 HINT_ENABLE_CLR_INDEX_REG Host Interrupt Enable Clear Index Register
0x200 RAW_STATUS_REG0 Raw Status Register 0
0x204 RAW_STATUS_REG1 Raw Status Register 1
0x208 RAW_STATUS_REG2 Raw Status Register 2
0x20C RAW_STATUS_REG3 Raw Status Register 3
0x210 RAW_STATUS_REG4 Raw Status Register 4
0x214 RAW_STATUS_REG5 Raw Status Register 5
0x218 RAW_STATUS_REG6 Raw Status Register 6
0x21C RAW_STATUS_REG7 Raw Status Register 7
0x220 RAW_STATUS_REG8 Raw Status Register 8
0x224 RAW_STATUS_REG9 Raw Status Register 9
0x228 RAW_STATUS_REG10 Raw Status Register 10
0x22C RAW_STATUS_REG11 Raw Status Register 11
0x230 RAW_STATUS_REG12 Raw Status Register 12
0x234 RAW_STATUS_REG13 Raw Status Register 13
0x238 RAW_STATUS_REG14 Raw Status Register 14
0x23C RAW_STATUS_REG15 Raw Status Register 15
0x280 ENA_STATUS_REG0 Enabled Status Register 0
0x284 ENA_STATUS_REG1 Enabled Status Register 1
0x288 ENA_STATUS_REG2 Enabled Status Register 2
0x28C ENA_STATUS_REG3 Enabled Status Register 3
0x290 ENA_STATUS_REG4 Enabled Status Register 4
0x294 ENA_STATUS_REG5 Enabled Status Register 5
0x298 ENA_STATUS_REG6 Enabled Status Register 6
0x29C ENA_STATUS_REG7 Enabled Status Register 7
0x2A0 ENA_STATUS_REG8 Enabled Status Register 8
0x2A4 ENA_STATUS_REG9 Enabled Status Register 9
0x2A8 ENA_STATUS_REG10 Enabled Status Register10
0x2AC ENA_STATUS_REG11 Enabled Status Register 11
0x2B0 ENA_STATUS_REG12 Enabled Status Register 12
0x2B4 ENA_STATUS_REG13 Enabled Status Register 13
0x2B8 ENA_STATUS_REG14 Enabled Status Register 14
0x2BC ENA_STATUS_REG15 Enabled Status Register 15
0x300 ENABLE_REG0 Enable Register 0
0x304 ENABLE_REG1 Enable Register 1
0x308 ENABLE_REG2 Enable Register 2
0x30C ENABLE_REG3 Enable Register 3
0x310 ENABLE_REG4 Enable Register 4
0x314 ENABLE_REG5 Enable Register 5
0x318 ENABLE_REG6 Enable Register 6
0x31C ENABLE_REG7 Enable Register 7
0x320 ENABLE_REG8 Enable Register 8
0x324 ENABLE_REG9 Enable Register 9
0x328 ENABLE_REG10 Enable Register 10
0x32C ENABLE_REG11 Enable Register 11
0x330 ENABLE_REG12 Enable Register 12
0x334 ENABLE_REG13 Enable Register 13
0x338 ENABLE_REG14 Enable Register 14
0x33C ENABLE_REG15 Enable Register 15
0x380 ENABLE_CLR_REG0 Enable Clear Register 0
0x384 ENABLE_CLR_REG1 Enable Clear Register 1
0x388 ENABLE_CLR_REG2 Enable Clear Register 2
0x38C ENABLE_CLR_REG3 Enable Clear Register 3
0x390 ENABLE_CLR_REG4 Enable Clear Register 4
0x394 ENABLE_CLR_REG5 Enable Clear Register 5
0x398 ENABLE_CLR_REG6 Enable Clear Register 6
0x39C ENABLE_CLR_REG7 Enable Clear Register 7
0x3A0 ENABLE_CLR_REG8 Enable Clear Register 8
0x3A4 ENABLE_CLR_REG9 Enable Clear Register 9
0x3A8 ENABLE_CLR_REG10 Enable Clear Register 10
0x3AC ENABLE_CLR_REG11 Enable Clear Register 11
0x3B0 ENABLE_CLR_REG12 Enable Clear Register 12
0x3B4 ENABLE_CLR_REG13 Enable Clear Register 13
0x3B8 ENABLE_CLR_REG14 Enable Clear Register 14
0x38C ENABLE_CLR_REG15 Enable Clear Register 15
0x400 CH_MAP_REG0 Interrupt Channel Map Register for 0 to 0+3
0x404 CH_MAP_REG1 Interrupt Channel Map Register for 4 to 4+3
0x408 CH_MAP_REG2 Interrupt Channel Map Register for 8 to 8+3
0x40C CH_MAP_REG3 Interrupt Channel Map Register for 12 to 12+3
0x410 CH_MAP_REG4 Interrupt Channel Map Register for 16 to 16+3
0x414 CH_MAP_REG5 Interrupt Channel Map Register for 20 to 20+3
0x418 CH_MAP_REG6 Interrupt Channel Map Register for 24 to 24+3
0x41C CH_MAP_REG7 Interrupt Channel Map Register for 28 to 28+3
0x420 CH_MAP_REG8 Interrupt Channel Map Register for 32 to 32+3
0x424 CH_MAP_REG9 Interrupt Channel Map Register for 36 to 36+3
0x428 CH_MAP_REG10 Interrupt Channel Map Register for 40 to 40+3
0x42C CH_MAP_REG11 Interrupt Channel Map Register for 44 to 44+3
0x430 CH_MAP_REG12 Interrupt Channel Map Register for 48 to 48+3
0x434 CH_MAP_REG13 Interrupt Channel Map Register for 52 to 52+3
0x438 CH_MAP_REG14 Interrupt Channel Map Register for 56 to 56+3
0x43C CH_MAP_REG15 Interrupt Channel Map Register for 60 to 60+3
0x440 CH_MAP_REG16 Interrupt Channel Map Register for 64 to 64+3
0x444 CH_MAP_REG17 Interrupt Channel Map Register for 68 to 68+3
0x448 CH_MAP_REG18 Interrupt Channel Map Register for 72 to 72+3
0x44C CH_MAP_REG19 Interrupt Channel Map Register for 76 to 76+3
0x450 CH_MAP_REG20 Interrupt Channel Map Register for 80 to 80+3
0x454 CH_MAP_REG21 Interrupt Channel Map Register for 84 to 84+3
0x458 CH_MAP_REG22 Interrupt Channel Map Register for 88 to 88+3
0x45C CH_MAP_REG23 Interrupt Channel Map Register for 92 to 92+3
0x460 CH_MAP_REG24 Interrupt Channel Map Register for 96 to 96+3
0x464 CH_MAP_REG25 Interrupt Channel Map Register for 100 to 100+3
0x468 CH_MAP_REG26 Interrupt Channel Map Register for 104 to 104+3
0x46C CH_MAP_REG27 Interrupt Channel Map Register for 108 to 108+3
0x470 CH_MAP_REG28 Interrupt Channel Map Register for 112 to 112+3
0x474 CH_MAP_REG29 Interrupt Channel Map Register for 116 to 116+3
0x478 CH_MAP_REG30 Interrupt Channel Map Register for 120 to 120+3
0x47C CH_MAP_REG31 Interrupt Channel Map Register for 124 to 124+3
0x480 CH_MAP_REG32 Interrupt Channel Map Register for 128 to 128+3
0x484 CH_MAP_REG33 Interrupt Channel Map Register for 132 to 132+3
0x488 CH_MAP_REG34 Interrupt Channel Map Register for 136 to 136+3
0x48C CH_MAP_REG35 Interrupt Channel Map Register for 140 to 140+3
0x490 CH_MAP_REG36 Interrupt Channel Map Register for 144 to 144+3
0x494 CH_MAP_REG37 Interrupt Channel Map Register for 148 to 148+3
0x498 CH_MAP_REG38 Interrupt Channel Map Register for 152 to 152+3
0x49C CH_MAP_REG39 Interrupt Channel Map Register for 156 to 156+3
0x4A0 CH_MAP_REG40 Interrupt Channel Map Register for 160 to 160+3
0x4A4 CH_MAP_REG41 Interrupt Channel Map Register for 164 to 164+3
0x4A8 CH_MAP_REG42 Interrupt Channel Map Register for 168 to 168+3
0x4AC CH_MAP_REG43 Interrupt Channel Map Register for 172 to 172+3
0x4B0 CH_MAP_REG44 Interrupt Channel Map Register for 176 to 176+3
0x4B4 CH_MAP_REG45 Interrupt Channel Map Register for 180 to 180+3
0x4B8 CH_MAP_REG46 Interrupt Channel Map Register for 184 to 184+3
0x4BC CH_MAP_REG47 Interrupt Channel Map Register for 188 to 188+3
0x4C0 CH_MAP_REG48 Interrupt Channel Map Register for 192 to 192+3
0x4C4 CH_MAP_REG49 Interrupt Channel Map Register for 196 to 196+3
0x4C8 CH_MAP_REG50 Interrupt Channel Map Register for 200 to 200+3
0x4CC CH_MAP_REG51 Interrupt Channel Map Register for 204 to 204+3
0x4D0 CH_MAP_REG52 Interrupt Channel Map Register for 208 to 208+3
0x4D4 CH_MAP_REG53 Interrupt Channel Map Register for 212 to 212+3
0x4D8 CH_MAP_REG54 Interrupt Channel Map Register for 216 to 216+3
0x4DC CH_MAP_REG55 Interrupt Channel Map Register for 220 to 220+3
0x4E0 CH_MAP_REG56 Interrupt Channel Map Register for 224 to 224+3
0x4E4 CH_MAP_REG57 Interrupt Channel Map Register for 228 to 228+3
0x4E8 CH_MAP_REG58 Interrupt Channel Map Register for 232 to 232+3
0x4FC CH_MAP_REG59 Interrupt Channel Map Register for 236 to 236+3
0x4F0 CH_MAP_REG60 Interrupt Channel Map Register for 240 to 240+3
0x4F4 CH_MAP_REG61 Interrupt Channel Map Register for 244 to 244+3
0x4F8 CH_MAP_REG62 Interrupt Channel Map Register for 248 to 248+3
0x4FC CH_MAP_REG63 Interrupt Channel Map Register for 252 to 252+3
0x500 CH_MAP_REG64 Interrupt Channel Map Register for 256 to 256+3
0x504 CH_MAP_REG65 Interrupt Channel Map Register for 260 to 260+3
0x508 CH_MAP_REG66 Interrupt Channel Map Register for 264 to 264+3
0x50C CH_MAP_REG67 Interrupt Channel Map Register for 268 to 268+3
0x510 CH_MAP_REG68 Interrupt Channel Map Register for 272 to 272+3
0x514 CH_MAP_REG69 Interrupt Channel Map Register for 276 to 276+3
0x518 CH_MAP_REG70 Interrupt Channel Map Register for 280 to 280+3
0x51C CH_MAP_REG71 Interrupt Channel Map Register for 284 to 284+3
0x520 CH_MAP_REG72 Interrupt Channel Map Register for 288 to 288+3
0x524 CH_MAP_REG73 Interrupt Channel Map Register for 292 to 292+3
0x528 CH_MAP_REG74 Interrupt Channel Map Register for 296 to 296+3
0x52C CH_MAP_REG75 Interrupt Channel Map Register for 300 to 300+3
0x520 CH_MAP_REG76 Interrupt Channel Map Register for 304 to 304+3
0x524 CH_MAP_REG77 Interrupt Channel Map Register for 308 to 308+3
0x528 CH_MAP_REG78 Interrupt Channel Map Register for 312 to 312+3
0x52C CH_MAP_REG79 Interrupt Channel Map Register for 316 to 316+3
0x530 CH_MAP_REG80 Interrupt Channel Map Register for 320 to 320+3
0x534 CH_MAP_REG81 Interrupt Channel Map Register for 324 to 324+3
0x538 CH_MAP_REG82 Interrupt Channel Map Register for 328 to 328+3
0x53C CH_MAP_REG83 Interrupt Channel Map Register for 332 to332+3
0x540 CH_MAP_REG84 Interrupt Channel Map Register for336 to 336+3
0x544 CH_MAP_REG85 Interrupt Channel Map Register for 340 to 340+3
0x548 CH_MAP_REG86 Interrupt Channel Map Register for 344 to 344+3
0x54C CH_MAP_REG87 Interrupt Channel Map Register for 348 to 348+3
0x550 CH_MAP_REG88 Interrupt Channel Map Register for 352 to 352+3
0x554 CH_MAP_REG89 Interrupt Channel Map Register for 356 to 356+3
0x558 CH_MAP_REG90 Interrupt Channel Map Register for 360 to 360+3
0x55C CH_MAP_REG91 Interrupt Channel Map Register for 364 to 364+3
0x560 CH_MAP_REG92 Interrupt Channel Map Register for 368 to 368+3
0x564 CH_MAP_REG93 Interrupt Channel Map Register for372 to 372+3
0x568 CH_MAP_REG94 Interrupt Channel Map Register for 376 to 376+3
0x56C CH_MAP_REG95 Interrupt Channel Map Register for 380 to 380+3
0x570 CH_MAP_REG96 Interrupt Channel Map Register for 384 to 384+3
0x574 CH_MAP_REG97 Interrupt Channel Map Register for 388 to 388+3
0x578 CH_MAP_REG98 Interrupt Channel Map Register for 392 to 392+3
0x57C CH_MAP_REG99 Interrupt Channel Map Register for 396 to 396+3
0x580 CH_MAP_REG100 Interrupt Channel Map Register for 400 to 400+3
0x584 CH_MAP_REG101 Interrupt Channel Map Register for 404 to 404+3
0x588 CH_MAP_REG102 Interrupt Channel Map Register for 408 to 408+3
0x58C CH_MAP_REG103 Interrupt Channel Map Register for 412 to412+3
0x590 CH_MAP_REG104 Interrupt Channel Map Register for 416 to 416+3
0x594 CH_MAP_REG105 Interrupt Channel Map Register for 420 to 420+3
0x598 CH_MAP_REG106 Interrupt Channel Map Register for 424 to 424+3
0x59C CH_MAP_REG107 Interrupt Channel Map Register for 428 to 428+3
0x5A0 CH_MAP_REG108 Interrupt Channel Map Register for 432 to 432+3
0x5A4 CH_MAP_REG109 Interrupt Channel Map Register for 436 to 436+3
0x5A8 CH_MAP_REG110 Interrupt Channel Map Register for 440 to 440+3
0x5AC CH_MAP_REG111 Interrupt Channel Map Register for 444 to 444+3
0x5B0 CH_MAP_REG112 Interrupt Channel Map Register for 448 to 448+3
0x5B4 CH_MAP_REG113 Interrupt Channel Map Register for 452 to 452+3
0x5B8 CH_MAP_REG114 Interrupt Channel Map Register for 456 to 456+3
0x5BC CH_MAP_REG115 Interrupt Channel Map Register for 460 to 460+3
0x5C0 CH_MAP_REG116 Interrupt Channel Map Register for 464 to 464+3
0x5C4 CH_MAP_REG117 Interrupt Channel Map Register for 468 to 468+3
0x5C8 CH_MAP_REG118 Interrupt Channel Map Register for 472 to 472+3
0x5CC CH_MAP_REG119 Interrupt Channel Map Register for 476 to 476+3
0x5D0 CH_MAP_REG120 Interrupt Channel Map Register for 480 to 480+3
0x5D4 CH_MAP_REG121 Interrupt Channel Map Register for 484 to 484+3
0x5D8 CH_MAP_REG122 Interrupt Channel Map Register for 488 to 488+3
0x5DC CH_MAP_REG123 Interrupt Channel Map Register for 482 to 492+3
0x5E0 CH_MAP_REG124 Interrupt Channel Map Register for 496 to 496+3
0x5E4 CH_MAP_REG125 Interrupt Channel Map Register for 500 to 500+3
0x5E8 CH_MAP_REG126 Interrupt Channel Map Register for 504 to 504+3
0x5EC CH_MAP_REG127 Interrupt Channel Map Register for 508 to 508+3
0x5F0 CH_MAP_REG128 Interrupt Channel Map Register for 512 to 512+3
0x5F4 CH_MAP_REG129 Interrupt Channel Map Register for 516 to 516+3
0x5F8 CH_MAP_REG130 Interrupt Channel Map Register for 520 to 520+3
0x5FC CH_MAP_REG131 Interrupt Channel Map Register for 524 to 524+3
0x600 CH_MAP_REG132 Interrupt Channel Map Register for 528 to 528+3
0x604 CH_MAP_REG133 Interrupt Channel Map Register for 532 to 532+3
0x608 CH_MAP_REG134 Interrupt Channel Map Register for 536 to 536+3
0x60C CH_MAP_REG135 Interrupt Channel Map Register for 540 to 540+3
0x610 CH_MAP_REG136 Interrupt Channel Map Register for 544 to 544+3
0x614 CH_MAP_REG137 Interrupt Channel Map Register for 548 to 548+3
0x618 CH_MAP_REG138 Interrupt Channel Map Register for 552 to 552+3
0x61C CH_MAP_REG139 Interrupt Channel Map Register for 556 to 556+3
0x620 CH_MAP_REG140 Interrupt Channel Map Register for 560 to 560+3
0x624 CH_MAP_REG141 Interrupt Channel Map Register for 564 to 564+3
0x628 CH_MAP_REG142 Interrupt Channel Map Register for 568 to 568+3
0x62C CH_MAP_REG143 Interrupt Channel Map Register for 572 to 572+3
0x630 CH_MAP_REG144 Interrupt Channel Map Register for 576 to 576+3
0x634 CH_MAP_REG145 Interrupt Channel Map Register for 580 to 580+3
0x638 CH_MAP_REG146 Interrupt Channel Map Register for 584 to 584+3
0x63C CH_MAP_REG147 Interrupt Channel Map Register for 588 to 588+3
0x640 CH_MAP_REG148 Interrupt Channel Map Register for 592 to 592+3
0x644 CH_MAP_REG149 Interrupt Channel Map Register for 596 to 596+3
0x648 CH_MAP_REG150 Interrupt Channel Map Register for 600 to 600+3
0x64C CH_MAP_REG151 Interrupt Channel Map Register for 604 to 604+3
0x650 CH_MAP_REG152 Interrupt Channel Map Register for 608 to 608+3
0x654 CH_MAP_REG153 Interrupt Channel Map Register for 612 to 612+3
0x658 CH_MAP_REG154 Interrupt Channel Map Register for 616 to 616+3
0x65C CH_MAP_REG155 Interrupt Channel Map Register for 620 to 620+3
0x660 CH_MAP_REG156 Interrupt Channel Map Register for 624 to 624+3
0x664 CH_MAP_REG157 Interrupt Channel Map Register for 628 to 628+3
0x668 CH_MAP_REG158 Interrupt Channel Map Register for 632 to 632+3
0x66C CH_MAP_REG159 Interrupt Channel Map Register for 636 to 636+3
0x670 CH_MAP_REG160 Interrupt Channel Map Register for 640 to 640+3
0x674 CH_MAP_REG161 Interrupt Channel Map Register for 644 to 644+3
0x678 CH_MAP_REG162 Interrupt Channel Map Register for 648 to 648+3
0x67C CH_MAP_REG163 Interrupt Channel Map Register for 652 to 652+3
0x680 CH_MAP_REG164 Interrupt Channel Map Register for 656 to 656+3
0x684 CH_MAP_REG165 Interrupt Channel Map Register for 660 to 660+3
0x688 CH_MAP_REG166 Interrupt Channel Map Register for 664 to 664+3
0x68C CH_MAP_REG167 Interrupt Channel Map Register for 668 to 668+3
0x690 CH_MAP_REG168 Interrupt Channel Map Register for 672 to 672+3
0x694 CH_MAP_REG169 Interrupt Channel Map Register for 676 to 676+3
0x698 CH_MAP_REG170 Interrupt Channel Map Register for 680 to 680+3
0x69C CH_MAP_REG171 Interrupt Channel Map Register for 684 to 684+3
0x800 HINT_MAP_REG0 Host Interrupt Map Register for 0 to 0+3
0x804 HINT_MAP_REG1 Host Interrupt Map Register for 4 to 4+3
0x808 HINT_MAP_REG2 Host Interrupt Map Register for 8 to 8+3
0x80C HINT_MAP_REG3 Host Interrupt Map Register for 12 to 12+3
0x810 HINT_MAP_REG4 Host Interrupt Map Register for 16 to 16+3
0x814 HINT_MAP_REG5 Host Interrupt Map Register for 20 to 20+3
0x818 HINT_MAP_REG6 Host Interrupt Map Register for 24 to 24+3
0x81C HINT_MAP_REG7 Host Interrupt Map Register for 28 to 28+3
0x820 HINT_MAP_REG8 Host Interrupt Map Register for 32 to 32+3
0x824 HINT_MAP_REG9 Host Interrupt Map Register for 36 to 36+3
0x828 HINT_MAP_REG10 Host Interrupt Map Register for 40 to 40+3
0x82C HINT_MAP_REG11 Host Interrupt Map Register for 44 to 44+3
0x830 HINT_MAP_REG12 Host Interrupt Map Register for 48 to 48+3
0x834 HINT_MAP_REG13 Host Interrupt Map Register for 52 to 52+3
0x1500 ENABLE_HINT_REG0 Host Interrupt Enable Register 0
0x1504 ENABLE_HINT_REG1 Host Interrupt Enable Register 1

8.3.2.3 CIC2 Register Map

Table 8-29 CIC2 Registers

ADDRESS OFFSET REGISTER MNEMONIC REGISTER NAME
0x0 REVISION_REG Revision Register
0x10 GLOBAL_ENABLE_HINT_REG Global Host Int Enable Register
0x20 STATUS_SET_INDEX_REG Status Set Index Register
0x24 STATUS_CLR_INDEX_REG Status Clear Index Register
0x28 ENABLE_SET_INDEX_REG Enable Set Index Register
0x2C ENABLE_CLR_INDEX_REG Enable Clear Index Register
0x34 HINT_ENABLE_SET_INDEX_REG Host Int Enable Set Index Register
0x38 HINT_ENABLE_CLR_INDEX_REG Host Int Enable Clear Index Register
0x200 RAW_STATUS_REG0 Raw Status Register 0
0x204 RAW_STATUS_REG1 Raw Status Register 1
0x208 RAW_STATUS_REG2 Raw Status Register 2
0x20C RAW_STATUS_REG3 Raw Status Register 3
0x210 RAW_STATUS_REG4 Raw Status Register 4
0x214 RAW_STATUS_REG5 Raw Status Register 5
0x218 RAW_STATUS_REG6 Raw Status Register 6
0x21C RAW_STATUS_REG7 Raw Status Register 7
0x220 RAW_STATUS_REG8 Raw Status Register 8
0x224 RAW_STATUS_REG9 Raw Status Register 9
0x228 RAW_STATUS_REG10 Raw Status Register 10
0x22C RAW_STATUS_REG11 Raw Status Register 11
0x230 RAW_STATUS_REG12 Raw Status Register 12
0x234 RAW_STATUS_REG13 Raw Status Register 13
0x238 RAW_STATUS_REG14 Raw Status Register 14
0x23C RAW_STATUS_REG15 Raw Status Register 15
0x280 ENA_STATUS_REG0 Enabled Status Register 0
0x284 ENA_STATUS_REG1 Enabled Status Register 1
0x288 ENA_STATUS_REG2 Enabled Status Register 2
0x28C ENA_STATUS_REG3 Enabled Status Register 3
0x290 ENA_STATUS_REG4 Enabled Status Register 4
0x294 ENA_STATUS_REG5 Enabled Status Register 5
0x298 ENA_STATUS_REG6 Enabled Status Register 6
0x29C ENA_STATUS_REG7 Enabled Status Register 7
0x2A0 ENA_STATUS_REG8 Enabled Status Register 8
0x2A4 ENA_STATUS_REG9 Enabled Status Register 9
0x2A8 ENA_STATUS_REG10 Enabled Status Register10
0x2AC ENA_STATUS_REG11 Enabled Status Register 11
0x2B0 ENA_STATUS_REG12 Enabled Status Register 12
0x2B4 ENA_STATUS_REG13 Enabled Status Register 13
0x2B8 ENA_STATUS_REG14 Enabled Status Register 14
0x2BC ENA_STATUS_REG15 Enabled Status Register 15
0x300 ENABLE_REG0 Enable Register 0
0x304 ENABLE_REG1 Enable Register 1
0x308 ENABLE_REG2 Enable Register 2
0x30C ENABLE_REG3 Enable Register 3
0x310 ENABLE_REG4 Enable Register 4
0x314 ENABLE_REG5 Enable Register 5
0x318 ENABLE_REG6 Enable Register 6
0x31C ENABLE_REG7 Enable Register 7
0x320 ENABLE_REG8 Enable Register 8
0x324 ENABLE_REG9 Enable Register 9
0x328 ENABLE_REG10 Enable Register 10
0x32C ENABLE_REG11 Enable Register 11
0x330 ENABLE_REG12 Enable Register 12
0x334 ENABLE_REG13 Enable Register 13
0x338 ENABLE_REG14 Enable Register 14
0x33C ENABLE_REG15 Enable Register 15
0x380 ENABLE_CLR_REG0 Enable Clear Register 0
0x384 ENABLE_CLR_REG1 Enable Clear Register 1
0x388 ENABLE_CLR_REG2 Enable Clear Register 2
0x38C ENABLE_CLR_REG3 Enable Clear Register 3
0x390 ENABLE_CLR_REG4 Enable Clear Register 4
0x394 ENABLE_CLR_REG5 Enable Clear Register 5
0x398 ENABLE_CLR_REG6 Enable Clear Register 6
0x39C ENABLE_CLR_REG7 Enable Clear Register 7
0x3A0 ENABLE_CLR_REG8 Enable Clear Register 8
0x3A4 ENABLE_CLR_REG9 Enable Clear Register 9
0x3A8 ENABLE_CLR_REG10 Enable Clear Register 10
0x3AC ENABLE_CLR_REG11 Enable Clear Register 11
0x3B0 ENABLE_CLR_REG12 Enable Clear Register 12
0x3B4 ENABLE_CLR_REG13 Enable Clear Register 13
0x3B8 ENABLE_CLR_REG14 Enable Clear Register 14
0x38C ENABLE_CLR_REG15 Enable Clear Register 15
0x400 CH_MAP_REG0 Interrupt Channel Map Register for 0 to 0+3
0x404 CH_MAP_REG1 Interrupt Channel Map Register for 4 to 4+3
0x408 CH_MAP_REG2 Interrupt Channel Map Register for 8 to 8+3
0x40C CH_MAP_REG3 Interrupt Channel Map Register for 12 to 12+3
0x410 CH_MAP_REG4 Interrupt Channel Map Register for 16 to 16+3
0x414 CH_MAP_REG5 Interrupt Channel Map Register for 20 to 20+3
0x418 CH_MAP_REG6 Interrupt Channel Map Register for 24 to 24+3
0x41C CH_MAP_REG7 Interrupt Channel Map Register for 28 to 28+3
0x420 CH_MAP_REG8 Interrupt Channel Map Register for 32 to 32+3
0x424 CH_MAP_REG9 Interrupt Channel Map Register for 36 to 36+3
0x428 CH_MAP_REG10 Interrupt Channel Map Register for 40 to 40+3
0x42C CH_MAP_REG11 Interrupt Channel Map Register for 44 to 44+3
0x430 CH_MAP_REG12 Interrupt Channel Map Register for 48 to 48+3
0x434 CH_MAP_REG13 Interrupt Channel Map Register for 52 to 52+3
0x438 CH_MAP_REG14 Interrupt Channel Map Register for 56 to 56+3
0x43C CH_MAP_REG15 Interrupt Channel Map Register for 60 to 60+3
0x5C0 CH_MAP_REG116 Interrupt Channel Map Register for 464 to 464+3
0x5C4 CH_MAP_REG117 Interrupt Channel Map Register for 468 to 468+3
0x5C8 CH_MAP_REG118 Interrupt Channel Map Register for 472 to 472+3
0x5CC CH_MAP_REG119 Interrupt Channel Map Register for 476 to 476+3
0x5D0 CH_MAP_REG120 Interrupt Channel Map Register for 480 to 480+3
0x5D4 CH_MAP_REG121 Interrupt Channel Map Register for 484 to 484+3
0x5D8 CH_MAP_REG122 Interrupt Channel Map Register for 488 to 488+3
0x5DC CH_MAP_REG123 Interrupt Channel Map Register for 482 to 492+3
0x5E0 CH_MAP_REG124 Interrupt Channel Map Register for 496 to 496+3
0x5E4 CH_MAP_REG125 Interrupt Channel Map Register for 500 to 500+3
0x5E8 CH_MAP_REG126 Interrupt Channel Map Register for 504 to 504+3
0x5EC CH_MAP_REG127 Interrupt Channel Map Register for 508 to 508+3
0x5F0 CH_MAP_REG128 Interrupt Channel Map Register for 512 to 512+3
0x5F4 CH_MAP_REG129 Interrupt Channel Map Register for 516 to 516+3
0x5F8 CH_MAP_REG130 Interrupt Channel Map Register for 520 to 520+3
0x5FC CH_MAP_REG131 Interrupt Channel Map Register for 524 to 524+3
0x600 CH_MAP_REG132 Interrupt Channel Map Register for 528 to 528+3
0x604 CH_MAP_REG133 Interrupt Channel Map Register for 532 to 532+3
0x608 CH_MAP_REG134 Interrupt Channel Map Register for 536 to 536+3
0x60C CH_MAP_REG135 Interrupt Channel Map Register for 540 to 540+3
0x610 CH_MAP_REG136 Interrupt Channel Map Register for 544 to 544+3
0x614 CH_MAP_REG137 Interrupt Channel Map Register for 548 to 548+3
0x618 CH_MAP_REG138 Interrupt Channel Map Register for 552 to 552+3
0x61C CH_MAP_REG139 Interrupt Channel Map Register for 556 to 556+3
0x620 CH_MAP_REG140 Interrupt Channel Map Register for 560 to 560+3
0x624 CH_MAP_REG141 Interrupt Channel Map Register for 564 to 564+3
0x628 CH_MAP_REG142 Interrupt Channel Map Register for 568 to 568+3
0x62C CH_MAP_REG143 Interrupt Channel Map Register for 572 to 572+3
0x630 CH_MAP_REG144 Interrupt Channel Map Register for 576 to 576+3
0x634 CH_MAP_REG145 Interrupt Channel Map Register for 580 to 580+3
0x638 CH_MAP_REG146 Interrupt Channel Map Register for 584 to 584+3
0x63C CH_MAP_REG147 Interrupt Channel Map Register for 588 to 588+3
0x640 CH_MAP_REG148 Interrupt Channel Map Register for 592 to 592+3
0x644 CH_MAP_REG149 Interrupt Channel Map Register for 596 to 596+3
0x648 CH_MAP_REG150 Interrupt Channel Map Register for 600 to 600+3
0x64C CH_MAP_REG151 Interrupt Channel Map Register for 604 to 604+3
0x650 CH_MAP_REG152 Interrupt Channel Map Register for 608 to 608+3
0x654 CH_MAP_REG153 Interrupt Channel Map Register for 612 to 612+3
0x658 CH_MAP_REG154 Interrupt Channel Map Register for 616 to 616+3
0x65C CH_MAP_REG155 Interrupt Channel Map Register for 620 to 620+3
0x660 CH_MAP_REG156 Interrupt Channel Map Register for 624 to 624+3
0x664 CH_MAP_REG157 Interrupt Channel Map Register for 628 to 628+3
0x668 CH_MAP_REG158 Interrupt Channel Map Register for 632 to 632+3
0x66C CH_MAP_REG159 Interrupt Channel Map Register for 636 to 636+3
0x670 CH_MAP_REG160 Interrupt Channel Map Register for 640 to 640+3
0x674 CH_MAP_REG161 Interrupt Channel Map Register for 644 to 644+3
0x678 CH_MAP_REG162 Interrupt Channel Map Register for 648 to 648+3
0x67C CH_MAP_REG163 Interrupt Channel Map Register for 652 to 652+3
0x680 CH_MAP_REG164 Interrupt Channel Map Register for 656 to 656+3
0x684 CH_MAP_REG165 Interrupt Channel Map Register for 660 to 660+3
0x688 CH_MAP_REG166 Interrupt Channel Map Register for 664 to 664+3
0x68C CH_MAP_REG167 Interrupt Channel Map Register for 668 to 668+3
0x690 CH_MAP_REG168 Interrupt Channel Map Register for 672 to 672+3
0x694 CH_MAP_REG169 Interrupt Channel Map Register for 676 to 676+3
0x698 CH_MAP_REG170 Interrupt Channel Map Register for 680 to 680+3
0x69C CH_MAP_REG171 Interrupt Channel Map Register for 684 to 684+3
0x800 HINT_MAP_REG0 Host Interrupt Map Register for 0 to 0+3
0x804 HINT_MAP_REG1 Host Interrupt Map Register for 4 to 4+3
0x808 HINT_MAP_REG2 Host Interrupt Map Register for 8 to 8+3
0x80C HINT_MAP_REG3 Host Interrupt Map Register for 12 to 12+3
0x810 HINT_MAP_REG4 Host Interrupt Map Register for 16 to 16+3
0x814 HINT_MAP_REG5 Host Interrupt Map Register for 20 to 20+3
0x818 HINT_MAP_REG6 Host Interrupt Map Register for 24 to 24+3
0x81C HINT_MAP_REG7 Host Interrupt Map Register for 28 to 28+3
0x820 HINT_MAP_REG8 Host Interrupt Map Register for 32 to 32+3
0x824 HINT_MAP_REG9 Host Interrupt Map Register for 36 to 36+3
0x828 HINT_MAP_REG10 Host Interrupt Map Register for 40 to 40+3
0x82C HINT_MAP_REG11 Host Interrupt Map Register for 44 to 44+3
0x830 HINT_MAP_REG12 Host Interrupt Map Register for 48 to 48+3
0x834 HINT_MAP_REG13 Host Interrupt Map Register for 52 to 52+3
0x838 HINT_MAP_REG14 Host Interrupt Map Register for 56 to 56+3
0x83C HINT_MAP_REG15 Host Interrupt Map Register for 60 to 60+3
0x840 HINT_MAP_REG16 Host Interrupt Map Register for 63 to 63+3
0x844 HINT_MAP_REG17 Host Interrupt Map Register for 66 to 66+3
0x848 HINT_MAP_REG18 Host Interrupt Map Register for 68 to 68+3
0x84C HINT_MAP_REG19 Host Interrupt Map Register for 72 to 72+3
0x850 HINT_MAP_REG20 Host Interrupt Map Register for 76 to 76+3
0x854 HINT_MAP_REG21 Host Interrupt Map Register for 80 to 80+3
0x858 HINT_MAP_REG22 Host Interrupt Map Register for 84 to 84+3
0x85C HINT_MAP_REG23 Host Interrupt Map Register for 88 to 88+3
0x860 HINT_MAP_REG24 Host Interrupt Map Register for 92 to 92+3
0x864 HINT_MAP_REG25 Host Interrupt Map Register for 94 to 94+3
0x868 HINT_MAP_REG26 Host Interrupt Map Register for 96 to 96+3
0x86C HINT_MAP_REG27 Host Interrupt Map Register for 100 to 100+3
0x1500 ENABLE_HINT_REG0 Host Int Enable Register 0
0x1504 ENABLE_HINT_REG1 Host Int Enable Register 1

8.3.3 Inter-Processor Register Map

Table 8-30 IPC Generation Registers (IPCGRx)

ADDRESS START ADDRESS END SIZE REGISTER NAME DESCRIPTION
0x02620200 0x02620203 4B NMIGR0 NMI Event Generation Register for C66x CorePac0
0x02620204 0x02620207 4B NMIGR1 NMI Event Generation Register for C66x CorePac1
0x02620208 0x0262020B 4B NMIGR2 NMI Event Generation Register for C66x CorePac2
0x0262020C 0x0262020F 4B NMIGR3 NMI Event Generation Register for C66x CorePac3
0x02620210 0x02620213 4B NMIGR4 NMI Event Generation Register for C66x CorePac4
0x02620214 0x02620217 4B NMIGR5 NMI Event Generation Register for C66x CorePac5
0x02620218 0x0262021B 4B NMIGR6 NMI Event Generation Register for C66x CorePac6
0x0262021C 0x0262021F 4B NMIGR7 NMI Event Generation Register for C66x CorePac7
0x02620220 0x0262023F 32B Reserved Reserved
0x02620240 0x02620243 4B IPCGR0 IPC Generation Register for C66x CorePac0
0x02620244 0x02620247 4B IPCGR1 IPC Generation Register for C66x CorePac1
0x02620248 0x0262024B 4B IPCGR2 IPC Generation Register for C66x CorePac2
0x0262024C 0x0262024F 4B IPCGR3 IPC Generation Register for C66x CorePac3
0x02620250 0x02620253 4B IPCGR4 IPC Generation Register for C66x CorePac4(1)
0x02620254 0x02620257 4B IPCGR5 IPC Generation Register for C66x CorePac5(1)
0x02620258 0x0262025B 4B IPCGR6 IPC Generation Register for C66x CorePac6(1)
0x0262025C 0x0262025F 4B IPCGR7 IPC Generation Register for C66x CorePac7(1)
0x02620260 0x02620263 4B IPCGR8 IPC Generation Register for ARM CorePac0
0x02620264 0x02620267 4B IPCGR9 IPC Generation Register for ARM CorePac1
0x02620268 0x0262026B 4B IPCGR10 IPC Generation Register for ARM CorePac2(1)
0x0262026C 0x0262026F 4B IPCGR11 IPC Generation Register for ARM CorePac3(1)
0x02620270 0x0262027B 12B Reserved Reserved
0x0262027C 0x0262027F 4B IPCGRH IPC Generation Register for Host
0x02620280 0x02620283 4B IPCAR0 IPC Acknowledgment Register for C66x CorePac0
0x02620284 0x02620287 4B IPCAR1 IPC Acknowledgment Register for C66x CorePac1
0x02620288 0x0262028B 4B IPCAR2 IPC Acknowledgment Register for C66x CorePac2
0x0262028C 0x0262028F 4B IPCAR3 IPC Acknowledgment Register for C66x CorePac3
0x02620290 0x02620293 4B IPCAR4 IPC Acknowledgment Register for C66x CorePac4(1)
0x02620294 0x02620297 4B IPCAR5 IPC Acknowledgment Register for C66x CorePac5(1)
0x02620298 0x0262029B 4B IPCAR6 IPC Acknowledgment Register for C66x CorePac6(1)
0x0262029C 0x0262029F 4B IPCAR7 IPC Acknowledgment Register for C66x CorePac7(1)
0x026202A0 0x026202A3 4B IPCAR8 IPC Acknowledgment Register for ARM CorePac0
0x026202A4 0x026202A7 4B IPCAR9 IPC Acknowledgement Register for ARM CorePac1
0x026202A8 0x026202AB 4B IPCAR10 IPC Acknowledgment Register for ARM CorePac2(1)
0x026202AC 0x026202AF 4B IPCAR11 IPC Acknowledgment Register for ARM CorePac3(1)
0x026202B0 0x026202BB 12B Reserved Reserved
0x026202A0 0x026202BB 28B Reserved Reserved
0x026202BC 0x026202BF 4B IPCARH IPC Acknowledgment Register for host
(1) 66AK2H12/14 only.

8.3.4 NMI and LRESET

The Nonmaskable Interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One NMI pin and one LRESET pin are shared by all eight C66x CorePacs on the device. The CORESEL[3:0] pins can be configured to select between the eight C66x CorePacs available as shown in Table 8-31.

Table 8-31 LRESET and NMI Decoding

CORESEL[3:0] PIN INPUT LRESET PIN INPUT NMI PIN INPUT LRESETNMIEN PIN INPUT RESET MUX BLOCK OUTPUT
XXXX X X 1 No local reset or NMI assertion
0000 0 X 0 Assert local reset to C66x CorePac0
0001 0 X 0 Assert local reset to C66x CorePac1
0010 0 X 0 Assert local reset to C66x CorePac2
0011 0 X 0 Assert local reset to C66x CorePac3
0100 0 X 0 Assert local reset to C66x CorePac4
0101 0 X 0 Assert local reset to C66x CorePac5
0110 0 X 0 Assert local reset to C66x CorePac6
0111 0 X 0 Assert local reset to C66x CorePac7
1XXX 0 X 0 Assert local reset to all C66x CorePacs
0000 1 1 0 Deassert local reset & NMI to C66x CorePac0
0001 1 1 0 Deassert local reset & NMI to C66x CorePac1
0010 1 1 0 Deassert local reset & NMI to C66x CorePac2
0011 1 1 0 Deassert local reset & NMI to C66x CorePac3
0100 1 1 0 Deassert local reset & NMI to C66x CorePac4(1)
0101 1 1 0 Deassert local reset & NMI to C66x CorePac5(1)
0110 1 1 0 Deassert local reset & NMI to C66x CorePac6(1)
0111 1 1 0 Deassert local reset & NMI to C66x CorePac7(1)
1XXX 1 1 0 Deassert local reset & NMI to all C66x CorePacs
0000 1 0 0 Assert NMI to C66x CorePac0
0001 1 0 0 Assert NMI to C66x CorePac1
0010 1 0 0 Assert NMI to C66x CorePac2
0011 1 0 0 Assert NMI to C66x CorePac3
0100 1 0 0 Assert NMI to C66x CorePac4(1)
0101 1 0 0 Assert NMI to C66x CorePac5(1)
0110 1 0 0 Assert NMI to C66x CorePac6(1)
0111 1 0 0 Assert NMI to C66x CorePac7(1)
1XXX 1 0 0 Assert NMI to all C66x CorePacs
(1) 66AK2H12/14 only.

8.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2Hxx

The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (for example, data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals, and offloads data transfers from the device C66x DSP CorePac or the ARM CorePac.

There are five EDMA channel controllers on the device:

  • EDMA3CC0 has two transfer controllers: TPTC0 and TPTC1
  • EDMA3CC1 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
  • EDMA3CC2 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
  • EDMA3CC3 has two transfer controllers: TPTC0 and TPTC1
  • EDMA3CC4 has two transfer controllers: TPTC0 and TPTC1

In the context of this document, TPTCx is associated with EDMA3CCy, and is referred to as EDMA3CCy TPTCx. Each of the transfer controllers has a direct connection to the switch fabric. Section 9.2 lists the peripherals that can be accessed by the transfer controllers.

EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR3A subsystems. The others are used for the remaining traffic.

Each EDMA3 channel controller includes the following features:

  • Fully orthogonal transfer description
    • 3 transfer dimensions:
      • Array (multiple bytes)
      • Frame (multiple arrays)
      • Block (multiple frames)
    • Single event can trigger transfer of array, frame, or entire block
    • Independent indexes on source and destination
  • Flexible transfer definition:
    • Increment or FIFO transfer addressing modes
    • Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no CPU intervention
    • Chaining allows multiple transfers to execute with one event
  • 512 PaRAM entries for all EDMA3CC
    • Used to define transfer context for channels
    • Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
  • 64 DMA channels for all EDMA3CC
    • Manually triggered (CPU writes to channel controller register)
    • External event triggered
    • Chain triggered (completion of one transfer triggers another)
  • 8 Quick DMA (QDMA) channels per EDMA3CCx
    • Used for software-driven transfers
    • Triggered upon writing to a single PaRAM set entry
  • Two transfer controllers and two event queues with programmable system-level priority for EDMA3CC0, EDMA3CC3 and EDMA3CC4
  • Four transfer controllers and four event queues with programmable system-level priority for each of EDMA3CC1 and EDMA3CC2
  • Interrupt generation for transfer completion and error conditions
  • Debug visibility
    • Queue watermarking/threshold allows detection of maximum usage of event queues
    • Error and status recording to facilitate debug

8.4.1 EDMA3 Device-Specific Information

The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases. For most applications increment mode can be used. On the SoC, the EDMA can use constant addressing mode only with the enhanced Viterbi decoder coprocessor (VCP) and the enhanced turbo decoder coprocessor (TCP). Constant addressing mode is not supported by any other peripheral or internal memory in the SoC. Note that increment mode is supported by all peripherals. For more information on these two addressing modes, see the KeyStone Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide.

For the range of memory addresses that includes EDMA3 channel controller (EDMA3CC) control registers and EDMA3 transfer controller (TPTC) control registers, see Section Section 8.1. For memory offsets and other details on EDMA3CC and TPTC Control Register entries, see the KeyStone Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide.

8.4.2 EDMA3 Channel Controller Configuration

Table 8-32 shows the configuration for each of the EDMA3 channel controllers present on the device.

Table 8-32 EDMA3 Channel Controller Configuration

DESCRIPTION EDMA3 CC0 EDMA3 CC1 EDMA3 CC2 EDMA3 CC3 EDMA3 CC4
Number of DMA channels in channel controller 64 64 64 64 64
Number of QDMA channels 8 8 8 8 8
Number of interrupt channels 64 64 64 64 64
Number of PaRAM set entries 512 512 512 512 512
Number of event queues 2 4 4 2 2
Number of transfer controllers 2 4 4 2 2
Memory protection existence Yes Yes Yes Yes Yes
Number of memory protection and shadow regions 8 8 8 8 8

8.4.3 EDMA3 Transfer Controller Configuration

Each transfer controller on the device is designed differently based on considerations like performance requirements, system topology (like main TeraNet bus width, external memory bus width), and so forth. The parameters that determine the transfer controller configurations are:

  • FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data. The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
  • BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller, respectively. This is typically equal to the bus width of the main TeraNet interface.
  • Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a transfer controller.
  • DSTREGDEPTH: This determines the number of destination FIFO register sets. The number of destination FIFO register sets for a transfer controller determines the maximum number of outstanding transfer requests.

All four parameters listed above are fixed by the design of the device.

Table 8-33 shows the configuration of each of the EDMA3 transfer controllers present on the device.

Table 8-33 EDMA3 Transfer Controller Configuration

PARAMETER EDMA3 CC0/CC4 EDMA3 CC1 EDMA3 CC2 EDMA3CC3
TC0 TC1 TC0 TC1 TC2 TC3 TC0 TC1 TC2 TC3 TC0 TC1
FIFOSIZE 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes
BUSWIDTH 32 bytes 32 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes
DSTREGDEPTH 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries
DBS 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 128 bytes 64 bytes 64 bytes

8.4.4 EDMA3 Channel Synchronization Events

The EDMA3 supports up to 64 DMA channels for all EDMA3CC that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. The following tables list the source of the synchronization event associated with each of the EDMA3CC DMA channels. On the 66AK2Hxx, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.

For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, and so forth, see the KeyStone Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide.

Table 8-34 EDMA3CC0 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 TIMER_8_INTL Timer interrupt low
1 TIMER_8_INTH Timer interrupt high
2 TIMER_9_INTL Timer interrupt low
3 TIMER_9_INTH Timer interrupt high
4 TIMER_10_INTL Timer interrupt low
5 TIMER_10_INTH Timer interrupt high
6 TIMER_11_INTL Timer interrupt low
7 TIMER_11_INTH Timer interrupt high
8 CIC_2_OUT66 CIC2 Interrupt Controller output
9 CIC_2_OUT67 CIC2 Interrupt Controller output
10 CIC_2_OUT68 CIC2 Interrupt Controller output
11 CIC_2_OUT69 CIC2 Interrupt Controller output
12 CIC_2_OUT70 CIC2 Interrupt Controller output
13 CIC_2_OUT71 CIC2 Interrupt Controller output
14 CIC_2_OUT72 CIC2 Interrupt Controller output
15 CIC_2_OUT73 CIC2 Interrupt Controller output
16 GPIO_INT8 GPIO interrupt
17 GPIO_INT9 GPIO interrupt
18 GPIO_INT10 GPIO interrupt
19 GPIO_INT11 GPIO interrupt
20 GPIO_INT12 GPIO interrupt
21 GPIO_INT13 GPIO interrupt
22 GPIO_INT14 GPIO interrupt
23 GPIO_INT15 GPIO interrupt
24 TIMER_4_INTL Timer interrupt low(1)
25 TIMER_4_INTH Timer interrupt high(1)
26 TIMER_5_INTL Timer interrupt low(1)
27 TIMER_5_INTH Timer interrupt high(1)
28 TIMER_6_INTL Timer interrupt low(1)
29 TIMER_6_INTH Timer interrupt high(1)
30 TIMER_7_INTL Timer interrupt low(1)
31 TIMER_7_INTH Timer interrupt high(1)
32 GPIO_INT0 GPIO interrupt
33 GPIO_INT1 GPIO interrupt
34 GPIO_INT2 GPIO interrupt
35 GPIO_INT3 GPIO interrupt
36 GPIO_INT4 GPIO interrupt
37 GPIO_INT5 GPIO interrupt
38 GPIO_INT6 GPIO interrupt
39 GPIO_INT7 GPIO interrupt
40 TIMER_0_INTL Timer interrupt low
41 TIMER_0_INTH Timer interrupt high
42 TIMER_1_INTL Timer interrupt low
43 TIMER_1_INTH Timer interrupt high
44 TIMER_2_INTL Timer interrupt low
45 TIMER_2_INTH Timer interrupt high
46 TIMER_3_INTL Timer interrupt low
47 TIMER_3_INTH Timer interrupt high
48 SRIO_INTDST0 SRIO interrupt
49 SRIO_INTDST1 SRIO interrupt
50 SRIO_INTDST2 SRIO interrupt
51 SRIO_INTDST3 SRIO interrupt
52 SRIO_INTDST4 SRIO interrupt
53 SRIO_INTDST5 SRIO interrupt
54 SRIO_INTDST6 SRIO interrupt
55 SRIO_INTDST7 SRIO interrupt
56 Reserved Reserved
57 Reserved Reserved
58 Reserved Reserved
59 Reserved Reserved
60 Reserved Reserved
61 Reserved Reserved
62 Reserved Reserved
63 Reserved Reserved
(1) 66AK2H12/14 only.

Table 8-35 EDMA3CC1 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 SPI_0_INT0 SPI0 interrupt
1 SPI_0_INT1 SPI0 interrupt
2 SPI_0_XEVT SPI0 transmit event
3 SPI_0_REVT SPI0 receive event
4 SEM_INT8 Semaphore interrupt
5 SEM_INT9 Semaphore interrupt
6 GPIO_INT0 GPIO interrupt
7 GPIO_INT1 GPIO interrupt
8 GPIO_INT2 GPIO interrupt
9 GPIO_INT3 GPIO interrupt
10 Reserved Reserved
11 Reserved Reserved
12 Reserved Reserved
13 Reserved Reserved
14 SEM_INT0 Semaphore interrupt
15 SEM_INT1 Semaphore interrupt
16 SEM_INT2 Semaphore interrupt
17 SEM_INT3 Semaphore interrupt
18 SEM_INT4 Semaphore interrupt
19 SEM_INT5 Semaphore interrupt
20 SEM_INT6 Semaphore interrupt
21 SEM_INT7 Semaphore interrupt
22 TIMER_8_INTL Timer interrupt low
23 TIMER_8_INTH Timer interrupt high
24 TIMER_9_INTL Timer interrupt low
25 TIMER_9_INTH Timer interrupt high
26 TIMER_10_INTL Timer interrupt low
27 TIMER_10_INTH Timer interrupt high
28 TIMER_11_INTL Timer interrupt low
29 TIMER_11_INTH Timer interrupt high
30 TIMER_12_INTL Timer interrupt low
31 TIMER_12_INTH Timer interrupt high
32 TIMER_13_INTL Timer interrupt low
33 TIMER_13_INTH Timer interrupt high
34 TIMER_14_INTL Timer interrupt low
35 TIMER_14_INTH Timer interrupt high
36 TIMER_15_INTL Timer interrupt low
37 TIMER_15_INTH Timer interrupt high
38 SEM_INT10 Semaphore interrupt
39 SEM_INT11 Semaphore interrupt
40 SEM_INT12 Semaphore interrupt
41 SEM_INT13 Semaphore interrupt
42 CIC_2_OUT0 CIC2 Interrupt Controller output
43 CIC_2_OUT1 CIC2 Interrupt Controller output
44 CIC_2_OUT2 CIC2 Interrupt Controller output
45 CIC_2_OUT3 CIC2 Interrupt Controller output
46 CIC_2_OUT4 CIC2 Interrupt Controller output
47 CIC_2_OUT5 CIC2 Interrupt Controller output
48 CIC_2_OUT6 CIC2 Interrupt Controller output
49 CIC_2_OUT7 CIC2 Interrupt Controller output
50 CIC_2_OUT8 CIC2 Interrupt Controller output
51 Reserved Reserved
52 Reserved Reserved
53 I2C_0_REVT I2C0 receive
54 I2C_0_XEVT I2C0 transmit
55 CIC_2_OUT13 CIC2 Interrupt Controller output
56 CIC_2_OUT14 CIC2 Interrupt Controller output
57 CIC_2_OUT15 CIC2 Interrupt Controller output
58 CIC_2_OUT16 CIC2 Interrupt Controller output
59 CIC_2_OUT17 CIC2 Interrupt Controller output
60 CIC_2_OUT18 CIC2 Interrupt Controller output
61 CIC_2_OUT19 CIC2 Interrupt Controller output
62 Reserved Reserved
63 Reserved Reserved

Table 8-36 EDMA3CC2 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 Reserved Reserved
1 Reserved Reserved
2 Reserved Reserved
3 Reserved Reserved
4 Reserved Reserved
5 Reserved Reserved
6 TETB_FULLINT4 TETB4 is full
7 TETB_HFULLINT4 TETB4 is half full
8 TETB_FULLINT5 TETB5 is full
9 TETB_HFULLINT5 TETB5 is half full
10 TETB_FULLINT6 TETB6 is full
11 TETB_HFULLINT6 TETB6 is half full
12 TETB_FULLINT7 TETB7 is full
13 TETB_HFULLINT7 TETB7 is half full
14 SRIO_INTDST0 SRIO interrupt
15 SRIO_INTDST1 SRIO interrupt
16 SRIO_INTDST2 SRIO interrupt
17 SRIO_INTDST3 SRIO interrupt
18 SRIO_INTDST4 SRIO interrupt
19 SRIO_INTDST5 SRIO interrupt
20 SRIO_INTDST6 SRIO interrupt
21 SRIO_INTDST7 SRIO interrupt
22 Reserved Reserved
23 Reserved Reserved
24 Reserved Reserved
25 Reserved Reserved
26 GPIO_INT0 GPIO interrupt
27 GPIO_INT1 GPIO interrupt
28 GPIO_INT2 GPIO interrupt
29 GPIO_INT3 GPIO interrupt
30 GPIO_INT4 GPIO interrupt
31 GPIO_INT5 GPIO interrupt
32 GPIO_INT6 GPIO interrupt
33 GPIO_INT7 GPIO interrupt
34 Reserved Reserved
35 Reserved Reserved
36 Reserved Reserved
37 Reserved Reserved
38 CIC_2_OUT48 CIC2 Interrupt Controller output
39 Reserved Reserved
40 UART_0_URXEVT UART0 receive event
41 UART_0_UTXEVT UART0 transmit event
42 CIC_2_OUT22 CIC2 Interrupt Controller output
43 CIC_2_OUT23 CIC2 Interrupt Controller output
44 CIC_2_OUT24 CIC2 Interrupt Controller output
45 CIC_2_OUT25 CIC2 Interrupt Controller output
46 CIC_2_OUT26 CIC2 Interrupt Controller output
47 CIC_2_OUT27 CIC2 Interrupt Controller output
48 CIC_2_OUT28 CIC2 Interrupt Controller output
49 SPI_0_XEVT SPI0 transmit event
50 SPI_0_REVT SPI0 receive event
51 Reserved Reserved
52 Reserved Reserved
53 Reserved Reserved
54 Reserved Reserved
55 Reserved Reserved
56 Reserved Reserved
57 Reserved Reserved
58 Reserved Reserved
59 Reserved Reserved
60 Reserved Reserved
61 Reserved Reserved
62 Reserved Reserved
63 Reserved Reserved

Table 8-37 EDMA3CC3 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 SPI_2_INT0 SPI2 interrupt
1 SPI_2_INT1 SPI2 interrupt
2 SPI_2_XEVT SPI2 transmit event
3 SPI_2_REVT SPI2 receive event
4 I2C_2_REVT I2C2 receive
5 I2C_2_XEVT I2C2 transmit
6 UART_1_URXEVT UART1 receive event
7 UART_1_UTXEVT UART1 transmit event
8 SPI_1_INT0 SPI1 interrupt
9 SPI_1_INT1 SPI1 interrupt
10 SPI_1_XEVT SPI1 transmit event
11 SPI_1_REVT SPI1 receive event
12 I2C_0_REVT I2C0 receive
13 I2C_0_XEVT I2C0 transmit
14 I2C_1_REVT I2C1 receive
15 I2C_1_XEVT I2C1 transmit
16 SRIO_INTDST0 SRIO interrupt
17 SRIO_INTDST1 SRIO interrupt
18 SRIO_INTDST2 SRIO interrupt
19 SRIO_INTDST3 SRIO interrupt
20 SRIO_INTDST4 SRIO interrupt
21 SRIO_INTDST5 SRIO interrupt
22 SRIO_INTDST6 SRIO interrupt
23 SRIO_INTDST7 SRIO interrupt
24 Reserved Reserved
25 Reserved Reserved
26 Reserved Reserved
27 Reserved Reserved
28 Reserved Reserved
29 Reserved Reserved
30 Reserved Reserved
31 Reserved Reserved
32 TETB_FULLINT0 TETB0 is full
33 TETB_HFULLINT0 TETB0 is half full
34 TETB_FULLINT1 TETB1 is full
35 TETB_HFULLINT1 TETB1 is half full
36 TETB_FULLINT2 TETB2 is full
37 TETB_HFULLINT2 TETB2 is half full
38 TETB_FULLINT3 TETB3 is full
39 TETB_HFULLINT3 TETB3 is half full
40 Reserved Reserved
41 Reserved Reserved
42 Reserved Reserved
43 Reserved Reserved
44 Reserved Reserved
45 Reserved Reserved
46 Reserved Reserved
47 Reserved Reserved
48 Reserved Reserved
49 Reserved Reserved
50 Reserved Reserved
51 Reserved Reserved
52 Reserved Reserved
53 Reserved Reserved
54 Reserved Reserved
55 Reserved Reserved
56 CIC_2_OUT57 CIC2 Interrupt Controller output
57 CIC_2_OUT50 CIC2 Interrupt Controller output
58 CIC_2_OUT51 CIC2 Interrupt Controller output
59 CIC_2_OUT52 CIC2 Interrupt Controller output
60 CIC_2_OUT53 CIC2 Interrupt Controller output
61 CIC_2_OUT54 CIC2 Interrupt Controller output
62 CIC_2_OUT55 CIC2 Interrupt Controller output
63 CIC_2_OUT56 CIC2 Interrupt Controller output

Table 8-38 EDMA3CC4 Events for 66AK2Hxx

EVENT NO. EVENT NAME DESCRIPTION
0 GPIO_INT16 GPIO interrupt
1 GPIO_INT17 GPIO interrupt
2 GPIO_INT18 GPIO interrupt
3 GPIO_INT19 GPIO interrupt
4 GPIO_INT20 GPIO interrupt
5 GPIO_INT21 GPIO interrupt
6 GPIO_INT22 GPIO interrupt
7 GPIO_INT23 GPIO interrupt
8 Reserved Reserved
9 Reserved Reserved
10 Reserved Reserved
11 Reserved Reserved
12 Reserved Reserved
13 Reserved Reserved
14 Reserved Reserved
15 Reserved Reserved
16 Reserved Reserved
17 Reserved Reserved
18 Reserved Reserved
19 Reserved Reserved
20 Reserved Reserved
21 Reserved Reserved
22 Reserved Reserved
23 Reserved Reserved
24 TIMER_8_INTL Timer interrupt low
25 TIMER_8_INTH Timer interrupt high
26 TIMER_14_INTL Timer interrupt low
27 TIMER_14_INTH Timer interrupt high
28 TIMER_15_INTL Timer interrupt low
29 TIMER_15_INTH Timer interrupt high
30 DBGTBR_DMAINT Debug trace buffer (TBR) DMA event
31 ARM_TBR_DMA ARM trace buffer (TBR) DMA event
32 QMSS_QUE_PEND_658 Navigator transmit queue pending event for indicated queue
33 QMSS_QUE_PEND_659 Navigator transmit queue pending event for indicated queue
34 QMSS_QUE_PEND_660 Navigator transmit queue pending event for indicated queue
35 QMSS_QUE_PEND_661 Navigator transmit queue pending event for indicated queue
36 QMSS_QUE_PEND_662 Navigator transmit queue pending event for indicated queue
37 QMSS_QUE_PEND_663 Navigator transmit queue pending event for indicated queue
38 QMSS_QUE_PEND_664 Navigator transmit queue pending event for indicated queue
39 QMSS_QUE_PEND_665 Navigator transmit queue pending event for indicated queue
40 QMSS_QUE_PEND_8736 Navigator transmit queue pending event for indicated queue
41 QMSS_QUE_PEND_8737 Navigator transmit queue pending event for indicated queue
42 QMSS_QUE_PEND_8738 Navigator transmit queue pending event for indicated queue
43 QMSS_QUE_PEND_8739 Navigator transmit queue pending event for indicated queue
44 QMSS_QUE_PEND_8740 Navigator transmit queue pending event for indicated queue
45 QMSS_QUE_PEND_8741 Navigator transmit queue pending event for indicated queue
46 QMSS_QUE_PEND_8742 Navigator transmit queue pending event for indicated queue
47 QMSS_QUE_PEND_8743 Navigator transmit queue pending event for indicated queue
48 ARM_NCNTVIRQ3 ARM virtual timer interrupt for core 3
49 ARM_NCNTVIRQ2 ARM virtual timer interrupt for core 2
50 ARM_NCNTVIRQ1 ARM virtual timer interrupt for core 1
51 ARM_NCNTVIRQ0 ARM virtual timer interrupt for core 0
52 ARM_NCNTPNSIRQ3 ARM non secure timer interrupt for core 3
53 ARM_NCNTPNSIRQ2 ARM non secure timer interrupt for core 2
54 ARM_NCNTPNSIRQ1 ARM non secure timer interrupt for core 1
55 ARM_NCNTPNSIRQ0 ARM non secure timer interrupt for core 0
56 CIC_2_OUT82 CIC2 Interrupt Controller output
57 CIC_2_OUT83 CIC2 Interrupt Controller output
58 CIC_2_OUT84 CIC2 Interrupt Controller output
59 CIC_2_OUT85 CIC2 Interrupt Controller output
60 CIC_2_OUT86 CIC2 Interrupt Controller output
61 CIC_2_OUT87 CIC2 Interrupt Controller output
62 CIC_2_OUT88 CIC2 Interrupt Controller output
63 CIC_2_OUT89 CIC2 Interrupt Controller output