74AC11138 3-Line to 8-Line Decoder/Demultiplexer

1 Features

Designed specifically for high-speed memory decoders and data transmission systems
Incorporates three enable inputs to simplify cascading and/or data reception
Center-Pin V_CC and GND configurations minimize high-speed switching noise
EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm process
500-mA typical latch-up immunity at 125 °C
Package options include plastic small-outline (D) and thin shrink small-outline (PW) packages, and standard plastic 300-mil DIPs (N)

2 Description

The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times.

Package Information

PART NUMBER	PACKAGE⁽¹⁾	PACKAGE SIZE⁽²⁾	BODY SIZE (NOM)⁽³⁾
74AC11138	D (SOIC, 16)	9.9mm × 6mm	9.9mm × 3.9mm
	N (PDIP, 16)	19.3mm x 9.4mm	19.3mm x 6.35mm
	NS (SOP, 16)	10.2mm x 7.8mm	10.3mm x 5.3mm
	PW (TSSOP, 16)	5.00mm x 6.4mm	5.00mm x 4.4mm

(1) For more information, see Section 10.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.

(3) The body size (length × width) is a nominal value and does not include pins.

Logic Diagram (Positive Logic)

3 Pin Configuration and Functions

74AC11138 D, N, or PW Package (Top
View)

Figure 3-1 D, N, or PW Package (Top View)

Table 3-1 Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
Y1	1	O	Data output Y1
Y2	2	O	Data output Y2
Y3	3	O	Data output Y3
GND	4	-	Ground
Y4	5	O	Data output Y4
Y5	6	O	Data output Y5
Y6	7	O	Data output Y6
Y7	8	O	Data output Y7
G2B	9	I	Input enable, active low
G2A	10	I	Input enable, active low
G1	11	I	Input enable, active high
VCC	12	-	Supply
C	13	I	Select input C
B	14	I	Select input B
A	15	I	Select input A
Y0	16	O	Data output Y0

Figure 3-2 Pin Functions