74AC11138 3-Line to 8-Line Decoder/Demultiplexer

1 Features

Designed specifically for high-speed memory decoders and data transmission systems
Incorporates three enable inputs to simplify cascading and/or data reception
Center-Pin V_CC and GND configurations minimize high-speed switching noise
EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm process
500-mA typical latch-up immunity at 125 °C
Package options include plastic small-outline (D) and thin shrink small-outline (PW) packages, and standard plastic 300-mil DIPs (N)