SNOSBI1C November   2009  – June 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Operating Ratings
    6. 6.6 Electrical Characteristics
    7. 6.7 AC Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Tri-State Test Circuits and Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Understanding ADC Error Specs
      2. 8.3.2 Digital Control Inputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 Analog Input Modes
        1. 8.4.1.1 Normal Mode
        2. 8.4.1.2 Fault Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Testing the ADC Converter
      2. 9.1.2 Microprocessor Interfacing
        1. 9.1.2.1 Interfacing 8080 Microprocessor Derivatives (8048, 8085)
        2. 9.1.2.2 Sample 8080A CPU Interfacing Circuitry and Program
        3. 9.1.2.3 INS8048 Interface
        4. 9.1.2.4 Interfacing the Z-80
        5. 9.1.2.5 Interfacing 6800 Microprocessor Derivatives (6502, etc.)
    2. 9.2 Typical Applications
      1. 9.2.1 8080 Interface
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Analog Differential Voltage Inputs and Common-Mode Rejection
          2. 9.2.1.2.2 Analog Inputs — Input Current
            1. 9.2.1.2.2.1 Input Bypass Capacitors
            2. 9.2.1.2.2.2 Input Source Resistance
            3. 9.2.1.2.2.3 Noise
          3. 9.2.1.2.3 Reference Voltage
            1. 9.2.1.2.3.1 Span Adjust
            2. 9.2.1.2.3.2 Reference Accuracy Requirements
          4. 9.2.1.2.4 Errors and Reference Voltage Adjustments
            1. 9.2.1.2.4.1 Zero Error
            2. 9.2.1.2.4.2 Full-Scale
            3. 9.2.1.2.4.3 Adjusting for an Arbitrary Analog Input Voltage Range
          5. 9.2.1.2.5 Clocking Option
          6. 9.2.1.2.6 Restart During a Conversion
          7. 9.2.1.2.7 Continuous Conversions
          8. 9.2.1.2.8 Driving the Data Bus
          9. 9.2.1.2.9 Wiring and Hook-Up Precautions
      2. 9.2.2 Multiple ADC0801 Series to MC6800 CPU Interface
      3. 9.2.3 Auto-Zeroed Differential Transducer Amplifier and ADC Converter
      4. 9.2.4 Multiple ADC Converters in a Z-80 Interrupt Driven Mode
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

All logic signal wires and leads should be grouped and kept as far away as possible from the analog signal leads. Exposed leads to the analog inputs can cause undesired digital noise and 60-Hz pickup. Shielded leads for the analog inputs may be required in sensitive applications. A single-point analog ground should be used that is also separated from the logic ground points. The power supply bypass capacitor should be returned to digital ground. Any VREF/2 bypass capacitors, analog input filter capacitors, or input signal shielding should be returned to the analog ground point. A test for proper grounding is to measure the zero error of the ADC converter. Zero errors in excess of 1/4 LSB is generally traceable to improper PCB layout and/or wiring.

To minimize potential offset issues, TI recommends to route the signal traces differentially next to each other so that they will see the same thermal gradients and the same number of feedthroughs. Furthermore, inductance is determined by the size of the loop of current. Providing a path for return currents next to the signal trace will reduce the inductance. A solid ground plane is very advantageous in this regard. Ensure to minimize the loop area formed by the bypass capacitor connection between VCC and ground. The ground pin should be connected to the PCB ground plane at the pin of the device.