Setting this bit causes a full reset of the chip and all SPI registers (including CONFIG_A). This bit is self-clearing. After writing this bit, the part may take up to 750ns to reset. During this time, do not perform any SPI transactions.

0 : Address is decremented during streaming reads/writes
1 : Address is incremented during streaming reads/writes (default)

Always returns 1. Always use SDO for SPI reads.
No SDIO mode supported.

0 : Normal operation (default)
1 : Reserved
2 : Reserved
3 : Power down (lowest power, slower resume)

Always returns 0x3, indicating that the part is a high speed ADC.

Returns 0x0021 indicating the device is in the ADCrrDJssssRF family.

Always returns 0x0451 (Vendor ID for Texas Instruments)

0 : Use ASCEND register to select address ascend/descend mode (default)
1 : Address stays constant throughout streaming operation; useful for reading and writing calibration vector information at the CAL_DATA register

This bit enables the SYSREF processor, which allows the device to process SYSREF events (default: disabled). SYSREF_RECV_EN must be set before setting SYSREF_PROC_EN.

Set this bit to enable the SYSREF receiver circuit (default: disabled)

Set this bit to zoom in the SYSREF windowing status and delays (impacts SYSERF_POS and SYSREF_SEL). When set, the delays used in the SYSREF windowing feature (reported in the SYSREF_POS register) become smaller. Use SYSREF_ZOOM for high clock rates, specifically when multiple SYSREF valid windows are encountered in the SYSREF_POS register; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section.

Set this field to select which SYSREF delay to use. Set this field based on the results returned by SYSREF_POS; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section. These bits must be set to 0 to use SYSREF calibration; see the Automatic SYSREF Calibration section.

The SYSREF signal can be observed on the LSB of the JESD204C output samples when SYSREF_TIMESTAMP_EN and TIME_STAMP_EN are both set. This bit allows SYSREF± to be used as the timestamp input.

Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin Functions table.

Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the Pin Functions table.

This bit inverts the SYSREF signal used for alignment.

Adjustable feedback gain for CMLtoCMOS converter (high gain:1)

Reserved

When set, noise on VA11 is suppressed. It is recommended to have this set, as it reduces noise coupling from the digital circuits to analog clock, at the expense of a small increase in power.

Adjustable delay for the sampling clock (one hot encoded)

Returns a 24-bit status value that indicates the position of the SYSREF edge with respect to CLK±. Use this to program SYSREF_SEL.

These bits enable adjustment of the analog full-scale range for INA±.
0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting

These bits enable adjustment of the analog full-scale range for INB±.
0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting

When set, VA11 is used as the voltage reference instead of the band-gap voltage.

When set, activates the low voltage PECL mode for the differential TMSTP± input.

Enables the differential differential TMSTP± input.

Sets the pre-emphasis for the SerDes output lanes. Pre-emphasis can be used to compensate for the high-frequency loss of the PCB trace. This is a global setting that affects all 16 lanes (DA[7:0]±, DB[7:0]±).

Select inputs for dual channel modes. If JMODE is selecting a single channel mode, this register has no effect.
0: A channel samples INA±, B channel samples INB± (no swap) (default)
1: A channel samples INB±, B channel samples INA± (swap)

Defines which input is sampled in single channel mode. If JMODE is not selecting a single channel mode, this register has no effect.
0: RESERVED
1: INA± is used (default)
2: INB± is used
3: ADC channel A samples INA± and ADC channel B samples INB± (DUAL DES mode). A calibration needs to be performance after switching the input mux for the changes to take effect.

Calibration Enable. Set high to run calibration. Set low to hold calibration in reset to program new calibration settings. Clearing CAL_EN also resets the clock dividers that clock the digital block and JESD204C interface.

Some calibration registers require clearing CAL_EN before making any changes. All registers with this requirement contain a note in their descriptions. After changing the registers, set CAL_EN to re-run calibration with the new settings. Always set CAL_EN before setting JESD_EN. Always clear JESD_EN before clearing CAL_EN.

0 : Disable background offset calibration (default)
1 : Enable background offset calibration (requires CAL_BG to be set).

0 : Disable foreground offset calibration (default)
1 : Enable foreground offset calibration (requires CAL_FG to be set).

0 : Disable background calibration (default)
1 : Enable background calibration

0 : Reset calibration values, skip foreground calibration.
1 : Reset calibration values, then run foreground calibration (default).

0 : ADC0 (ADC1 will stand in for ADC0)

1 : ADC1

2 : ADC2 (ADC1 will stand in for ADC2)

Select the amount of averaging used for the offset correction routine. A larger number corresponds to more averaging.

Select the amount of averaging used for the linearity calibration routine. A larger number corresponds to more averaging.

Calibration status code

This bit returns a 1 when background calibration is successfully stopped at the requested phase. This bit returns a 0 when calibration starts operating again. If background calibration is disabled, this bit is set when foreground calibration is completed or skipped.

This bit is high to indicate that foreground calibration has completed (or was skipped).

0 : CALSTAT output matches FG_DONE.
1 : CALSTAT output matches CAL_STOPPED.
2 : CALSTAT output matches ALARM.
3 : CALSTAT output is always low.

This bit selects the hardware or software trigger source.
0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The CALTRIG input is disabled (ignored).
1 : Use the CALTRIG input for the calibration trigger. The CAL_SOFT_TRIG register is ignored.

CAL_SOFT_TRIG is a software bit to provide the functionality of the CALTRIG input pin when there are no hardware resources to drive CALTRIG. Program CAL_TRIG_EN=0 to use CAL_SOFT_TRIG for the calibration trigger.
Note: If no calibration trigger is needed, leave CAL_TRIG_EN=0 and CAL_SOFT_TRIG=1 (trigger set high).

These bits adjust how long an ADC sleeps before waking for calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values below 4 are not recommended because of limited overall power reduction benefits.
0: Sleep delay = (23 + 1) × 256 × tCLK
1: Sleep delay = (215 + 1) × 256 × tCLK
2: Sleep delay = (218 + 1) × 256 × tCLK
3: Sleep delay = (221 + 1) × 256 × tCLK
4: Sleep delay = (224 + 1) × 256 × tCLK (default, approximately 1.338 seconds with a 3.2-GHz clock)
5: Sleep delay = (227 + 1) × 256 × tCLK
6: Sleep delay = (230 + 1) × 256 × tCLK
7: Sleep delay = (233 + 1) × 256 × tCLK

These bits adjust how much time is provided for settling before calibrating an ADC after the ADC wakes up (only applies when LP_EN = 1). Values lower than 1 are not recommended because there is insufficient time for the core to stabilize before calibration begins.
0: Wake delay = (23 + 1) × 256 × tCLK
1: Wake delay = (218 + 1) × 256 × tCLK (default, approximately 21 ms with a 3.2-GHz clock)
2: Wake delay = (221 + 1) × 256 × tCLK
3: Wake delay = (224 + 1) × 256 × tCLK

0 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous mode).
1 : ADCs sleep until awoken by a trigger. An ADC is awoken when the calibration trigger is low.

0 : Disable low-power background calibration (default)
1 : Enable low-power background calibration (only applies when CAL_BG=1).

Set this bit to enable the CAL_DATA register to enable reading and writing of calibration data; see the CAL_DATA register for more information.

After setting CAL_DATA_EN, repeated reads of this register return all calibration values for the ADCs. Repeated writes of this register input all calibration values for the ADCs. To read the calibration data, read the register 673 times. To write the vector, write the register 673 times with previously stored calibration data. To speed up the read or write operation, set ADDR_HOLD = 1 and use streaming read or write process.

IMPORTANT: Accessing the CAL_DATA register when CAL_STOPPED = 0 corrupts the calibration. Also, stopping the process before reading or writing 673 times leaves the calibration data in an invalid state.

This register enables gain trim of INA±. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_A to adjust the analog full-scale voltage (Vfs) of INA±.

This register enables gain trim of INB±. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_B to adjust the analog full-scale voltage (Vfs) of INB±.

This register enables trimming of the internal band-gap reference. After reset, the factory trimmed value can be read and adjusted as required.

This register controls the INA± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

This register controls the INB± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

Small rounding errors may occur when subtracting the dither signal. The error can be chosen to either slightly degrade SNR or to slightly increase the DC offset and FS/2 spur. In addition, the FS/4 spur will also be increased slightly while in single channel mode.
0 : Rounding error degrades SNR
1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur

0 : Small dither for better SNR (default)
1 : Large dither for better spurious performance

Set this bit to enable ADC dither. Dither can improve spurious performance at the expense of slightly degraded SNR. The dither amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR and spurious performance.

When set, the timestamp signal is transmitted on the LSB of the output samples. The latency of the timestamp signal (through the entire chip) matches the latency of the analog ADC inputs. Also set SYNC_RECV_EN when using TIME_STAMP_EN.

Note 1: The control bit is placed on the LSB of the 8-bit samples (leaving 7-bits of sample data).
Note 2: The control bit that is enabled by this register is never advertised in the ILA (CS is 0 in the ILA).

0 : Disable JESD204C interface
1 : Enable JESD204C interface

Note: Before altering other JESD204C registers, you must clear JESD_EN. When JESD_EN is 0, the block is held in reset and the serializers are powered down. The clocks are gated off to save power. The LMFC/LEMC counter is also held in reset, so SYSREF will not align the LMFC/LEMC.

Note 2: Always set CAL_EN before setting JESD_EN.
Note 3: Always clear JESD_EN before clearing CAL_EN.

K is the number of frames per multiframe and this register must be programmed as K-1. Depending on the JMODE setting, there are constraints on the legal values of K (see KR).
The default values is KM1=31, which corresponds to K=32.

Note: For modes using the 64b/66b link layer, the KM1 register is ignored and the value of K is determined from JMODE. The effective value of K is 256*E/F.

Note: This register should only be changed when JESD_EN is 0.

Set this bit to 0 to request JESD204C synchronization (equivalent to the SYNC~ signal being asserted). For normal operation, leave this bit set to 1.

Note: The JSYNC_N register can always generate a synchronization request, regardless of the SYNC_SEL register. However, if the selected sync pin is stuck low, you cannot de-assert the synchronization request unless you program SYNC_SEL=2.

0 : Normal lane mapping (default). Link A uses lanes DA0 to DA3 and link B uses lanes DB0 to DB3. Other lanes are powered down.
1 : Alternate lane mapping (use upper lanes). Link A uses lanes DA4 to DA7 and link B uses lanes DB4 to DB7. Lanes DA0 to DA3 and DB0 to DB3 are powered down.

Note: This option is only supported when JMODE selects a mode that uses 8 or less lanes. The behavior is undefined for modes that do not meet this requirement.

0 : Use the SYNCSE input for SYNC~ function (default)
1 : Use the TMSTP input for SYNC~ function. TMSTP_RECV_EN must also be set.
2 : Do not use any sync input pin (use software SYNC~ through JSYNC_N)

Output sample format for JESD204C samples
0 : Offset binary
1 : Signed 2’s complement (default)

0 : 8B/10B Scrambler disabled (applies only to 8B/10B modes)
1 : 8b/10b Scrambler enabled (default)

Note 1: 64B/66B modes always use scrambling. This register does not apply to 64B/66B modes.

Note 2: This register should only be changed when JESD_EN is 0.

0 : Test mode disabled. Normal operation (default)
1 : PRBS7 test mode
2 : PRBS15 test mode
3 : PRBS23 test mode
4 : Ramp test mode
5 : Transport Layer test mode
6 : D21.5 test mode
7 : K28.5 test mode*
8 : Repeated ILA test mode*
9 : Modified RPAT test mode*
10: Serial outputs held low
11: Serial outputs held high
12: RESERVED
13: PRBS9 test mode
14: PRBS31 test mode
15: Clock test pattern (0x00FF)
16: K28.7 test mode*
17-31: RESERVED

* These test modes are only supported when JMODE is selecting a mode that uses 8b/10b encoding.
Note: This register should only be changed when JESD_EN is 0.

Specifies the DID (Device ID) value that is transmitted during the second multiframe of the JESD204B ILA. Link A will transmit DID, and link B will transmit DID+1. Bit 0 is ignored and always returns 0 (if you program an odd number, it will be decremented to an even number).

Note: This register should only be changed when JESD_EN is 0.

Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically. This only applies to modes that use 8B/10B encoding.
0 : Use K28.7 (default) (JESD204C compliant)
1 : Use K28.1 (not JESD204C compliant)
2 : Use K28.5 (not JESD204C compliant)
3 : Reserved

When using a JESD204C receiver, always use FCHAR=0.
When using a general purpose 8B/10B receiver, the K28.7 character may cause issues. When K28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers will re-align to the false comma. To avoid this, program FCHAR to 1 or 2.

Note: This register should only be changed when JESD_EN is 0.

When set, indicates that the JESD204C link is up.

Returns the state of the JESD204C SYNC~ signal.
0 : SYNC~ asserted
1 : SYNC~ de-asserted

When high, indicates that the digital block clock, frame clock, or multiframe (LMFC) clock phase was realigned by SYSREF. Writing a 1 to this bit will clear it.

When high, indicates that the multiframe (LMFC) clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit will clear it.

When high, indicates that the serializer PLL is locked.

When set, the “B” ADC channel is powered down. The digital channels that are bound to the “B” ADC channel are also powered down (see DIG_BIND).

Important notes:
1. You must set JESD_EN=0 before changing PD_CH.
2. To power down both ADC channels, use the MODE register.
3. If both channels are powered down, then the entire JESD204C subsystem is powered down, including serializer PLL and LMFC.
4. If the selected JESD204C mode transmits A and B data on link A, and the B digital channel is disabled, link A remains operational, but the B-channel samples are undefined. For proper operation in foreground calibration mode, ADC_OFF in the CAL_CFG register should be programmed to 0x1.

When set, the “A” ADC channel is powered down. The digital channels that are bound to the “A” ADC channel are also powered down (see DIG_BIND).

Important notes:
1. You must set JESD_EN=0 before changing PD_CH.
2. To power down both ADC channels, use the MODE register.
3. If both channels are powered down, then the entire JESD204C subsystem is powered down, including serializer PLL and LMFC.
4. If the selected JESD204C mode transmits A and B data on link A, and the B digital channel is disabled, link A remains operational, but the B-channel samples are undefined. For proper operation in foreground calibration mode, ADC_OFF in the CAL_CFG register should be programmed to 0x1.

Program these register bits to enable extra lanes (even if the selected JMODE does not require the lanes to be enabled). EXTRA_LANE_A(n) enables An (n=1 to 7). This register enables the link layer clocks for the affected lanes. To also enable the extra serializes set EXTRA_SER_A=1.

0 : Only the link layer clocks for extra lanes are enabled.
1 : Serializers for extra lanes are enabled (as well as link layer clocks). Use this mode to transmit data from the extra lanes.

Important Notes:
1. This register should only be changed when JESD_EN is 0.
2. The bit-rate and mode of the extra lanes are set by JMODE and JTEST (see exception below).
3. If a lane is enabled by this register (and was not enabled by JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp (same as JTEST=4).
4. This register does not override the PD_CH register, so make sure the link is enabled to use this feature.
5. To enable serializer 'n', the lower number lanes 0 to n-1 must also be enabled, otherwise serializer 'n' will not receive a clock.

Program these register bits to enable extra lanes (even if the selected JMODE does not require the lanes to be enabled). EXTRA_LANE_B(n) enables Bn (n=1 to 7). This register enables the link layer clocks for the affected lanes. To also enable the extra serializes set EXTRA_SER_B=1.

0 : Only the link layer clocks for extra lanes are enabled.
1 : Serializers for extra lanes are enabled (as well as link layer clocks). Use this mode to transmit data from the extra lanes.

Important Notes:
1. This register should only be changed when JESD_EN is 0.
2. The bit-rate and mode of the extra lanes are set by JMODE and JTEST (see exception below).
3. If a lane is enabled by this register (and was not enabled by JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp (same as JTEST=4).
4. This register does not override the PD_CH register, so make sure that the link is enabled to use this feature.
5. To enable serializer 'n', the lower number lanes 0 to n-1 must also be enabled, otherwise serializer 'n' will not receive a clock.

Select the mode for the 64b/66b sync word (32 bits of data per multi-block). This only applies when JMODE is selecting a 64b/66b mode.

0 : Transmit CRC-12 signal (default setting)
1 : RESERVED
2 : Transmit FEC signal
3 : RESERVED

Note: This device does not support any JESD204C command features. All command fields will be set to zero (idle headers).
Note: This register should only be changed when JESD_EN is 0.

This parameter defines the absolute sample level that causes control bit 0 to be set. The detection level in dBFS (peak) is 20log10(OVR_T0/256) (Default: 0xF2 = 242-> -0.5dBFS)

This parameter defines the absolute sample level that causes control bit 1 to be set. The detection level in dBFS (peak) is 20log10(OVR_T1/256) (Default: 0xAB = 171 -> -3.5dBFS)

Enables over-range status output pins when set high. The ORA0, ORA1, ORB0 and ORB1 outputs are held low when OVR_EN is set low. This register only affects the over-range output pins (ORxx). JESD204C modes that transmit over-range bits are not affected by this register.

Program this register to adjust the pulse extension for the ORA0/1 and ORB0/1 outputs. The minimum pulse duration of the over-range outputs is 8 * 2^OVR_N DEVCLK cycles. Incrementing this field doubles the monitoring period.

0xA

Spin identification value:

0: ADC12DJ5200RF

2 : ADC12DJ4000RF

10: ADC08DJ5200RF

When set, noise on VD11 is suppressed. It is recommended to have this set, as it reduces noise coupling from the digital circuits to analog clock, at the expense of a small increase in power.

0: SYSREF Calibration Disabled. Use the TAD register to manually control the tad[16:0] output and adjust the DEVCLK delay. (default)
1: SYSREF Calibration Enabled. The DEVCLK delay is automatically calibrated. The TAD register is ignored.

A 0-to-1 transition on SRC_EN starts the SYSREF calibration sequence. Program SRC_CFG before setting SRC_EN. Make sure that ADC calibration is not currently running before setting SRC_EN.

Specifies the amount of averaging used for SYSREF Calibration. Larger values will increase calibration time and reduce the variance of the calibrated value.
0: 4 averages
1: 16 averages
2: 64 averages
3: 256 averages

Specifies the duration of each high-speed accumulation for SYSREF Calibration. If the SYSREF period exceeds the supported value, calibration will fail. Larger values will increase calibration time and support longer SYSREF periods. For a given SYSREF period, larger values will also reduce the variance of the calibrated value.
0: 4 cycles per accumulation, max SYSREF period of 128 DEVCLK cycles
1: 16 cycles per accumulation, max SYSREF period of 1664 DEVCLK cycles
2: 64 cycles per accumulation, max SYSREF period of 7808 DEVCLK cycles
3: 256 cycles per accumulation, max SYSREF period of 32384 DEVCLK cycles

Max duration of SYSREF calibration is bounded by: TSYSREFCAL (in DEVCLK cycles) = 384 * 19 * 4^(SRC_AVG + SRC_HDUR + 2)

This bit returns ‘1’ when SRC_EN=1 and SYSREF Calibration has been completed.

This field returns the value for TAD[16:0] computed by SYSREF Calibration. It is only valid if SRC_DONE=1.

SRC_TAD[16] indicates if DEVCLK has been inverted.
SRC_TAD[15:8] indicates the coarse delay adjustment.
SRC_TAD[7:0] indicates the fine delay adjustment.

Inverts the sampling clock when set.

This register controls the coarse resolution of the sampling aperture delay adjustment when SRC_EN=0. Use this register to manually control the DEVCLK aperture delay when SYSREF Calibration is disabled. If ADC calibration or JESD204B is running, it is recommended that you gradually increase or decrease this value (1 code at a time) to avoid clock glitches. Refer to Switching Characteristics for TAD_COARSE resolution.

If ADC calibration is enabled (CAL_EN=1), or the JESD204C link is enabled (JESD_EN=1), the following rules must be obeyed to avoid clock glitches and unpredictable behavior:
1. Do not change TAD_INV. You must program CAL_EN=0 and JESD_EN=0 before changing TAD_INV.
2. TAD_COARSE must be increased or decreased gradually (no more than 4 codes at a time). This rule can be obeyed manually via SPI writes, or by setting TAD_RAMP_EN.

Specifies the ramp rate for TAD_COARSE when the TAD_COARSE register is written while TAD_RAMP_EN=1.

0: TAD_COARSE ramps up or down one code per 384 sampling clock cycles.
1: TAD_COARSE ramps up or down 4 codes per 384 sampling clock cycles.

TAD ramp enable. Set this bit if you want the coarse TAD adjustment (TAD_COARSE) to ramp up or down instead of changing abruptly.
0 : After writing the TAD_COARSE register, the applied TAD_COARSE setting is updated within 1536 CLK cycles (ramp feature disabled).
1 : After writing the TAD_COARSE register, the applied TAD_COARSE setting ramps up or down gradually until it matches the TAD_COARSE register.

This bit returns a ‘1’ whenever any alarm occurs that is unmasked in the ALM_STATUS register. Use ALM_MASK to mask (disable) individual alarms. CAL_STATUS_SEL can be used to drive the ALARM bit onto the CALSTAT output pin to provide a hardware alarm interrupt signal.

FIFO overflow/underflow alarm: This bit is set whenever an active JESD204C lane FIFO experiences an underflow or overflow condition. Write a ‘1’ to clear this bit. To inspect which lane generated the alarm, read FIFO_LANE_ALM.

PLL Lock Lost Alarm: This bit is set whenever the PLL is not locked. Write a ‘1’ to clear this bit.

Link Alarm: This bit is set whenever the JESD204C link is enabled, but is not in the data encoder state (for 8B/10B modes). In 64B/66B modes, there is no data encoder state, so this alarm will be set when the link first starts up, and will also be set if any event causes a FIFO/serializer realignment. Write a ‘1’ to clear this bit.

Realigned Alarm: This bit is set whenever SYSREF causes the internal clocks (including the LMFC/LEMC) to be realigned. Write a ‘1’ to clear this bit.

Not used for ADC08DJ5200RF.

Clock Alarm: This bit can be used to detect an upset to the internal JESD204C clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match. Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register.

Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’
Note: When JESD_EN=0, all alarms (except CLK_ALM) are undefined. It is recommended that the user clears the alarms after setting JESD_EN=1.

When set, FIFO_ALM is masked and will not impact the ALARM register bit.

When set, PLL_ALM is masked and will not impact the ALARM register bit.

When set, LINK_ALM is masked and will not impact the ALARM register bit.

When set, REALIGNED_ALM is masked and will not impact the ALARM register bit.

Not used for ADC08DJ5200RF.

When set, CLK_ALM is masked and will not impact the ALARM register bit.

FIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow or underflow. Use this register to determine which lane(s) generated an alarm. Writing a ‘1’ to any bit in this register will clear the alarm (the alarm may immediately trip again if the overflow/underflow condition persists). Writing a ‘1’ to the FIFO_ALM bit in the ALM_STATUS register will clear all bits of this register.

This register (and other TADJ* registers that follow it) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes. The default values for all TADJ* registers are factory programmed values. The factory trimmed values can be read out and adjusted as required.

See TADJ_A register for description. Adjusts timing of B-ADC in dual channel mode with foreground calibration enabled.

See TADJ_A register for description. Adjusts timing of A-ADC in single channel mode with foreground calibration enabled and sampling INA±.

See TADJ_A register for description. Adjusts timing of B-ADC in single channel mode with foreground calibration enabled and sampling INA±.

See TADJ_A register for description. Adjusts timing of A-ADC in single channel mode with foreground calibration enabled and sampling INB±.

See TADJ_A register for description. Adjusts timing of B-ADC in single channel mode with foreground calibration enabled and sampling INB±.

Offset adjustment value applied to A-ADC when it samples INA± in dual channel mode and foreground calibration is enabled.

Offset adjustment value applied to A-ADC when it samples INB± in dual channel mode and foreground calibration is enabled.

Offset adjustment value applied to A-ADC when it samples INA± in single channel mode and foreground calibration is enabled.

Offset adjustment value applied to A-ADC when it samples INB± using 90° clock phase and foreground calibration is enabled.

Offset adjustment value applied to B-ADC when it samples INA± and foreground calibration is enabled. Applies to both dual channel mode and single channel mode.

Offset adjustment value applied to B-ADC when it samples INB± and foreground calibration is enabled. Applies to both dual channel mode and single channel mode.

Fine gain adjustment for ADC A bank 0.

Fine gain adjustment for ADC A bank 1.

Fine gain adjustment for ADC B bank 0.

Fine gain adjustment for ADC B bank 1.

Fine gain adjustment for ADC A bank 0.

Fine gain adjustment for ADC A bank 1.

Fine gain adjustment for ADC B bank 0.

Fine gain adjustment for ADC B bank 1.

When set, the PFIR on the B channel uses the same coefficients as the PFIR on the A channel. When PFIR_SHARE=0, the B channel filter uses its own set of coefficients (unique from channel A). See Programmable FIR Filter (PFIR) section for usage details.

When set, the PFIR filters are merged into a single logical filter. This mode processes ADC data samples as if they belong to a single sample stream. Set PFIR_MERGE=1 whenever the ADC is setup in Single Channel Mode.

Side coefficient weight for PFIR. This field determines the weight of the coefficients (except for the center coefficient). Increasing the coefficient weight increases the range of the coefficients at the expense of reduced precision. The LSB weight is 2^PFIR_SCW-16, where PFIR_SCW weight can be programmed from 0 to 6. The default is 0 which provides an LSB weight of 2^-16.

0 : PFIR block is disabled (default)
1 : RESERVED
2 : Enable PFIR block
3 : RESERVED

Note: When using the PFIR, you must also program the filter coefficients.

Note: All PFIR_* register should only be changed when JESD_EN=0.

Signed, 2’s complement coefficient for the PFIR filter. This is the first tap for the ADC A programmable FIR filter in Dual Channel Mode or the first tap for the programmable FIR filter in Single Channel Mode.

Signed, 2’s complement coefficient for the PFIR filter. This is the second tap for the ADC A programmable FIR filter in Dual Channel Mode or the second tap for the programmable FIR filter in Single Channel Mode.