SBAS997B February   2020  – October 2024 ADC09DJ1300-Q1 , ADC09QJ1300-Q1 , ADC09SJ1300-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
        4. 6.3.2.4 ADC Core
          1. 6.3.2.4.1 ADC Core Calibration
          2. 6.3.2.4.2 ADC Theory of Operation
          3. 6.3.2.4.3 Analog Reference Voltage
          4. 6.3.2.4.4 ADC Over-range Detection
          5. 6.3.2.4.5 Code Error Rate (CER)
        5. 6.3.2.5 Temperature Monitoring Diode
        6. 6.3.2.6 Timestamp
        7. 6.3.2.7 Clocking
          1. 6.3.2.7.1 Converter PLL (C-PLL) for Sampling Clock Generation
          2. 6.3.2.7.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
          3. 6.3.2.7.3 Optional CMOS Clock Outputs (ORC, ORD)
          4. 6.3.2.7.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
            1. 6.3.2.7.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
            2. 6.3.2.7.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        8. 6.3.2.8 JESD204C Interface
          1. 6.3.2.8.1  Transport Layer
          2. 6.3.2.8.2  Scrambler
          3. 6.3.2.8.3  Link Layer
          4. 6.3.2.8.4  8B/10B Link Layer
            1. 6.3.2.8.4.1 Data Encoding (8B/10B)
            2. 6.3.2.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
            3. 6.3.2.8.4.3 Code Group Synchronization (CGS)
            4. 6.3.2.8.4.4 Initial Lane Alignment Sequence (ILAS)
            5. 6.3.2.8.4.5 Frame and Multiframe Monitoring
          5. 6.3.2.8.5  64B/66B Link Layer
            1. 6.3.2.8.5.1 64B/66B Encoding
            2. 6.3.2.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. 6.3.2.8.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. 6.3.2.8.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
                2. 6.3.2.8.5.2.1.2 Forward Error Correction (FEC) Mode
            3. 6.3.2.8.5.3 Initial Lane Alignment
            4. 6.3.2.8.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
          6. 6.3.2.8.6  Physical Layer
            1. 6.3.2.8.6.1 SerDes Pre-Emphasis
          7. 6.3.2.8.7  JESD204C Enable
          8. 6.3.2.8.8  Multi-Device Synchronization and Deterministic Latency
          9. 6.3.2.8.9  Operation in Subclass 0 Systems
          10. 6.3.2.8.10 Alarm Monitoring
            1. 6.3.2.8.10.1 Clock Upset Detection
            2. 6.3.2.8.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1  Serializer Test-Mode Details
        2. 6.4.4.2  PRBS Test Modes
        3. 6.4.4.3  Clock Pattern Mode
        4. 6.4.4.4  Ramp Test Mode
        5. 6.4.4.5  Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6  D21.5 Test Mode
        7. 6.4.4.7  K28.5 Test Mode
        8. 6.4.4.8  Repeated ILA Test Mode
        9. 6.4.4.9  Modified RPAT Test Mode
        10. 6.4.4.10 Calibration Modes and Trimming
          1. 6.4.4.10.1 Foreground Calibration Mode
          2. 6.4.4.10.2 Background Calibration Mode
          3. 6.4.4.10.3 Low-Power Background Calibration (LPBG) Mode
        11. 6.4.4.11 Offset Calibration
        12. 6.4.4.12 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
    6. 6.6 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
        4. 7.2.1.4 Quad Channel Hand-Held 1.25-GSPS 625-MSPS Oscilloscope
      2. 7.2.2 Initialization Set Up
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Sequencing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 Quad Channel AAV Package, 144-Ball Flip Chip BGA (Top View)
Figure 4-2 Dual Channel AAV Package, 144-Ball Flip Chip BGA (Top View)
Figure 4-3 Single Channel AAV Package, 144-Ball Flip Chip BGA (Top View)
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
A1, A4, A5, A8, B1, B2, B3, B4, B5, B6, B7, B8, C2, C5, C6, D2, D3, E1, E2, E4, E7, F4, F7, G4, G7, H1, H2, H4, H7, J2, K2, L1, L2, L3, L4, L5, L6, L7, L8, M1, M4, M5, M8 AGND — Analog supply ground. Tie AGND, PGND, SE_GND and DGND to a common ground plane (GND) on the circuit board.
C3 BG O Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads, as specified in the table. This pin can be left disconnected if not used.
B9 CALSTAT O Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used.
A9 CALTRIG I Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not used.
G1 CLK– I Device (sampling) clock negative input or differential PLL reference clock negative input. TI strongly recommends using AC-coupling for best performance. This pin can be left disconnected if SE_CLK is used to apply the reference clock.
F1 CLK+ I Device (sampling) clock positive input or differential PLL reference clock negative input. The clock signal is strongly recommended to be AC-coupled to this input for best performance. This differential input has an internal 100Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0. This pin can be left disconnected if SE_CLK is used to apply the reference clock when the PLL is used.
C7 CLKCFG0 I CLKCFG0 and CLKCFG1 can be used enable additional clock outputs on ORC and ORD when the C-PLL is used (PLL_EN is set high). Tie this pin to ground if not used.
D7 CLKCFG1 I CLKCFG0 and CLKCFG1 can be used enable additional clock outputs on ORC and ORD when the C-PLL is used (PLL_EN is set high). Tie this pin to ground if not used.
K12 D0– O High-speed serialized data output for lane 0, negative connection. This pin can be left disconnected if not used.
J12 D0+ O High-speed serialized data output for lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100Ω differential termination at the receiver. This pin can be left disconnected if not used.
H12 D1– O High-speed serialized data output for lane 1, negative connection. This pin can be left disconnected if not used.
G12 D1+ O High-speed serialized data output for lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100Ω differential termination at the receiver. This pin can be left disconnected if not used.
F12 D2– O High-speed serialized data output for lane 2, negative connection. This pin can be left disconnected if not used.
E12 D2+ O High-speed serialized data output for lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100Ω differential termination at the receiver. This pin can be left disconnected if not used.
D12 D3– O High-speed serialized data output for lane 3, negative connection. This pin can be left disconnected if not used.
C12 D3+ O High-speed serialized data output for lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100Ω differential termination at the receiver. This pin can be left disconnected if not used.
K11 D4- O High-speed serialized data output for lane 4, negative connection. Not used for single channel devices. This pin can be left disconnected if not used.
J11 D4+ O High-speed serialized data output for lane 4, positive connection. Not used for single channel devices. This differential output must be AC-coupled and must always be terminated with a 100Ω differential termination at the receiver. This pin can be left disconnected if not used.
H11 D5- O High-speed serialized data output for lane 5, negative connection. Not used for single channel devices. This pin can be left disconnected if not used.
G11 D5+ O High-speed serialized data output for lane 5, positive connection. Not used for single channel devices. This differential output must be AC-coupled and must always be terminated with a 100Ω differential termination at the receiver. This pin can be left disconnected if not used.
F11 D6- O High-speed serialized data output for lane 6, negative connection. Not used for single channel devices. This pin can be left disconnected if not used.
E11 D6+ O High-speed serialized data output for lane 6, positive connection. Not used for single channel devices. This differential output must be AC-coupled and must always be terminated with a 100Ω differential termination at the receiver. This pin can be left disconnected if not used.
D11 D7- O High-speed serialized data output for lane 7, negative connection. Not used for single channel devices. This pin can be left disconnected if not used.
C11 D7+ O High-speed serialized data output for lane 7, positive connection. Not used for single channel devices. This differential output must be AC-coupled and must always be terminated with a 100Ω differential termination at the receiver. This pin can be left disconnected if not used.
A11, A12, B11, B12, C10, F10, G10, K10, L9, L11, L12, M11, M12 DGND — Digital supply ground. Tie AGND, PGND, SE_GND and DGND to a common ground plane (GND) on the circuit board.
A3 INA– I Channel A analog input negative connection for quad, dual and single channel devices. See INA+ for detailed description. This input is terminated to VA11 through a 50-Ω termination resistor. This pin can be left disconnected if not used.
A2 INA+ I Channel A analog input positive connection for quad, dual and single channel devices. The differential full-scale input voltage is determined by the FS_RANGE register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to VA11 through a 50Ω termination resistor. The input common-mode voltage is internally self-biased to VA11 (1.1 V nominally) and must follow the recommendations in the table. This input can be AC coupled to the source if DC signals are not required. If DC signals are required then a DC-coupled fully differential driving amplifier must be used with its output common-mode voltage set to the VA11 supply voltage. This pin can be left disconnected if not used.
A7 INB– I Channel B analog input negative connection for quad and dual channel devices. Do not connect for single channel device. See INB+ for detailed description. This input is terminated to VA11 through a 50Ω termination resistor. This pin can be left disconnected if not used.
A6 INB+ I Channel B analog input positive connection for quad and dual channel devices. Do not connect for single channel device. The differential full-scale input voltage is determined by the FS_RANGE register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to VA11 through a 50Ω termination resistor. The input common-mode voltage is internally self-biased to VA11 (1.1 V nominally) and must follow the recommendations in the table. This input can be AC coupled to the source if DC signals are not required. If DC signals are required then a DC-coupled fully differential driving amplifier must be used with its output common-mode voltage set to the VA11 supply voltage. This pin can be left disconnected if not used.
M7 INC– I Channel C analog input negative connection for quad channel device. Do not connect for single and dual channel devices. See INC+ for detailed description. This input is terminated to VA11 through a 50Ω termination resistor. This pin can be left disconnected if not used.
M6 INC+ I Channel C analog input positive connection for quad channel device. Do not connect for single and dual channel devices. The differential full-scale input voltage is determined by the FS_RANGE register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to VA11 through a 50Ω termination resistor. The input common-mode voltage is internally self-biased to VA11 (1.1V nominally) and must follow the recommendations in the table. This input can be AC coupled to the source if DC signals are not required. If DC signals are required then a DC-coupled fully differential driving amplifier must be used with its output common-mode voltage set to the VA11 supply voltage. This pin can be left disconnected if not used.
M3 IND– I Channel D analog input negative connection for quad channel device. Do not connect for single and dual channel devices. See IND+ for detailed description. This input is terminated to VA11 through a 50Ω termination resistor. This pin can be left disconnected if not used.
M2 IND+ I Channel D analog input positive connection for quad channel device. Do not connect for single and dual channel devices. The differential full-scale input voltage is determined by the FS_RANGE register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to VA11 through a 50Ω termination resistor. The input common-mode voltage is internally self-biased to VA11 (1.1V nominally) and must follow the recommendations in the table. This input can be AC coupled to the source if DC signals are not required. If DC signals are required then a DC-coupled fully differential driving amplifier must be used with its output common-mode voltage set to the VA11 supply voltage. This pin can be left disconnected if not used.
C9 ORA O Fast over-range detection status output for channel A. When the analog input for channel A exceeds the threshold programmed into OVR_T, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
D9 ORB O Fast over-range detection status output for channel B. Only used for quad and dual channel devices. Do not connect for single channel device. When the analog input for channel B exceeds the threshold programmed into OVR_T, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
E9 ORC O Fast over-range detection status output for channel C or additional clock output. The fast over-range detection function is only available for quad channel device. When the analog input for channel C exceeds the threshold programmed into OVR_T, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can alternatively be used as an additional clock output (DIVREF_C) when enabled by CLKCFG[1:0] or through the SPI register configuration and when PLL_EN is high. When CLKCFG0 and CLKCFG1 are both set low (or disabled through SPI) the ORC output is used to output the over-range signal for ADC channel C.ORC can be programmed as a copy of PLLREFO (CLKCFG[1:0] = 0x1) or as a divide-by-2 (CLKCFG[1:0] = 0x2) or divide-by-4 (CLKCFG[1:0] = 0x3) copy of PLLREFO. The clock at ORC is available at device power up if PLL_EN is set high, PD is set low and CLKCFG[1:0] are configured appropriately. This pin can be left disconnected if not used.
F9 ORD O Fast over-range detection status output for channel D or additional clock output. The fast over-range detection function is only available for quad channel device. When the analog input for channel D exceeds the threshold programmed into OVR_T, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can alternatively be used as an additional clock output (DIVREF_D) when enabled by CLKCFG[1:0] or through the SPI register configuration and when PLL_EN is high. When CLKCFG0 and CLKCFG1 are both set low (or disabled through SPI) the ORD output is used to output the over-range signal for ADC channel D.ORD can be programmed as a copy of PLLREFO when any or both of CLKCFG[1:0] are set which will be available at start up if PLL_EN is set high and PD is held low. ORD can be set as a divide-by-2 or divide-by-4 copy of PLLREFO when overridden through the SPI register. A clock out of ORD is only available if a clock is also output from ORC. If only one clock is required then use ORC. This pin can be left disconnected if not used.
M9 PD I CMOS input to power down the device for power savings or temperature diode calibration. Setting PD high disables PLLREFO and the ORC and ORD clock outputs and therefore this pin should not be used if these clocks are critical for system operation. Tie this pin to GND if not used.
J3, K5 PGND — PLL supply ground. Tie AGND, PGND, SE_GND and DGND to a common ground plane (GND) on the circuit board.
D8 PLL_EN I CMOS input to enable the internal PLL for sampling clock generation if set high or to disable and bypass the PLL if set low. Tie this pin to GND if PLL is not used.
C8 PLLREF_SE I CMOS input to select the single-ended PLL reference clock input (SE_CLK) if set high or the differential clock input (CLK±) if set low. Only CLK± can be used for the sampling clock if the PLL is disabled. Tie this pin to GND if the PLL is not used or if CLK± is used as the reference clock input.
K7 PLLREFO– O Negative LVDS PLL reference clock output. The clock is repeated from the selected PLL reference clock input (CLK± or SE_CLK). It is available at device power up to clock other devices when PLL_EN is set high and PD is held low. This pin can be left disconnected if not used.
J7 PLLREFO+ O Positive LVDS PLL reference clock output. The clock is repeated from the selected PLL reference clock input (CLK± or SE_CLK). It is available at device power up to clock other devices when PLL_EN is set high and PD is held low. This pin can be left disconnected if not used.
F8 SCLK I Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial programming data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1V to 1.9V CMOS levels.
E8 SCS I Serial interface chip select active low input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1V to 1.9V CMOS levels. This pin has a 82kΩ pull-up resistor to VD11.
G8 SDI I Serial interface data input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1V to 1.9V CMOS levels.
G9 SDO O Serial interface data output. The Using the Serial Interface section describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9V CMOS levels during serial interface read operations. This pin can be left disconnected if not used.
F2 SE_CLK I Single-ended PLL reference clock input. This input is selected when PLL_EN is held high and PLLREF_SE is held high. When PLLREF_SE is set low, CLK± is used as the differential PLL reference input. This pin should be tied to GND if not used.
G2 SE_GND — Ground reference for single-ended PLL reference clock input. Tie AGND, PGND, SE_GND and DGND to a common ground plane (GND) on the circuit board.
C4 SYNCSE I Single-ended JESD204C SYNC signal. This input is an active low input that is used to initialize the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. The 64B/66B modes do not use the SYNC signal. When toggled low in 8B/10B modes this input initiates code group synchronization (see the Code Group Synchronization (CGS) section). After code group synchronization, this input must be toggled high to start the initial lane alignment sequence (see the Initial Lane Alignment Sequence (ILAS) section). Tie this pin to ground if TMSTP± or JSYNC_N is used as the JESD204C SYNC signal or for 64B/66B encoded JESD204C modes.
K1 SYSREF– I SYSREF negative input. Leave this pin disconnected if not used and power down the SYSREF± receiver using SYSREF_RECV_EN.
J1 SYSREF+ I The SYSREF positive input is used to achieve synchronization and deterministic latency across the JESD204C interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination changes to 50Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode voltage range provided in the table. Leave this pin disconnected if not used and power down the SYSREF± receiver using SYSREF_RECV_EN.
K4 TDIODE– I Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.
K3 TDIODE+ I Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used.
D1 TMSTP– I Timestamp input negative connection. This pin can be left disconnected and the TMSTP receiver powered down (TMSTP_RECV_EN = 0) if timestamp is not required.
C1 TMSTP+ I Timestamp input positive connection. This input is a timestamp input, used to mark a specific sample, when TIME_STAMP_EN is set to 1. For additional usage information, see the Timestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0. The termination changes to 50Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for both AC- and DC-coupled configurations. The common-mode voltage must be within the range provided in the table when both AC and DC coupled. Can also be used as a differential SYNC input for the JESD204C interface with 8b/10b encoding. This pin can be left disconnected and the TMSTP receiver powered down (TMSTP_RECV_EN = 0) if timestamp is not required.
K9 TRIGOUT– O Negative LVDS output for trigger repeated from TMSTP± or clock output generated from the SerDes PLL. This output can be enabled by setting TRIGOUT_EN to 1 and configured by TRIGOUT_MODE. Setting the PD pin high disables this output. This pin can be left disconnected if not used.
J9 TRIGOUT+ O Positive LVDS output for trigger repeated from TMSTP± or clock output generated from the SerDes PLL. This output can be enabled by setting TRIGOUT_EN to 1 and configured by TRIGOUT_MODE. Setting the PD pin high disables this output. This pin can be left disconnected if not used.
D6, E3, E5, F3, F5, G3, G5, H3, H5, J6 VA11 — 1.1V analog supply
D4, D5, E6, F6, G6, H6 VA19 — 1.9V analog supply
A10, B10, D10, E10, H8, H9, H10, J10, L10, M10 VD11 — 1.1V digital supply
J4, J5 VPLL19 — 1.9V supply for internal PLL and VCO
K6 VREFO — 1.9V supply for PLLREFO± output driver and PLL charge pump
J8, K8 VTRIG — 1.1V to 1.9V supply for TRIGOUT± output driver