SBASA53A July 2021 – October 2024 ADC09DJ800-Q1 , ADC09QJ800-Q1 , ADC09SJ800-Q1
PRODUCTION DATA
The sync header stream can be used to identify bit errors on the link or to correct bit errors. Two modes of operation are available in ADC09xJ800-Q1. Cyclic redundancy checking (CRC) can be used to identify bit errors. ADC09xJ800-Q1 only supports 12-bit CRC (CRC-12) and does not support the optional 3-bit CRC-3 described by JESD204C. Alternatively, forward error correction (FEC) can be used to identify bit errors and then correct bit errors. For information on CRC-12, see Cyclic Redundancy Check (CRC Mode). For information on FEC, see Forward Error Correction (FEC) Mode.