SNAS825A December   2021  – April 2022 ADC128S102-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ADC128S102-SEP Transfer Function
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Digital Inputs and Outputs
      4. 7.3.4 Radiation Environments
        1. 7.3.4.1 Total Ionizing Dose
        2. 7.3.4.2 Single Event Latch-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 ADC128S102-SEP Operation
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequence
    2. 9.2 Power Management
    3. 9.3 Power-Supply Noise Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 ADC128S102-SEP Operation

Simplified schematics of the ADC128S102-SEP in both track and hold operation are provided in Figure 7-3 and Figure 7-4, respectively. In Figure 7-3, the ADC128S102-SEP is in track mode: switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC128S102-SEP is in this state for the first three SCLK cycles after CS is brought low.

GUID-14F4D700-0B84-4221-875E-ABB75F794042-low.gif Figure 7-3 ADC128S102-SEP in Track Mode

Figure 7-4 shows the ADC128S102-SEP in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC128S102-SEP is in this state for the last 13 SCLK cycles after CS is brought low.

GUID-0271A3DC-6E13-443A-BC08-E5E9FA275011-low.gifFigure 7-4 ADC128S102-SEP in Hold Mode