An operational timing diagram and a serial interface timing diagram for the ADC128S102-SEP are illustrated in the Section 6.8 section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the control register are placed on DIN, the serial data input pin. New data are written to DIN with each conversion.

A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC DOUT pin is in a high-impedance state when CS is high and is active when CS is low. CS is asynchronous and therefore functions as an output enable. Similarly, SCLK is internally gated off when CS is brought high.

During the first three SCLK cycles, the ADC is in track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data are clocked out. SCLK falling edges 1 through 4 clock out leading zeros and falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than one conversion in a frame (continuous conversion mode), the ADC re-enters track mode on the SCLK falling edge after the N × 16th SCLK rising edge and re-enters the hold/convert mode on the N × 16 + 4th SCLK falling edge. N is an integer value.

The ADC128S102-SEP enters track mode under three different conditions. In Figure 6-1, CS goes low with SCLK high and the ADC enters track mode on the first SCLK falling edge. In the second condition, CS goes low with SCLK low. Under this condition, the ADC automatically enters track mode and the CS falling edge is taken as the first SCLK falling edge. In the third condition, CS and SCLK go low simultaneously and the ADC enters track mode. Although there is no timing restriction with respect to the falling edges of CS and SCLK, see Figure 6-3 for setup and hold time requirements for the CS falling edge with respect to the SCLK rising edge.

During each conversion, data are clocked into a control register through the DIN pin on the first eight SCLK rising edges after the fall of CS. As given in Table 7-1, Table 7-2, and Table 7-3, the control register is loaded with data indicating the input channel to be converted on the subsequent conversion.

Although the ADC128S102-SEP can acquire the input signal to full resolution in the first conversion immediately following power up, the first conversion result after power up is that of a randomly selected channel. Therefore, incorporate a dummy conversion to set the required channel to be used on the subsequent conversion.