SNAS825A December   2021  – April 2022 ADC128S102-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ADC128S102-SEP Transfer Function
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Digital Inputs and Outputs
      4. 7.3.4 Radiation Environments
        1. 7.3.4.1 Total Ionizing Dose
        2. 7.3.4.2 Single Event Latch-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 ADC128S102-SEP Operation
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequence
    2. 9.2 Power Management
    3. 9.3 Power-Supply Noise Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2 Power Management

The ADC128S102-SEP is fully powered up when CS is low and is fully powered down when CS is high, with one exception. If operating in continuous conversion mode, the ADC128S102-SEP automatically enters power-down mode between the 16th SCLK falling edge of a conversion and the 1st SCLK falling edge of the subsequent conversion (see Figure 6-1).

In continuous conversion mode, the ADC128S102-SEP can perform multiple conversions back to back. Each conversion requires 16 SCLK cycles and the ADC128S102-SEP performs conversions continuously as long as CS is held low. Continuous mode offers maximum throughput.

In burst mode, throughput can be traded off for power consumption by performing fewer conversions per unit time. In other words, more time is spent in power-down mode and less time is spent in normal mode. By using this technique, very low sample rates can be achieved while still using an SCLK frequency within the electrical specifications. To calculate the power consumption (PC), simply multiply the fraction of time spent in normal mode (tN) by the normal mode power consumption (PN), as shown in Equation 1, and add the fraction of time spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS).

Equation 1. GUID-4BC74D96-939B-4BDB-B51D-02A53A900291-low.gif