The signal range requirement forces the design to use a 5-V analog supply at V_A, the analog supply. This requirement stems from the fact that V_A is also a reference potential for the ADC. If the requirement of interfacing to the MCU changes to 3.3 V, the V_D supply voltage must also change to 3.3 V. The maximum sampling rate of the ADC128S102-SEP when all channels (eight) are enabled is f_S = f_SCLK / (16 × 8).

Faster sampling rates can be achieved when fewer channels are sampled. A single channel can be sampled at the maximum rate of f_S (single) = f_SCLK / 16.

The V_A and V_D pins are separated by a 51-Ω resistor to minimize digital noise from corrupting the analog reference input. If additional filtering is required, the resistor can be replaced by a ferrite bead, thus achieving a second-order filter response. Further noise consideration can be provided to the SPI interface, especially when the controller MCU is capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal path can help reduce ground bounce, and thus improve overall noise performance of the system. Care must be taken when the signal source is capable of producing voltages beyond V_A. In such instances, the internal ESD diodes can start conducting. The ESD diodes are not intended as input signal clamps. To provide the desired clamping action, use Schottky diodes.