SNAS825A December   2021  – April 2022 ADC128S102-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ADC128S102-SEP Transfer Function
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Digital Inputs and Outputs
      4. 7.3.4 Radiation Environments
        1. 7.3.4.1 Total Ionizing Dose
        2. 7.3.4.2 Single Event Latch-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 ADC128S102-SEP Operation
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequence
    2. 9.2 Power Management
    3. 9.3 Power-Supply Noise Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50 pF (unless otherwise noted); minimum and maximum values at TA = –55°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
IDCL Input leakage current –1 1 µA
CIN Input capacitance(1) Track mode 33 pF
Hold mode 3
DC PERFORMANCE
Resolution No missing codes 12 Bits
DNL Differential nonlinearity VA = VD = 3 V 0.5 1.8 LSB
–0.99 –0.3
VA = VD = 5 V 0.9 1.7
–0.99 –0.5
INL Integral nonlinearity VA = VD = 3 V –1.6 ±0.6 1.6 LSB
VA = VD = 5 V –1.5 ±0.9 1.5
VOFF Input offset error VA = VD = 3 V –2.3 0.8 2.3 LSB
VA = VD = 5 V –2.3 1.1 2.3
OEM Offset error match VA = VD = 3 V –1.5 ±0.1 1.5 LSB
VA = VD = 5 V –1.5 ±0.3 1.5
FSE Full-scale error VA = VD = 3 V –2.1 0.8 2.1 LSB
VA = VD = 5 V –2.1 0.3 2.1
FSEM Full-scale error match VA = VD = 3 V –1.6 ±0.1 1.6 LSB
VA = VD = 5 V –1.6 ±0.3 1.6
AC PERFORMANCE
FPBW Full-power bandwidth VA = VD = 3 V 6.8 MHz
VA = VD = 5 V 10
SINAD Signal-to-noise + distortion ratio VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS		 68 72 dB
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS		 68 72
SNR Signal-to-noise ratio VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS		 68.5 72 dB
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS		 68 72
THD Total harmonic distortion VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS		 –86 –72 dB
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS		 –87 –72
SFDR Spurious-free dynamic range VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS		 75 91 dB
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS		 75 90
ENOB Effective number of bits VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS		 11.1 11.6 Bits
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS		 11 11.6
ISO Channel-to-channel isolation VA = VD = 3 V,
fIN = 20 kHz, –0.02 dBFS		 84 dB
VA = VD = 5 V,
fIN = 20 kHz, –0.02 dBFS		 85
IMD Intermodulation distortion,
second order terms		 VA = VD = 3 V,
fIN = 19.5 kHz, –0.02 dBFS		 –93 –77 dB
VA = VD = 5 V,
fIN = 19.5 kHz, –0.02 dBFS		 –93 –77
Intermodulation distortion,
third order terms		 VA = VD = 3 V,
fIN = 19.5 kHz, –0.02 dBFS		 –91 –70
VA = VD = 5 V,
fIN = 19.5 kHz, –0.02 dBFS		 –91 –70
DIGITAL INPUTS
VIH Input high logic level VA = VD = 2.7 V to 3.6 V 2.1 V
VA = VD = 4.75 V to 5.25 V 2.4
VIL Input low logic level VA = VD = 2.7 V to 5.25 V 0.8 V
Input current VIN = 0 V or VD ±0.01 ±2 µA
Digital input capacitance(1) 3.5 pF
DIGITAL OUTPUTS
Output format Straight binary
VOH Output high logic level ISOURCE = 200 µA,
VA = VD = 2.7 V to 5.25 V		 VD - 0.5 V
VOL Output low logic level ISOURCE = 200 µA to 1 mA,
VA = VD = 2.7 V to 5.25 V		 0.4 V
Hiigh-impedance output leakage current VA = VD = 2.7 V to 5.25 V ±0.01 ±1 µA
Hiigh-impedance output capacitance(1) 3.5 pF
POWER SUPPLY
IA + ID Total supply current,
normal mode (CS low)		 VA = VD = 2.7 V to 3.6 V
fSAMPLE = 1 MSPS, fIN = 40 kHz		 0.9 1.5 mA
VA = VD = 4.75 V to 5.25 V
fSAMPLE = 1 MSPS, fIN = 40 kHz		 2.2 3.2
Total supply current,
shutdown mode (CS high)		 VA = VD = 2.7 V to 3.6 V
fSAMPLE = 0 kSPS		 5.5 50 µA
VA = VD = 4.75 V to 5.25 V
fSAMPLE = 0 kSPS		 6 70
PC Power consumption,
normal mode (CS low)		 VA = VD = 3 V
fSAMPLE = 1 MSPS, fIN = 40 kHz		 2.7 4.5 mW
VA = VD = 5 V
fSAMPLE = 1 MSPS, fIN = 40 kHz		 11 15.5
Power consumption,
shutdown mode (CS high)		 VA = VD = 3 V
fSAMPLE = 0 kSPS		 16.5 150 µW
VA = VD = 5 V
fSAMPLE = 0 kSPS		 30 350
(1) This parameter is specified by design and/or characterization and is not tested in production.