SNAS411P August   2008  – April 2017 ADC128S102QML-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: ADC128S102QML-SP Converter
    6. 6.6 Electrical Characteristics: Radiation
    7. 6.7 Electrical Characteristics: Burn in Delta Parameters - TA at 25°C
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ADC128S102 Transfer Function
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Digital Inputs and Outputs
      4. 7.3.4 Radiation Environments
        1. 7.3.4.1 Total Ionizing Dose
        2. 7.3.4.2 Single Event Latch-Up and Functional Interrupt
        3. 7.3.4.3 Single Event Upset
    4. 7.4 Device Functional Modes
      1. 7.4.1 ADC128S102 Operation
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequence
    2. 9.2 Power Management
    3. 9.3 Power Supply Noise Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Specification Definitions
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NAC|16
  • Y|0
  • NAD|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
VA Analog supply voltage –0.3 6.5 V
VD Digital supply voltage(4) –0.3 VA + 0.3 V
Voltage on any pin to GND –0.3 VA + 0.3 V
Input current at any pin (2) ±10 mA
Power dissipation TA = 25°C See (3)
Package input current(2) ±20 mA mA
Soldering temperature, 10 seconds 260 °C
Junction temperature 175 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When the input voltage at any pin exceeds the power supplies (that is, VIN less than AGND or VIN greater than VA or VD), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
(3) The absolute maximum junction temperature (TJmax) for this device is 175°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/RθJA. The values for maximum power dissipation listed above will be reached only when the ADC128S102QML-SP is operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
(4) The maximum voltage is not to exceed 6.5 V

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±8000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.

6.3 Recommended Operating Conditions

See (1)(2)
MIN MAX UNIT
Operating temperature –55 125 °C
VA supply voltage 2.7 5.25 V
VD supply voltage 2.7 VA V
Digital input voltage 0 VA V
Analog input voltage 0 VA V
Clock frequency 0.8 16 MHz
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is functional, but do not verify specific performance limits. For specifications and test conditions, see the Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

6.4 Thermal Information

THERMAL METRIC(1) ACD128S102QML-SP UNIT
NAC (CFP)
16 PINS
RθJA Junction-to-ambient thermal resistance 127 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 11.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: ADC128S102QML-SP Converter

The following specifications apply for AGND = DGND = 0V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, CL = 50pF, unless otherwise noted.
PARAMETER TEST CONDITIONS SUBGROUP MIN TYP(1) MAX UNIT
STATIC CONVERTER CHARACTERISTICS
Resolution with no missing codes 12 Bits
INL Integral non-linearity (end point method) VA = VD = 3 V [1, 2, 3] –1 ±0.6 1.1 LSB
VA = VD = 5 V [1, 2, 3] –1.25 ±0.9 1.4 LSB
DNL Differential non-linearity VA = VD = 3 V [1, 2, 3] 0.5 0.9 LSB
[1, 2, 3] –0.7 –0.3 LSB
VA = VD = 5 V [1, 2, 3] 0.9 1.5 LSB
[1, 2, 3] –0.9 −0.5 LSB
VOFF Offset error VA = VD = 3 V [1, 2, 3] –2.3 0.8 2.3 LSB
VA = VD = 5 V [1, 2, 3] –2.3 1.1 2.3 LSB
OEM Offset error match VA = VD = 3 V [1, 2, 3] –1.5 ±0.1 1.5 LSB
VA = VD = 5 V [1, 2, 3] –1.5 ±0.3 1.5 LSB
FSE Full scale error VA = VD = 3 V [1, 2, 3] –2 0.8 2 LSB
VA = VD = 5 V [1, 2, 3] –2 0.3 2 LSB
FSEM Full scale error match VA = VD = 3 V [1, 2, 3] –1.5 ±0.1 1.5 LSB
VA = VD = 5 V [1, 2, 3] –1.5 ±0.3 1.5 LSB
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full power bandwidth (–3 dB) VA = VD = 3 V 6.8 MHz
VA = VD = 5 V 10 MHz
SINAD Signal-to-noise plus distortion ratio VA = VD = 3 V,
fIN = 40.2 kHz, −0.02 dBFS		 [4, 5, 6] 68 72 dB
VA = VD = 5 V,
fIN = 40.2 kHz, −0.02 dBFS		 [4, 5, 6] 68 72 dB
SNR Signal-to-noise ratio VA = VD = 3 V,
fIN = 40.2 kHz, −0.02 dBFS		 [4, 5, 6] 69 72 dB
VA = VD = 5 V,
fIN = 40.2 kHz, −0.02 dBFS		 [4, 5, 6] 68.5 72 dB
THD Total harmonic distortion VA = VD = 3 V,
fIN = 40.2 kHz, −0.02 dBFS		 [4, 5, 6] –86 –74 dB
VA = VD = 5 V,
fIN = 40.2 kHz, −0.02 dBFS		 [4, 5, 6] –87 –74 dB
SFDR Spurious-free dynamic range VA = VD = 3 V,
fIN = 40.2 kHz, −0.02 dBFS		 [4, 5, 6] 75 91 dB
VA = VD = 5 V,
fIN = 40.2 kHz, −0.02 dBFS		 [4, 5, 6] 75 90 dB
ENOB Effective number of bits VA = VD = 3 V,
fIN = 40.2 kHz		 [4, 5, 6] 11.1 11.6 Bits
VA = VD = 5 V,
fIN = 40.2 kHz, −0.02 dBFS		 [4, 5, 6] 11.1 11.6 Bits
ISO Channel-to-channel isolation VA = VD = 3 V,
fIN = 20 kHz		 84 dB
VA = VD = 5 V,
fIN = 20 kHz, −0.02 dBFS		 85 dB
IMD Intermodulation distortion, second order terms VA = VD = 3 V,
fa = 19.5 kHz, fb = 20.5 kHz		 [4, 5, 6] –93 –78 dB
VA = VD = 5 V,
fa = 19.5 kHz, fb = 20.5 kHz		 [4, 5, 6] –93 –78 dB
Intermodulation distortion, third order terms VA = VD = 3 V,
fa = 19.5 kHz, fb = 20.5 kHz		 [4, 5, 6] –91 –70 dB
VA = VD = 5 V,
fa = 19.5 kHz, fb = 20.5 kHz		 [4, 5, 6] –91 –70 dB
ANALOG INPUT CHARACTERISTICS
VIN Input range 0 to VA V
IDCL DC leakage current [1, 2, 3] ±0.01 ±1 µA
CINA Input capacitance Track mode, see (2) 38 pF
Hold mode, see (2) 4.5 pF
DIGITAL INPUT CHARACTERISTICS
VIH Input high voltage VA = VD = 2.7 V to 3.6 V [1, 2, 3] 2.1 V
VA = VD = 4.75 V to 5.25 V [1, 2, 3] 2.4 V
VIL Input low voltage VA = VD = 2.7 V to 5.25 V [1, 2, 3] 0.8 V
IIN Input current VIN = 0 V or VD [1, 2, 3] ±1 ±1 µA
CIND Digital input capacitance See (2) 3.5 pF
DIGITAL OUTPUT CHARACTERISTICS
VOH Output high voltage ISOURCE = 200 µA,
VA = VD = 2.7 V to 5.25 V		 [1, 2, 3] VD –0.5 V
VOL Output low voltage ISINK = 200 µA to 1 mA,
VA = VD = 2.7 V to 5.25 V		 [1, 2, 3] 0.4 V
IOZH, IOZL Hi-impedance output leakage current VA = VD = 2.7 V to 5.25 V [1, 2, 3] ±0.01 ±1 µA
COUT Hi-impedance output capacitance See (2) 3.5 pF
Output coding Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)
VA, VD Analog and digital supply voltages VA ≥ VD [1, 2, 3] 2.7 V
[1, 2, 3] 5.25 V
IA + ID Total supply current,
normal mode ( CS low)		 VA = VD = 2.7 V to 3.6 V,
fSAMPLE = 1 MSPS, fIN = 40 kHz		 [1, 2, 3] 0.9 1.5 mA
VA = VD = 4.75 V to 5.25 V,
fSAMPLE = 1 MSPS, fIN = 40 kHz		 [1, 2, 3] 2.2 3.1 mA
Total supply current,
shutdown mode (CS high)		 VA = VD = 2.7 V to 3.6 V,
fSCLK = 0 kSPS		 [1, 2, 3] 0.11 1 μA
VA = VD = 4.75 V to 5.25 V,
fSCLK = 0 kSPS		 [1, 2, 3] 0.12 1.4 μA
PC Power consumption,
normal mode ( CS low)		 VA = VD = 3 V
fSAMPLE = 1 MSPS, fIN = 40 kHz		 [1, 2, 3] 2.7 4.5 mW
VA = VD = 5 V
fSAMPLE = 1 MSPS, fIN = 40 kHz		 [1, 2, 3] 11.0 15.5 mW
Power consumption,
shutdown mode (CS high)		 VA = VD = 3 V
fSCLK = 0 kSPS		 [1, 2, 3] 0.33 3 µW
VA = VD = 5 V
fSCLK = 0 kSPS		 [1, 2, 3] 0.6 7 µW
AC ELECTRICAL CHARACTERISTICS
fSCLKMIN Minimum clock frequency VA = VD = 2.7 V to 5.25 V [9, 10, 11] 0.8 MHz
fSCLK Maximum clock frequency VA = VD = 2.7 V to 5.25 V [9, 10, 11] 16 MHz
fS Sample rate continuous mode VA = VD = 2.7 V to 5.25 V [9, 10, 11] 50 kSPS
[9, 10, 11] 1 MSPS
tCONVERT Conversion (hold) time VA = VD = 2.7 V to 5.25 V [9, 10, 11] 13 SCLK cycles
DC SCLK duty cycle VA = VD = 2.7 V to 5.25 V MIN 40%
MAX 60%
tACQ Acquisition (track) time VA = VD = 2.7 V to 5.25 V [9, 10, 11] 3 SCLK cycles
Throughput time Acquisition time + conversion time
VA = VD = 2.7 V to 5.25 V		 [9, 10, 11] 16 SCLK cycles
tAD Aperture delay VA = VD = 2.7 V to 5.25 V 4 ns
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms.
(2) This parameter is specified by design and/or characterization and is not tested in production.

6.6 Electrical Characteristics: Radiation

The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50 pF.(1)
PARAMETER TEST CONDITIONS SUBGROUP MIN TYP MAX UNIT
IA + ID Total supply current shutdown mode (CS high) VA = VD = 2.7 V to 3.6 V,
fSCLK = 0 kSPS		 [1] 30 µA
VA = VD = 4.75 V to 5.25 V,
fSCLK = 0 kSPS		 [1] 100 µA
IOZH, IOZL Hi-impedance output leakage current VA = VD = 2.7 V to 5.25 V [1] ±10 µA
(1) Pre and post irradiation limits are identical to those listed in the DC Parameters and AC and Timing Characteristics, except as listed in Electrical Characteristics: Radiation. When performing post irradiation electrical measurements for any RHA level, TA = 25°C.

6.7 Electrical Characteristics: Burn in Delta Parameters - TA at 25°C

The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50 pF.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INL Integral non-linearity VA = VD = 3 V –0.5 0.106 0.5 LSB
VA = VD = 5 V –0.35 0.016 0.35 LSB
IMD Intermodulation distortion, second order terms VA = VD = 3 V –14 1.35 14 dB
VA = VD = 5 V –17 1.67 17 dB
IMD Intermodulation distortion, third order terms VA = VD = 3 V –10 0.47 10 dB
VA = VD = 5 V –10 0.9 10 dB
(1) This is worse case drift, Deltas are performed at room temperature post operational life. All other parameters, no deltas are required.

6.8 Timing Requirements

The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50 pF.
SUBGROUP MIN NOM(1) MAX UNIT
tCSH CS hold time after SCLK rising edge See (2) [9, 10, 11] 10 0 ns
tCSS CS setup time prior to SCLK rising edge See (2) [9, 10, 11] 10 4.5 ns
tEN CS falling edge to DOUT enabled [9, 10, 11] 5 30 ns
tDACC DOUT access time after SCLK falling edge [9, 10, 11] 17 27 ns
tDHLD DOUT hold time after SCLK falling edge [9, 10, 11] 7 ns
tDS DIN setup time prior to SCLK rising edge [9, 10, 11] 10 ns
tDH DIN hold time after SCLK rising edge [9, 10, 11] 10 ns
tCH SCLK high time 0.4 × tSCLK ns
tCL SCLK low time 0.4 × tSCLK ns
tDIS CS rising edge to DOUT high-impedance DOUT falling [9, 10, 11] 2.4 20 ns
DOUT rising [9, 10, 11] 0.9 20 ns
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms.
(2) Clock may be in any state (high or low) when CS goes high. Setup and hold time restrictions apply only to CS going low.

Table 1. Quality Conformance Inspection(1)

SUBGROUP DESCRIPTION TEMP (°C)
1 Static tests at 25
2 Static tests at 125
3 Static tests at –55
4 Dynamic tests at 25
5 Dynamic tests at 125
6 Dynamic tests at –55
7 Functional tests at 25
8A Functional tests at 125
8B Functional tests at –55
9 Switching tests at 25
10 Switching tests at 125
11 Switching tests at –55
12 Setting time at 25
13 Setting time at 125
14 Setting time at –55
(1) MIL-STD-883, Method 5005 - Group A
ADC128S102QML-SP 30018151.gif Figure 1. ADC128S102 Operational Timing Diagram
ADC128S102QML-SP 30018106.gif Figure 2. ADC128S102 Serial Timing Diagram
ADC128S102QML-SP 30018150.gif Figure 3. SCLK and CS Timing Parameters

6.9 Typical Characteristics

TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.
ADC128S102QML-SP 30018140.png Figure 4. DNL
ADC128S102QML-SP 30018142.png Figure 6. INL
ADC128S102QML-SP 30018121.png Figure 8. DNL vs Supply
ADC128S102QML-SP 30018122.png Figure 10. SNR vs Supply
ADC128S102QML-SP 30018133.png Figure 12. ENOB vs Supply
ADC128S102QML-SP 30018158.png Figure 14. INL vs SCLK Duty Cycle
ADC128S102QML-SP 30018164.png Figure 16. THD vs SCLK Duty Cycle
ADC128S102QML-SP 30018156.png Figure 18. DNL vs SCLK
ADC128S102QML-SP 30018130.png Figure 20. DNL vs SCLK
ADC128S102QML-SP 30018162.png Figure 22. SNR vs SCLK
ADC128S102QML-SP 30018165.png Figure 24. THD vs SCLK
ADC128S102QML-SP 30018153.png Figure 26. ENOB vs SCLK
ADC128S102QML-SP 30018154.png Figure 28. ENOB vs Temperature
ADC128S102QML-SP 30018160.png Figure 30. INL vs Temperature
ADC128S102QML-SP 30018166.png Figure 32. THD vs Temperature
ADC128S102QML-SP 30018141.png Figure 5. DNL
ADC128S102QML-SP 30018143.png Figure 7. INL
ADC128S102QML-SP 30018120.png Figure 9. INL vs Supply
ADC128S102QML-SP 30018132.png Figure 11. THD vs Supply
ADC128S102QML-SP 30018155.png Figure 13. DNL vs SCLK Duty Cycle
ADC128S102QML-SP 30018161.png Figure 15. SNR vs SCLK Duty Cycle
ADC128S102QML-SP 30018152.png Figure 17. ENOB vs SCLK Duty Cycle
ADC128S102QML-SP 30018159.png Figure 19. INL vs SCLK
ADC128S102QML-SP 30018131.png Figure 21. INL vs SCLK
ADC128S102QML-SP 30018123.png Figure 23. SNR vs SCLK
ADC128S102QML-SP 30018124.png Figure 25. THD vs SCLK
ADC128S102QML-SP 30018145.png Figure 27. ENOB vs SCLK
ADC128S102QML-SP 30018157.png Figure 29. DNL vs Temperature
ADC128S102QML-SP 30018163.png Figure 31. SNR vs Temperature
ADC128S102QML-SP 30018144.png Figure 33. Power Consumption vs SCLK