SNAS518J July   2011  – July 2015 ADC12D1800RF

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1 Pin Diagram
      1. 3.1.1 Pin Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 4.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 4.7  Converter Electrical Characteristics: Analog Input / Output and Reference Characteristics
    8. 4.8  Converter Electrical Characteristics: I-Channel to Q-Channel Characteristics
    9. 4.9  Converter Electrical Characteristics: Sampling Clock Characteristics
    10. 4.10 Converter Electrical Characteristics: AutoSync Feature Characteristics
    11. 4.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 4.12 Converter Electrical Characteristics: Power Supply Characteristics
    13. 4.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 4.14 Converter Electrical Characteristics: Serial Port Interface
    15. 4.15 Converter Electrical Characteristics Calibration
    16. 4.16 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
      1. 5.1.1 RF Performance
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Input Control and Adjust
        1. 5.3.1.1 AC/DC-coupled Mode
        2. 5.3.1.2 Input Full-Scale Range Adjust
        3. 5.3.1.3 Input Offset Adjust
        4. 5.3.1.4 DES Timing Adjust
        5. 5.3.1.5 Sampling Clock Phase (Aperture) Delay Adjust
      2. 5.3.2 Output Control and Adjust
        1. 5.3.2.1 SDR / DDR Clock
        2. 5.3.2.2 LVDS Output Differential Voltage
        3. 5.3.2.3 LVDS Output Common-Mode Voltage
        4. 5.3.2.4 Output Formatting
        5. 5.3.2.5 Test Pattern Mode
        6. 5.3.2.6 Time Stamp
      3. 5.3.3 Calibration Feature
        1. 5.3.3.1 Calibration Control Pins and Bits
        2. 5.3.3.2 How to Execute a Calibration
        3. 5.3.3.3 Power-on Calibration
        4. 5.3.3.4 On-command Calibration
        5. 5.3.3.5 Calibration Adjust
        6. 5.3.3.6 Read / Write Calibration Settings
        7. 5.3.3.7 Calibration and Power-Down
        8. 5.3.3.8 Calibration and the Digital Outputs
      4. 5.3.4 Power Down
    4. 5.4 Device Functional Modes
      1. 5.4.1 DES/Non-DES Mode
      2. 5.4.2 Demux/Non-Demux Mode
    5. 5.5 Programming
      1. 5.5.1 Control Modes
        1. 5.5.1.1 Non-Extended Control Mode
          1. 5.5.1.1.1  Dual Edge Sampling Pin (DES)
          2. 5.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 5.5.1.1.3  Dual Data Rate Phase Pin (DDRPh)
          4. 5.5.1.1.4  Calibration Pin (CAL)
          5. 5.5.1.1.5  Calibration Delay Pin (CalDly)
          6. 5.5.1.1.6  Power Down I-channel Pin (PDI)
          7. 5.5.1.1.7  Power Down Q-channel Pin (PDQ)
          8. 5.5.1.1.8  Test Pattern Mode Pin (TPM)
          9. 5.5.1.1.9  Full-Scale Input Range Pin (FSR)
          10. 5.5.1.1.10 AC / DC-Coupled Mode Pin (VCMO)
          11. 5.5.1.1.11 LVDS Output Common-mode Pin (VBG)
        2. 5.5.1.2 Extended Control Mode
          1. 5.5.1.2.1 The Serial Interface
    6. 5.6 Register Maps
      1. 5.6.1 Register Definitions
  6. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Analog Inputs
        1. 6.1.1.1 Acquiring the Input
        2. 6.1.1.2 Driving the ADC in DES Mode
        3. 6.1.1.3 FSR and the Reference Voltage
        4. 6.1.1.4 Out-of-Range Indication
        5. 6.1.1.5 Maximum Input Range
        6. 6.1.1.6 AC-Coupled Input Signals
        7. 6.1.1.7 DC-Coupled Input Signals
        8. 6.1.1.8 Single-Ended Input Signals
      2. 6.1.2 Clock Inputs
        1. 6.1.2.1 CLK Coupling
        2. 6.1.2.2 CLK Frequency
        3. 6.1.2.3 CLK Level
        4. 6.1.2.4 CLK Duty Cycle
        5. 6.1.2.5 CLK Jitter
        6. 6.1.2.6 CLK Layout
      3. 6.1.3 LVDS Outputs
        1. 6.1.3.1 Common-mode and Differential Voltage
        2. 6.1.3.2 Output Data Rate
        3. 6.1.3.3 Terminating Unused LVDS Output Pins
      4. 6.1.4 Synchronizing Multiple ADC12D1800RFS in a System
        1. 6.1.4.1 AutoSync Feature
        2. 6.1.4.2 DCLK Reset Feature
      5. 6.1.5 Recommended System Chips
        1. 6.1.5.1 Temperature Sensor
        2. 6.1.5.2 Clocking Device
        3. 6.1.5.3 Amplifiers for Analog Input
        4. 6.1.5.4 Balun Recommendations for Analog Input
    2. 6.2 Typical Application
      1. 6.2.1 RF Sampling Receiver
      2. 6.2.2 Design Requirements
      3. 6.2.3 Detailed Design Procedure
      4. 6.2.4 Application Curves
  7. 7 Power Supply Recommendations
    1. 7.1 System Power-on Considerations
      1. 7.1.1 Power-on, Configuration, and Calibration
      2. 7.1.2 Power-on and Data Clock (DCLK)
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Power Planes
      2. 8.1.2 Bypass Capacitors
      3. 8.1.3 Ground Planes
      4. 8.1.4 Power System Example
    2. 8.2 Layout Example
    3. 8.3 Thermal Management
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Specification Definitions
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Specifications

4.1 Absolute Maximum Ratings(1)(2)

MIN MAX UNIT
Supply Voltage (VA, VTC, VDR, VE) 2.2 V
Supply Difference
  max(VA/TC/DR/E)- min(VA/TC/DR/E)		 0 100 mV
Voltage on Any Input Pin
(except VIN±)		 −0.15 (VA + 0.15) V
VIN± Voltage Range –0.5 2.5 V
Ground Difference
 max(GNDTC/DR/E) -min(GNDTC/DR/E)		 0 100 mV
Input Current at Any Pin(3) –50 50 mA
ADC12D1800RF Package Power Dissipation at TA ≤ 65°C(3) 4.95 W
Storage temperature, Tstg –65 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the Absolute Maximum Ratings. Recommended Operating Conditions indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE = 0V, unless otherwise specified.
(3) When the input voltage at any pin exceeds the power supply limits, i.e. less than GND or greater than VA, the current at that pin should be limited to 50 mA. In addition, over-voltage at a pin must adhere to the maximum voltage limits. Simultaneous over-voltage at multiple pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package thermal resistances from junction to case.

4.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)   ±2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
Machine model (MM) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions(1)(2)

MIN MAX UNIT
TA Ambient Temperature Range: ADC12D1800RF (Standard JEDEC thermal model) –40 50 °C
TA Ambient Temperature Range: ADC12D1800RF (Enhanced thermal model / heatsink) –40 50 °C
TJ Junction Temperature Range - applies only to maximum operating speed 120 °C
Supply Voltage (VA, VTC, VE) 1.8 2 V
Driver Supply Voltage (VDR) 1.8 VA V
VIN± Voltage Range(3) –0.4 2.4 (d.c.-coupled) V
VIN± Differential Voltage Range(4) 1.0 (d.c.-coupled at 100% duty cycle)
2.0 (d.c.-coupled a t20% duty cycle)
2.8 (d.c.-coupled at 10% duty cycle)		 V
VIN± Current Range(3) –50 50 peak (a.c.-coupled) mA
VIN± Power 15.3 (maintaining common mode voltage, a.c.-coupled)
17.1 (not maintaining common mode voltage, a.c.-coupled)		 dBm
Ground Difference
max(GNDTC/DR/E) -min(GNDTC/DR/E)		 0 V
CLK± Voltage Range 0 VA V
Differential CLK Amplitude VP-P 0.4 2 V
Common Mode Input Voltage VCMI VCMO - 150 VCMO + 150 mV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the Absolute Maximum Ratings. Recommended Operating Conditions indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE = 0V, unless otherwise specified.
(3) Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.
(4) This rating is intended for d.c.-coupled applications; the voltages listed may be safely applied to VIN± for the life-time duty-cycle of the part.

4.4 Thermal Information

THERMAL METRIC(1) ADC12D1800RF UNIT
NXA
292 PINS
RθJA Junction-to-ambient thermal resistance 16 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 2.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and C Package Thermal Metrics application report, SPRA953.

4.5 Converter Electrical Characteristics: Static Converter Characteristics

Unless otherwise specified, the following apply after calibration for VA = VDR = VTC = VE = +1.9 V; I- and Q-channels, AC-coupled, unused channel terminated to AC ground, FSR Pin = High; CL = 10 pF; Differential, AC coupled Sine Wave Sampling Clock, fCLK = 1.8 GHz at 0.5 VP-P with 50% duty cycle (as specified); VBG = Floating; Extended Control Mode with Register 6h written to 1C0Eh; Rext = Rtrim = 3300Ω ± 0.1%; Analog Signal Source Impedance = 100Ω Differential; 1:2 Demultiplex Non-DES Mode; Duty Cycle Stabilizer on. Limits are TA = 25°C, unless otherwise noted.(1)(2)(3)
PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
TYP LIM
Resolution with No Missing Codes TA = TMIN to TMAX, TJ < 105°C 12 bits
INL Integral Non-Linearity
(Best fit)		 1 MHz DC-coupled over-ranged sine wave ±2.5 LSB
DNL Differential Non-Linearity 1 MHz DC-coupled over-ranged sine wave ±0.4 LSB
VOFF Offset Error 5 LSB
VOFF_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV
PFSE Positive Full-Scale Error See (4), TA = TMIN to TMAX, TJ < 105°C ±25 mV
NFSE Negative Full-Scale Error See (4), TA = TMIN to TMAX, TJ < 105°C ±25 mV
Out-of-Range Output Code(5) (VIN+) − (VIN−) > + Full Scale, TA = TMIN to TMAX, TJ < 105°C 4095
(VIN+) − (VIN−) < − Full Scale, TA = TMIN to TMAX, TJ < 105°C 0
(1) The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC12D1800RF 30164304.gif
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).
(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 4-1. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.
(5) This parameter is specified by design and is not tested in production.

4.6 Converter Electrical Characteristics: Dynamic Converter Characteristics(1)

Limits apply TA = TMIN to TMAX, TJ < 105°C
PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
MIN TYP MAX
Bandwidth Non-DES Mode, DESCLKIQ Mode
-3 dB(2) 2.7 GHz
-6 dB 3.1 GHz
-9 dB 3.5 GHz
-12 dB 4.0 GHz
DESI Mode, DESQ Mode
-3 dB(2) 1.2 GHz
-6 dB 2.3 GHz
-9 dB 2.7 GHz
-12 dB 3.0 GHz
DESIQ Mode
-3 dB(2) 1.75 GHz
-6 dB 2.7 GHz
Gain Flatness Non-DES Mode
D.C. to Fs/2 ±0.4 dB
D.C. to Fs ±1.1 dB
D.C. to 3Fs/2 ±1.7 dB
D.C. to 2Fs ±5.7 dB
DESI, DESQ Mode
D.C. to Fs/2 ±2.7 dB
D.C. to Fs ±9.2 dB
DESIQ Mode
D.C. to Fs/2 ±1.6 dB
DESCLKIQ Mode
D.C. to Fs/2 ±1.2 dB
CER Code Error Rate 10-18 Error/
Sample
IMD3 3rd order Intermodulation Distortion DES Mode
FIN = 2670 MHz ± 2.5MHz
at -13 dBFS		 -75 dBFS
-62 dBc
FIN = 2070 MHz ± 2.5MHz
at -13 dBFS		 -85 dBFS
-72 dBc
FIN = 2670 MHz ± 2.5MHz
at -16 dBFS		 -80 dBFS
-64 dBc
FIN = 2070 MHz ± 2.5MHz
at -16 dBFS		 -83 dBFS
-67 dBc
Noise Floor Density 50Ω single-ended termination, DES Mode -155.0 dBm/Hz
-154.0 dBFS/Hz
NON-DES MODE(3)(4)(5)
ENOB Effective Number of Bits AIN = 125 MHz at -0.5 dBFS 9.3 bits
AIN = 248 MHz at -0.5 dBFS 9.3 bits
AIN = 498 MHz at -0.5 dBFS 8.4 9.3 bits
AIN = 1147 MHz at -0.5 dBFS 8.7 bits
AIN = 1448 MHz at -0.5 dBFS 8.7 bits
SINAD Signal-to-Noise Plus Distortion Ratio AIN = 125 MHz at -0.5 dBFS 57.7 dB
AIN = 248 MHz at -0.5 dBFS 57.7 dB
AIN = 498 MHz at -0.5 dBFS 52.1 57.7 dB
AIN = 1147 MHz at -0.5 dBFS 54.1 dB
AIN = 1448 MHz at -0.5 dBFS 54 dB
SNR Signal-to-Noise Ratio AIN = 125 MHz at -0.5 dBFS 58.6 dB
AIN = 248 MHz at -0.5 dBFS 58.2 dB
AIN = 498 MHz at -0.5 dBFS 52.9 58.1 dB
AIN = 1147 MHz at -0.5 dBFS 54.9 dB
AIN = 1448 MHz at -0.5 dBFS 54.3 dB
THD Total Harmonic Distortion AIN = 125 MHz at -0.5 dBFS -64.9 dB
AIN = 248 MHz at -0.5 dBFS -65.7 dB
AIN = 498 MHz at -0.5 dBFS -67 –60 dB
AIN = 1147 MHz at -0.5 dBFS -61.5 dB
AIN = 1448 MHz at -0.5 dBFS -64.9 dB
2nd Harm Second Harmonic Distortion AIN = 125 MHz at -0.5 dBFS -68.8 dBc
AIN = 248 MHz at -0.5 dBFS -85.6 dBc
AIN = 498 MHz at -0.5 dBFS -72.5 dBc
AIN = 1147 MHz at -0.5 dBFS -81.2 dBc
AIN = 1448 MHz at -0.5 dBFS -70.4 dBc
3rd Harm Third Harmonic Distortion AIN = 125 MHz at -0.5 dBFS -70.4 dBc
AIN = 248 MHz at -0.5 dBFS -67.5 dBc
AIN = 498 MHz at -0.5 dBFS -69.8 dBc
AIN = 1147 MHz at -0.5 dBFS -70.4 dBc
AIN = 1448 MHz at -0.5 dBFS -73 dBc
SFDR Spurious-Free Dynamic Range AIN = 125 MHz at -0.5 dBFS 68.1 dBc
AIN = 248 MHz at -0.5 dBFS 67 dBc
AIN = 498 MHz at -0.5 dBFS 54 71.7 dBc
AIN = 1147 MHz at -0.5 dBFS 60 dBc
AIN = 1448 MHz at -0.5 dBFS 61 dBc
DES MODE(3)(6)(4)(5)
ENOB Effective Number of Bits AIN = 125 MHz at -0.5 dBFS 9 bits
AIN = 248 MHz at -0.5 dBFS 9 bits
AIN = 498 MHz at -0.5 dBFS 9.1 bits
AIN = 1147 MHz at -0.5 dBFS 8.6 bits
AIN = 1448 MHz at -0.5 dBFS 8.6 bits
SINAD Signal-to-Noise Plus Distortion Ratio AIN = 125 MHz at -0.5 dBFS 56 dB
AIN = 248 MHz at -0.5 dBFS 56 dB
AIN = 498 MHz at -0.5 dBFS 56.5 dB
AIN = 1147 MHz at -0.5 dBFS 53.6 dB
AIN = 1448 MHz at -0.5 dBFS 53.6 dB
SNR Signal-to-Noise Ratio AIN = 125 MHz at -0.5 dBFS 57.2 dB
AIN = 248 MHz at -0.5 dBFS 57.3 dB
AIN = 498 MHz at -0.5 dBFS 57.3 dB
AIN = 1147 MHz at -0.5 dBFS 54.7 dB
AIN = 1448 MHz at -0.5 dBFS 54 dB
THD Total Harmonic Distortion AIN = 125 MHz at -0.5 dBFS -62.1 dB
AIN = 248 MHz at -0.5 dBFS -61.6 dB
AIN = 498 MHz at -0.5 dBFS -64 dB
AIN = 1147 MHz at -0.5 dBFS -59.7 dB
AIN = 1448 MHz at -0.5 dBFS -62.8 dB
2nd Harm Second Harmonic Distortion AIN = 125 MHz at -0.5 dBFS -82 dBc
AIN = 248 MHz at -0.5 dBFS -78.5 dBc
AIN = 498 MHz at -0.5 dBFS -71.1 dBc
AIN = 1147 MHz at -0.5 dBFS -76.9 dBc
AIN = 1448 MHz at -0.5 dBFS -75.3 dBc
3rd Harm Third Harmonic Distortion AIN = 125 MHz at -0.5 dBFS -64.7 dBc
AIN = 248 MHz at -0.5 dBFS -62.5 dBc
AIN = 498 MHz at -0.5 dBFS -71.4 dBc
AIN = 1147 MHz at -0.5 dBFS -60.4 dBc
AIN = 1448 MHz at -0.5 dBFS -65.8 dBc
SFDR Spurious-Free Dynamic Range AIN = 125 MHz at -0.5 dBFS 64.2 dBc
AIN = 248 MHz at -0.5 dBFS 62.4 dBc
AIN = 498 MHz at -0.5 dBFS 68.1 dBc
AIN = 1147 MHz at -0.5 dBFS 60.3 dBc
AIN = 1448 MHz at -0.5 dBFS 63.6 dBc
(1) This parameter is specified by design and/or characterization and is not tested in production.
(2) The -3 dB point is the traditional Full-Power Bandwidth (FPBW) specification. Although the insertion loss is approximately half the power at this frequency, the dynamic performance of the ADC does not necessarily begin to degrade to a level below which it may be effectively used in an application. The ADC may be used at input frequencies above the -3 dB FPBW point, for example, into the 3rd Nyquist zone. Depending on system requirements, it is only necessary to compensate for the insertion loss.
(3) The Dynamic Specifications are ensured for room to hot ambient temperature only (25°C to 85°C). Refer to the plots of the dynamic performance vs. temperature in Typical Performance Plots to see typical performance from cold to room temperature (-40°C to 25°C).
(4) The Fs/2 spur was removed from all the dynamic performance specifications.
(5) Typical dynamic performance is only tested at Fin = 498 MHz; other input frequencies are specified by design and / or characterization and are not tested in production.
(6) These measurements were taken in Extended Control Mode (ECM) with the DES Timing Adjust feature enabled (Addr: 7h). This feature is used to reduce the interleaving timing spur amplitude, which occurs at fs/2-fin, and thereby increase the SFDR, SINAD and ENOB.

4.7 Converter Electrical Characteristics: Analog Input / Output and Reference Characteristics

MIN and MAX limits apply TA = TMIN to TMAX, TJ < 105°C
PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
MIN TYP MAX
ANALOG INPUTS
VIN_FSR Analog Differential Input Full Scale Range Non-Extended Control Mode
FSR Pin High 740 800 860 mVP-P
Extended Control Mode
FM(14:0) = 4000h (default) 800 mVP-P
FM(14:0) = 7FFFh 1000 mVP-P
CIN Analog Input Capacitance,
Non-DES Mode(2)(1)		 Differential 0.02 pF
Each input pin to ground 1.6 pF
Analog Input Capacitance,
DES Mode(2)(1)		 Differential 0.08 pF
Each input pin to ground 2.2 pF
RIN Differential Input Resistance 91 100 109 Ω
COMMON MODE OUTPUT
VCMO Common Mode Output Voltage ICMO = ±100 µA 1.15 1.25 1.35 V
TC_VCMO Common Mode Output Voltage Temperature Coefficient ICMO = ±100 µA(3) 38 ppm/°C
VCMO_LVL VCMO input threshold to set
DC-coupling Mode		 See (3) 0.63 V
CL_VCMO Maximum VCMO Load Capacitance See (2) 80 pF
BANDGAP REFERENCE
VBG Bandgap Reference Output Voltage IBG = ±100 µA 1.15 1.25 1.35 V
TC_VBG Bandgap Reference Voltage Temperature Coefficient IBG = ±100 µA(3) 32 ppm/°C
CL_VBG Maximum Bandgap Reference load Capacitance See (2) 80 pF
(1) The differential and pin-to-ground input capacitances are lumped capacitance values from design; they are defined as shown below.

ADC12D1800RF 30164395.gif
(2) This parameter is specified by design and is not tested in production.
(3) This parameter is specified by design and/or characterization and is not tested in production.

4.8 Converter Electrical Characteristics: I-Channel to Q-Channel Characteristics

PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
TYP LIM
Offset Match See (1) 2 LSB
Positive Full-Scale Match Zero offset selected in
Control Register		 2 LSB
Negative Full-Scale Match Zero offset selected in
Control Register		 2 LSB
Phase Matching (I, Q) fIN = 1.0 GHz(1) < 1 Degree
X-TALK Crosstalk from I-channel (Aggressor) to Q-channel (Victim) Aggressor = 867 MHz F.S.
Victim = 100 MHz F.S.		 −70 dB
Crosstalk from Q-channel (Aggressor) to I-channel (Victim) Aggressor = 867 MHz F.S.
Victim = 100 MHz F.S.		 −70 dB
(1) This parameter is specified by design and/or characterization and is not tested in production.

4.9 Converter Electrical Characteristics: Sampling Clock Characteristics

Limits apply TA = TMIN to TMAX, TJ < 105°C
PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
MIN TYP MAX
VIN_CLK Differential Sampling Clock Input Level(1) Sine Wave Clock
Differential Peak-to-Peak		 0.4 0.6 2.0 VP-P
Square Wave Clock
Differential Peak-to-Peak		 0.4 0.6 2.0 VP-P
CIN_CLK Sampling Clock Input Capacitance(2) Differential 0.1 pF
Each input to ground 1 pF
RIN_CLK Sampling Clock Differential Input Resistance See (1) 100 Ω
(1) This parameter is specified by design and/or characterization and is not tested in production.
(2) This parameter is specified by design and is not tested in production.

4.10 Converter Electrical Characteristics: AutoSync Feature Characteristics

PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
TYP LIM
VIN_RCLK Differential RCLK Input Level(1) Differential Peak-to-Peak 360 mVP-P
CIN_RCLK RCLK Input Capacitance(1) Differential 0.1 pF
Each input to ground 1 pF
RIN_RCLK RCLK Differential Input Resistance See (1) 100 Ω
IIH_RCLK Input Leakage Current;
VIN = VA		 22 µA
IIL_RCLK Input Leakage Current;
VIN = GND		 -33 µA
VO_RCOUT Differential RCOut Output Voltage 360 mV
(1) This parameter is specified by design and/or characterization and is not tested in production.

4.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics

Limits apply TA = TMIN to TMAX, TJ < 105°C
PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
MIN TYP MAX
DIGITAL CONTROL PINS (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)
VIH Logic High Input Voltage 0.7×VA 0.3×VA V
VIL Logic Low Input Voltage
IIH Input Leakage Current;
VIN = VA		 0.02 μA
IIL Input Leakage Current;
VIN = GND		 FSR, CalDly, CAL, NDM, TPM, DDRPh, DES -0.02 μA
SCS, SCLK, SDI -17 μA
PDI, PDQ, ECE -38 μA
CIN_DIG Digital Control Pin Input Capacitance(2) Measured from each control pin to GND 1.5 pF
DIGITAL OUTPUT PINS (Data, DCLKI, DCLKQ, ORI, ORQ)
VOD LVDS Differential Output Voltage VBG = Floating, OVS = High 400 630 800 mVP-P
VBG = Floating, OVS = Low 230 460 630 mVP-P
VBG = VA, OVS = High 670 mVP-P
VBG = VA, OVS = Low 500 mVP-P
ΔVO DIFF Change in LVDS Output Swing Between Logic Levels ±1 mV
VOS Output Offset Voltage(1) VBG = Floating 0.8 V
VBG = VA 1.2 V
ΔVOS Output Offset Voltage Change Between Logic Levels See (2) ±1 mV
IOS Output Short Circuit Current(1) VBG = Floating;
D+ and D− connected to 0.8V		 ±4 mA
ZO Differential Output Impedance See (1) 100 Ω
VOH Logic High Output Level CalRun, IOH = −100 µA,(1)
SDO, IOH = −400 µA(1)		 1.65 V
VOL Logic Low Output Level CalRun, IOL = 100 µA,(1)
SDO, IOL = 400 µA(1)		 0.15 V
DIFFERENTIAL DCLK RESET PINs (DCLK_RST)
VCMI_DRST DCLK_RST Common Mode Input Voltage See (1) 1.25 V
VID_DRST Differential DCLK_RST Input Voltage See (1) VIN_CLK VP-P
RIN_DRST Differential DCLK_RST Input Resistance See (1) 100 Ω
(1) This parameter is specified by design and/or characterization and is not tested in production.
(2) This parameter is specified by design and is not tested in production.

4.12 Converter Electrical Characteristics: Power Supply Characteristics

Limits apply TA = TMIN to TMAX, TJ < 105°C
PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
TYP MAX
IA Analog Supply Current PDI = PDQ = Low 1360 mA
PDI = Low; PDQ = High 745 mA
PDI = High; PDQ = Low 745 mA
PDI = PDQ = High 2.7 mA
ITC Track-and-Hold and Clock Supply Current PDI = PDQ = Low 515 mA
PDI = Low; PDQ = High 305 mA
PDI = High; PDQ = Low 305 mA
PDI = PDQ = High 650 µA
IDR Output Driver Supply Current PDI = PDQ = Low 275 mA
PDI = Low; PDQ = High 145 mA
PDI = High; PDQ = Low 145 mA
PDI = PDQ = High 6 µA
IE Digital Encoder Supply Current PDI = PDQ = Low 110 mA
PDI = Low; PDQ = High 65 mA
PDI = High; PDQ = Low 65 mA
PDI = PDQ = High 34 µA
ITOTAL Total Supply Current 1:2 Demux Mode
PDI = PDQ = Low		 2260 2481 mA
Non-Demux Mode
PDI = PDQ = Low		 2220 mA
PC Power Consumption 1:2 Demux Mode
PDI = PDQ = Low 4.29 4.7 W
PDI = Low; PDQ = High 2.39 W
PDI = High; PDQ = Low 2.39 W
PDI = PDQ = High 6.5 mW
Non-Demux Mode
PDI = PDQ = Low 4.22 W

4.13 Converter Electrical Characteristics: AC Electrical Characteristics

Limits apply for TA = TMIN to TMAX, TJ < 105°C
PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
MIN TYP MAX
SAMPLING CLOCK (CLK)
fCLK (max) Maximum Sampling Clock Frequency 1.8 GHz
fCLK (min) Minimum Sampling Clock Frequency Non-DES Mode; LFS = 0b 300 MHz
Non-DES Mode; LFS = 1b 150 MHz
DES Mode 500 MHz
Sampling Clock Duty Cycle fCLK(min) ≤ fCLK ≤ fCLK(max)(1) 20% 50% 80%
tCL Sampling Clock Low Time See (2) 111 278 ps
tCH Sampling Clock High Time See (2) 111 278 ps
DATA CLOCK (DCLKI, DCLKQ)
DCLK Duty Cycle See (2) 45% 50% 55%
tSR Setup Time DCLK_RST± See (1) 45 ps
tHR Hold Time DCLK_RST± See (1) 45 ps
tPWR Pulse Width DCLK_RST± See (2) 5 Sampling Clock Cycles
tSYNC_DLY DCLK Synchronization Delay 90° Mode(2) 4 Sampling Clock Cycles
0° Mode(2) 5
tLHT Differential Low-to-High Transition Time 10%-to-90%, CL = 2.5 pF(1) 200 ps
tHLT Differential High-to-Low Transition Time 10%-to-90%, CL = 2.5 pF(1) 200 ps
tSU Data-to-DCLK Setup Time 90° Mode(2) 430 ps
tH DCLK-to-Data Hold Time 90° Mode(2) 430 ps
tOSK DCLK-to-Data Output Skew 50% of DCLK transition to 50% of Data transition(2) ±50 ps
DATA INPUT-TO-OUTPUT
tAD Aperture Delay(1) Sampling CLK+ Rise to Acquisition of Data 1.29 ns
tAJ Aperture Jitter See (1) 0.2 ps (rms)
tOD Sampling Clock-to Data Output Delay (in addition to Latency) 50% of Sampling Clock transition to 50% of Data transition(1) 3.2 ns
tLAT Latency in 1:2 Demux Non-DES Mode(2) DI, DQ Outputs 34 Sampling Clock Cycles
DId, DQd Outputs 35
Latency in 1:4 Demux DES Mode(2) DI Outputs 34
DQ Outputs 34.5
DId Outputs 35
DQd Outputs 35.5
Latency in Non-Demux Non-DES Mode(2) DI Outputs 34
DQ Outputs 34
Latency in Non-Demux DES Mode(2) DI Outputs 34
DQ Outputs 34.5
tORR Over Range Recovery Time Differential VIN step from ±1.2V to 0V to accurate conversion(1) 1 Sampling Clock Cycle
tWU Wake-Up Time (PDI/PDQ low to Rated Accuracy Conversion) Non-DES Mode(2) 500 ns
DES Mode(2) 1 µs
(1) This parameter is specified by design and/or characterization and is not tested in production.
(2) This parameter is specified by design and is not tested in production.

4.14 Converter Electrical Characteristics: Serial Port Interface

Limits apply for TA = TMIN to TMAX, TJ < 105°C
PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
TYP MIN
fSCLK Serial Clock Frequency See (2) 15 MHz
Serial Clock Low Time 30 ns
Serial Clock High Time 30 ns
tSSU Serial Data-to-Serial Clock Rising Setup Time See (1) 2.5 ns
tSH Serial Data-to-Serial Clock Rising Hold Time See (2) 1 ns
tSCS SCS-to-Serial Clock Rising Setup Time See (1) 2.5 ns
tHCS SCS-to-Serial Clock Falling Hold Time See (1) 1.5 ns
tBSU Bus turn-around time See (1) 10 ns
(1) This parameter is specified by design and/or characterization and is not tested in production.
(2) This parameter is specified by design and is not tested in production.

4.15 Converter Electrical Characteristics Calibration

Limits apply for TA = TMIN to TMAX, TJ < 105°C
PARAMETER TEST CONDITIONS ADC12D1800RF UNIT
MIN TYP MAX
tCAL Calibration Cycle Time Non-ECM 4.1·107 Sampling Clock Cycles
ECM CSS = 0b
ECM CSS = 1b
tCAL_L CAL Pin Low Time See (1) 1280 Sampling Clock Cycles
tCAL_H CAL Pin High Time See (1) 1280
tCalDly Calibration delay determined by CalDly Pin(1) CalDly = Low 224 Sampling Clock Cycles
CalDly = High 230
(1) This parameter is specified by design and is not tested in production.
ADC12D1800RF 30164322.gifFigure 4-1 Input / Output Transfer Characteristic
ADC12D1800RF 30164359.gif
*The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.
Figure 4-2 Clocking in 1:2 Demux Non-DES Mode*
ADC12D1800RF 30164360.gif
*The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.
Figure 4-3 Clocking in Non-Demux Non-DES Mode*
ADC12D1800RF 30164399.gif
*The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.
Figure 4-4 Clocking in 1:4 Demux DES Mode*
ADC12D1800RF 30164396.gif
*The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.
Figure 4-5 Clocking in Non-Demux Mode DES Mode*
ADC12D1800RF 30164320.gifFigure 4-6 Data Clock Reset Timing (Demux Mode)
ADC12D1800RF 30164325.gifFigure 4-7 Power-on and On-Command Calibration Timing
ADC12D1800RF 30164319.gifFigure 4-8 Serial Interface Timing

4.16 Typical Characteristics

VA = VDR = VTC = VE = 1.9V, fCLK = 1.8 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux Non-DES Mode has similar performance), unless otherwise stated.

ADC12D1800RF 30164338.gifFigure 4-9 INL vs. Code (ADC12D1800RF)
ADC12D1800RF 30164339.gifFigure 4-11 DNL vs. Code (ADC12D1800RF)
ADC12D1800RF 30164376.gifFigure 4-13 ENOB vs. Temperature (ADC12D1800RF)
ADC12D1800RF 30164378.gifFigure 4-15 ENOB vs. Clock Frequency (ADC12D1800RF)
ADC12D1800RF 30164342.gifFigure 4-17 ENOB vs. VCMI (ADC12D1800RF)
ADC12D1800RF 30164369.gifFigure 4-19 SNR vs. Supply Voltage (ADC12D1800RF)
ADC12D1800RF 30164371.gifFigure 4-21 SNR vs. Input Frequency (ADC12D1800RF)
ADC12D1800RF 30164373.gifFigure 4-23 THD vs. Supply Voltage (ADC12D1800RF)
ADC12D1800RF 30164375.gifFigure 4-25 THD vs. Input Frequency (ADC12D1800RF)
ADC12D1800RF 30164384.gifFigure 4-27 SFDR vs. Supply Voltage (ADC12D1800RF)
ADC12D1800RF 30164383.gifFigure 4-29 SFDR vs. Input Frequency (ADC12D1800RF)
ADC12D1800RF 30164387.gifFigure 4-31 Spectral Response DESI Mode (ADC12D1800RF)
ADC12D1800RF 30164363.gifFigure 4-33 Crosstalk vs. Source Frequency (ADC12D1800RF)
ADC12D1800RF 30164381.gifFigure 4-35 Power Consumption vs. Clock Frequency (ADC12D1800RF)
ADC12D1800RF 30164340.gifFigure 4-10 INL vs. Temperature (ADC12D1800RF)
ADC12D1800RF 30164341.gifFigure 4-12 DNL vs. Temperature (ADC12D1800RF)
ADC12D1800RF 30164377.gifFigure 4-14 ENOB vs. Supply Voltage (ADC12D1800RF)
ADC12D1800RF 30164379.gifFigure 4-16 ENOB vs. Input Frequency (ADC12D1800RF)
ADC12D1800RF 30164368.gifFigure 4-18 SNR vs. Temperature (ADC12D1800RF)
ADC12D1800RF 30164370.gifFigure 4-20 SNR vs. Clock Frequency (ADC12D1800RF)
ADC12D1800RF 30164372.gifFigure 4-22 THD vs. Temperature (ADC12D1800RF)
ADC12D1800RF 30164374.gifFigure 4-24 THD vs. Clock Frequency (ADC12D1800RF)
ADC12D1800RF 30164385.gifFigure 4-26 SFDR vs. Temperature (ADC12D1800RF)
ADC12D1800RF 30164382.gifFigure 4-28 SFDR vs. Clock Frequency (ADC12D1800RF)
ADC12D1800RF 30164389.gifFigure 4-30 Spectral Response Non-DES Mode (ADC12D1800RF)
ADC12D1800RF 30164391.gifFigure 4-32 Spectral Response DESCLKIQ Mode (ADC12D1800RF)
ADC12D1800RF 30164348.gifFigure 4-34 Insertion Loss (ADC12D1800RF)