SLVSDR2B November 2018 – March 2021 ADC12DJ3200QML-SP
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The ADC12DJ3200QML-SP can be used as a dual-channel ADC where the sampling rate is equal to the clock frequency (fS = fCLK) provided at the CLK+ and CLK– pins. The two inputs, AIN± and BIN±, serve as the respective inputs for each channel in this mode. This mode is chosen simply by setting JMODE to the appropriate setting for the desired configuration as described in Table 7-18. The analog inputs can be swapped by setting DUAL_INPUT (see the input mux control register)