SLVSDR2B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZMX|196
  • NWE|196
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5.2 Decimation Filters

The decimation filters are arranged to provide a programmable overall decimation of 2, 4, 8, or 16. All filter outputs have a resolution of 15 bits. The decimate-by-2 filter has a real output and the decimate-by-4, decimate-by-8, and decimate-by-16 filters have complex outputs. Table 7-10 lists the effective output sample rates, available signal bandwidths, output formats, and stop-band attenuation for each decimation mode. The available bandwidths of the complex output modes are twice that of equivalent real decimation modes because of the nature of the I/Q data and complex signaling. This higher bandwidth results in the decimate-by-2 real and decimate-by-4 complex modes having approximately the same useful output bandwidth.

Table 7-10 Output Sample Rates and Signal Bandwidths
DECIMATION SETTINGƒ(DEVCLK)OUTPUT FORMAT
OUTPUT RATE (MSPS)MAX ALIAS PROTECTED SIGNAL BANDWIDTH (MHz)STOP-BAND ATTENUATIONPASS-BAND RIPPLE
No decimationƒ(DEVCLK)ƒ(DEVCLK) / 2—< ±0.001 dBReal signal, 12-bit data
Decimate-by-2ƒ(DEVCLK) / 20.4 × ƒ(DEVCLK) / 2> 89 dB< ±0.001 dBReal signal, 15-bit data
Decimate-by-4
(D4_AP87 = 0)		ƒ(DEVCLK) / 40.8 × ƒ(DEVCLK) / 4> 90 dB< ±0.001 dBComplex signal, 15-bit data
Decimate-by-4
(D4_AP87 = 1)		ƒ(DEVCLK) / 40.875 × ƒ(DEVCLK) / 4> 66 dB< ±0.005 dBComplex signal, 15-bit data
Decimate-by-8ƒ(DEVCLK) / 80.8 × ƒ(DEVCLK) / 8> 90 dB< ±0.001 dBComplex signal, 15-bit data
Decimate-by-16ƒ(DEVCLK) / 160.8 × ƒ(DEVCLK) / 16> 90 dB< ±0.001 dBComplex signal, 15-bit data

Figure 7-7 to Figure 7-18 provide the composite decimation filter responses. The pass-band section (black trace) shows the alias-protected region of the response. The transition band (red trace) shows the transition region of the response, or the regions that alias into the transition region, which is not alias protected and therefore desired signals must not be within this band. The aliasing band (blue trace) shows the attenuation applied to the bands that alias back into the pass band after decimation and are sufficiently low to prevent undesired signals from showing up in the pass band. Use analog input filtering for additional attenuation of the aliasing band or to prevent harmonics, interleaving spurs, or other undesired spurious signals from folding into the desired signal band before the decimation filter.

GUID-0F29A081-A0E2-4F2E-8825-BD8907C6C35A-low.gifFigure 7-7 Decimate-by-2 Composite Response (D2_HIGH_PASS = 0)
GUID-D4ACF8D7-3E77-4FEE-9246-FA6B1B465253-low.gifFigure 7-9 Decimate-by-2 Composite Response (D2_HIGH_PASS = 1)
GUID-F48024E6-E9BD-49DF-B5E9-5EE1204E623C-low.gifFigure 7-11 Decimate-by-4 Composite Response (D4_AP87 = 0)
GUID-0BAB8008-E4CC-454A-9B74-AC746EBAE3FA-low.gifFigure 7-13 Decimate-by-4 Composite Response (D4_AP87 = 1)
GUID-8D26F336-209F-4BA8-AB6B-A3946E7B8F9F-low.gifFigure 7-15 Decimate-by-8 Composite Response
GUID-24E37CA7-44C2-4CFC-93A0-A658BEEB422E-low.gifFigure 7-17 Decimate-by-16 Composite Response
GUID-91426F14-46F5-4D83-BCF5-1AFE0B2B3CEC-low.gifFigure 7-8 Decimate-by-2 Composite Zoomed Pass-Band Response (D2_HIGH_PASS = 0)
GUID-5BA3A3F7-D2A9-4FDA-8F6C-F79837687B20-low.gifFigure 7-10 Decimate-by-2 Composite Zoomed Pass-Band Response (D2_HIGH_PASS = 1)
GUID-AD7FA018-E112-4C87-ADFA-68D2AEFB51DA-low.gifFigure 7-12 Decimate-by-4 Composite Zoomed Pass-Band Response (D4_AP87 = 0)
GUID-D80EBD25-4B29-453F-87DA-4FBC1AA0C529-low.gifFigure 7-14 Decimate-by-4 Composite Zoomed Pass-Band Response (D4_AP87 = 1)
GUID-020C3277-AAEC-4A4B-A762-4041637900D6-low.gifFigure 7-16 Decimate-by-8 Composite Zoomed Pass-Band Response
GUID-C30B9E5A-88B6-46BF-ACD1-702FD3DBC451-low.gifFigure 7-18 Decimate-by-16 Composite Zoomed Pass-Band Response

For maximum efficiency, a group of high-speed filter blocks are implemented with specific blocks used for each decimation setting to achieve the composite responses illustrated in Figure 7-7 to Figure 7-18. Table 7-11 describes the combination of filter blocks used for each decimation setting and Table 7-12 lists the coefficient details and decimation factor of each filter block. The coefficients are symmetric with the center tap indicated by bold text.

Table 7-11 Decimation Mode Filter Usage
DECIMATION SETTINGFILTER BLOCKS USED
2CS80
4 (D4_AP87 = 0)CS45, CS80
4 (D4_AP87 = 1)CS45, CS87
8CS20, CS40, CS80
16CS10, CS20, CS40, CS80
Table 7-12 Filter Coefficient Details
FILTER COEFFICIENT SET (Decimation Factor of Filter)
CS10 (2)CS20 (2)CS40 (2)CS45 (2)CS80 (2)CS87 (2)
–65–65109109–327–3275656–37–37–15–15
000000000000
577577–837–83722312231–401–4011181182323
10240000000000
48244824–8881–888115961596–291–291–40–40
819200000000
3974239742–4979–49796126126464
65536000000
2011320113–1159–1159–97–97
327680000
20312031142142
0000
–3356–3356–201–201
0000
53085308279279
0000
–8140–8140–380–380
0000
1228412284513513
0000
–18628–18628–690–690
0000
2945529455939939
0000
–53191–53191–1313–1313
0000
16605916605919561956
26214400
–3398–3398
00
1040410404
16384