SLVSDR2B November 2018 – March 2021 ADC12DJ3200QML-SP
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The ADC12DJ3200QML-SP clock inputs must be AC-coupled to the device to provide rated performance. The clock source must have extremely low jitter (integrated phase noise) to achieve rated performance. Recommended clock synthesizers include the LMX2615-SP.
The JESD204B data converter system (ADC plus FPGA) requires additional SYSREF and device clocks. The LMK04832 device is an excellent choice to generate these clocks. Depending on the ADC clock frequency and jitter requirements, this device may also be used as the system clock synthesizer or as a device clock and SYSREF distribution device when multiple ADC12DJ3200QML-SP devices are used in a system.