SLVSEO0C August   2021  – June 2024 ADC12DJ4000RF

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 Analog Reference Voltage
        4. 7.3.2.4 ADC Overrange Detection
        5. 7.3.2.5 Code Error Rate (CER)
      3. 7.3.3 Temperature Monitoring Diode
      4. 7.3.4 Timestamp
      5. 7.3.5 Clocking
        1. 7.3.5.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.5.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.5.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.5.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.5.3.2 Automatic SYSREF Calibration
      6. 7.3.6 Programmable FIR Filter (PFIR)
        1. 7.3.6.1 Dual Channel Equalization
        2. 7.3.6.2 Single Channel Equalization
        3. 7.3.6.3 Time Varying Filter
      7. 7.3.7 Digital Down Converters (DDC)
        1. 7.3.7.1 Rounding and Saturation
        2. 7.3.7.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.7.2.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.7.2.2 NCO Selection
          3. 7.3.7.2.3 Basic NCO Frequency Setting Mode
          4. 7.3.7.2.4 Rational NCO Frequency Setting Mode
          5. 7.3.7.2.5 NCO Phase Offset Setting
          6. 7.3.7.2.6 NCO Phase Synchronization
        3. 7.3.7.3 Decimation Filters
        4. 7.3.7.4 Output Data Format
        5. 7.3.7.5 Decimation Settings
          1. 7.3.7.5.1 Decimation Factor
          2. 7.3.7.5.2 DDC Gain Boost
      8. 7.3.8 JESD204C Interface
        1. 7.3.8.1  Transport Layer
        2. 7.3.8.2  Scrambler
        3. 7.3.8.3  Link Layer
        4. 7.3.8.4  8B/10B Link Layer
          1. 7.3.8.4.1 Data Encoding (8B/10B)
          2. 7.3.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.8.4.3 Code Group Synchronization (CGS)
          4. 7.3.8.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.8.4.5 Frame and Multiframe Monitoring
        5. 7.3.8.5  64B/66B Link Layer
          1. 7.3.8.5.1 64B/66B Encoding
          2. 7.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.8.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.8.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.8.5.4 Initial Lane Alignment
          5. 7.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.8.6  Physical Layer
        7. 7.3.8.7  SerDes Pre-Emphasis
        8. 7.3.8.8  JESD204C Enable
        9. 7.3.8.9  Multi-Device Synchronization and Deterministic Latency
        10. 7.3.8.10 Operation in Subclass 0 Systems
      9. 7.3.9 Alarm Monitoring
        1. 7.3.9.1 NCO Upset Detection
        2. 7.3.9.2 Clock Upset Detection
        3. 7.3.9.3 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
        5. 7.4.4.5 Dual DDC and Redundant Data Mode
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
          2. 7.4.6.5.2 Long Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8 JESD204C Interface

The ADC12DJ4000RF uses a JESD204C high-speed serial interface for data converters to transfer data from the ADC to the receiving logic device. Many of the available JESD204C output formats are backwards compatible with existing JESD204B receivers, including many of the JESD204B modes in the ADC12DJ2700 and ADC12DJ3200. The device serialized lanes are capable of operating with both 8B/10B encoding and 64B/66B encoding. A maximum of 16 lanes can be used to lower lane rates for interfacing with speed-limited logic devices. There are a few differences between 8B/10B and 64B/66B encoded JESD204C, which will be described throughout this section. Figure 7-19 shows a simplified block diagram of the 8B/10B encoded JESD204C interface and Figure 7-20 shows a simplified block diagram of the 64B/66B encoded JESD204C interface.

ADC12DJ4000RF Simplified 8B/10B Encoded JESD204C Interface DiagramFigure 7-19 Simplified 8B/10B Encoded JESD204C Interface Diagram
ADC12DJ4000RF Simplified 64B/66B Encoded JESD204C Interface DiagramFigure 7-20 Simplified 64B/66B Encoded JESD204C Interface Diagram

The various signals used in the JESD204C interface and the associated the device pin names are summarized briefly in Table 7-16 for reference. Most of the signals are common between 8B/10B and 64B/66B encoded JESD204C, except for SYNC which is not needed to achieve block synchronization for 64B/66B encoding. The sync header encoded into the data stream is used for block synchronization instead of the SYNC signal.

Table 7-16 Summary of JESD204C Signals
SIGNAL NAMEPIN NAMES8B/10B64B/66BDESCRIPTION
DataDA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)YesYesHigh-speed serialized data after 8B/10B or 64B/66B encoding
SYNCSYNCSE, TMSTP+, TMSTP–YesNoLink initialization signal (handshake), toggles low to start code group synchronization (CGS) process. Not used for 64B/66B encoding modes, unless it is used for NCO synchronization purposes.
Device clockCLK+, CLK–YesYesADC sampling clock, also used for clocking digital logic and output serializers
SYSREFSYSREF+, SYSREF–YesYesSystem timing reference used to deterministically reset the internal local multiframe clock (LMFC) or local extended multiblock clock (LEMC) counters in each JESD204C device

Not all optional features of JESD204C are supported by the device. The list of features that are supported and the features that are not supported is provided in Table 7-17.

Table 7-17 Declaration of Supported JESD204C Features
LETTER IDENTIFIERREFERENCE CLAUSEFEATURESUPPORT IN ADC12DJ4000RF
aclause 88B/10B link layerSupported
bclause 764B/66B link layerSupported
cclause 764B/80B link layerNot supported
dclause 7The command channel when using the 64B/66B or 64B/80B link layerNot supported
eclause 7Forward error correction (FEC) when using the 64B/66B or 64B/80B link layerSupported
fclause 7CRC3 when using the 64B/66B or 64B/80B link layerNot supported
gclause 8A physical SYNC pin when using the 8B/10B link layerSupported
hclause 7, clause 8Subclass 0Not supported, but subclass 1 transmitter is compatible with subclass 0 receiver
iclause 7, clause 8Subclass 1Supported
jclause 8Subclass 2Not supported
kclause 7, clause 8Lane alignment within a single linkSupported
lclause 7, clause 8Subclass 1 with support for a lane alignment on a multipoint link by means of the MULTIREF signalNot supported
mclause 8SYNC interface timing is compatible with JESD204ASupported
nclause 8SYNC interface timing is compatible with JESD204BSupported