SLVSGH5B March   2023  – June 2024 ADC12DJ5200SE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Device Comparison
      2. 6.3.2  Analog Inputs
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
      3. 6.3.3  ADC Core
        1. 6.3.3.1 ADC Theory of Operation
        2. 6.3.3.2 ADC Core Calibration
        3. 6.3.3.3 Analog Reference Voltage
        4. 6.3.3.4 ADC Overrange Detection
        5. 6.3.3.5 Code Error Rate (CER)
      4. 6.3.4  Temperature Monitoring Diode
      5. 6.3.5  Timestamp
      6. 6.3.6  Clocking
        1. 6.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.6.3.2 Automatic SYSREF Calibration
      7. 6.3.7  Programmable FIR Filter (PFIR)
        1. 6.3.7.1 Dual Channel Equalization
        2. 6.3.7.2 Single Channel Equalization
        3. 6.3.7.3 Time Varying Filter
      8. 6.3.8  Digital Down Converters (DDC)
        1. 6.3.8.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 6.3.8.1.1 NCO Fast Frequency Hopping (FFH)
          2. 6.3.8.1.2 NCO Selection
          3. 6.3.8.1.3 Basic NCO Frequency Setting Mode
          4. 6.3.8.1.4 Rational NCO Frequency Setting Mode
          5. 6.3.8.1.5 NCO Phase Offset Setting
          6. 6.3.8.1.6 52
          7. 6.3.8.1.7 NCO Phase Synchronization
        2. 6.3.8.2 Decimation Filters
        3. 6.3.8.3 Output Data Format
        4. 6.3.8.4 Decimation Settings
          1. 6.3.8.4.1 Decimation Factor
          2. 6.3.8.4.2 DDC Gain Boost
      9. 6.3.9  JESD204C Interface
        1. 6.3.9.1 Transport Layer
        2. 6.3.9.2 Scrambler
        3. 6.3.9.3 Link Layer
        4. 6.3.9.4 8B/10B Link Layer
          1. 6.3.9.4.1 Data Encoding (8B/10B)
          2. 6.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.9.4.3 Code Group Synchronization (CGS)
          4. 6.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.9.4.5 Frame and Multiframe Monitoring
        5. 6.3.9.5 64B/66B Link Layer
          1. 6.3.9.5.1 64B/66B Encoding
          2. 6.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 6.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 6.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 6.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 6.3.9.5.4 Initial Lane Alignment
          5. 6.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.9.6 Physical Layer
          1. 6.3.9.6.1 SerDes Pre-Emphasis
        7. 6.3.9.7 JESD204C Enable
        8. 6.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 6.3.9.9 Operation in Subclass 0 Systems
      10. 6.3.10 Alarm Monitoring
        1. 6.3.10.1 NCO Upset Detection
        2. 6.3.10.2 Clock Upset Detection
        3. 6.3.10.3 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode
      2. 6.4.2 Single-Channel Mode (DES Mode)
      3. 6.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 6.4.4 JESD204C Modes
        1. 6.4.4.1 JESD204C Operating Modes Table
        2. 6.4.4.2 JESD204C Modes cont.
        3. 6.4.4.3 JESD204C Transport Layer Data Formats
        4. 6.4.4.4 64B/66B Sync Header Stream Configuration
        5. 6.4.4.5 Dual DDC and Redundant Data Mode
      5. 6.4.5 Power-Down Modes
      6. 6.4.6 Test Modes
        1. 6.4.6.1 Serializer Test-Mode Details
        2. 6.4.6.2 PRBS Test Modes
        3. 6.4.6.3 Clock Pattern Mode
        4. 6.4.6.4 Ramp Test Mode
        5. 6.4.6.5 Short and Long Transport Test Mode
          1. 6.4.6.5.1 Short Transport Test Pattern
          2. 6.4.6.5.2 Long Transport Test Pattern
        6. 6.4.6.6 D21.5 Test Mode
        7. 6.4.6.7 K28.5 Test Mode
        8. 6.4.6.8 Repeated ILA Test Mode
        9. 6.4.6.9 Modified RPAT Test Mode
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
        2. 6.4.7.2 Background Calibration Mode
        3. 6.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 Streaming Mode
    6. 6.6 SPI Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Wideband RF Sampling Receiver
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
        2. 7.2.1.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.10.1 NCO Upset Detection

The NCO_ALM register bit indicates if the NCO in channel A or B has been upset. The NCO phase accumulators in channel A are continuously compared to channel B. If the accumulators differ for even one clock cycle, the NCO_ALM register bit is set and remains set until cleared by the host system by writing a 1. This feature requires the phase and frequency words for each NCO accumulator in DDC A (PHASEAx, FREQAx) to be set to the same values as the NCO accumulators in DDC B (PHASEBx, FREQBx). For example, PHASEA0 must be the same as PHASEB0 and FREQA0 must be the same as FREQB0, however, PHASEA1 can be set to a different value than PHASEA0. This requirement ultimately reduces the number of NCO frequencies available for phase coherent frequency hopping from four to two for each DDC. DDC B can use a different NCO frequency than DDC A by setting the NCOB[1:0] pins to a different value than NCOA[1:0]. This detection is only valid after the NCOs are synchronized by either SYSREF or the start of the ILA sequence (as determined by the NCO synchronization register). For the NCO upset detection to work properly, follow these steps:

  1. Program JESD_EN = 0
  2. Make sure the device is configured to use both channels (PD_ACH = 0, PD_BCH = 0)
  3. Select a JMODE that uses the NCO
  4. Program all NCO frequencies and phases to be the same for channel A and B (for example, FREQA0 = FREQB0, FREQA1 = FREQB1, FREQA2 = FREQB2, and FREQA3 = FREQB3)
  5. If desired, use the CMODE and CSEL registers or the NCOA[1:0] and NCOB[1:0] pins to choose a unique frequency for channel A and channel B
  6. Program JESD_EN = 1
  7. Synchronize the NCOs (using SYNC or using SYSREF); see the NCO synchronization register
  8. Write a 1 to the NCO_ALM register bit to clear it
  9. Monitor the NCO_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured
  10. If the frequency or phase registers are changed while the NCO is enabled, the NCOs can get out of synchronization
  11. Repeat steps 7-9
  12. If the device enters and exits global power down, repeat steps 7-9