SBASAG0A October   2021  – October 2024 ADC12DJ800 , ADC12QJ800 , ADC12SJ800

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
        4. 6.3.2.4 ADC Core
          1. 6.3.2.4.1 ADC Theory of Operation
          2. 6.3.2.4.2 ADC Core Calibration
          3. 6.3.2.4.3 Analog Reference Voltage
          4. 6.3.2.4.4 ADC Over-range Detection
          5. 6.3.2.4.5 Code Error Rate (CER)
      3. 6.3.3 Temperature Monitoring Diode
      4. 6.3.4 Timestamp
      5. 6.3.5 Clocking
        1. 6.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 6.3.6 JESD204C Interface
        1. 6.3.6.1  Transport Layer
        2. 6.3.6.2  Scrambler
        3. 6.3.6.3  Link Layer
        4. 6.3.6.4  8B/10B Link Layer
          1. 6.3.6.4.1 Data Encoding (8B/10B)
          2. 6.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.6.4.3 Code Group Synchronization (CGS)
          4. 6.3.6.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.6.4.5 Frame and Multiframe Monitoring
        5. 6.3.6.5  64B/66B Link Layer
          1. 6.3.6.5.1 64B/66B Encoding
          2. 6.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 6.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 6.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 6.3.6.5.3 Initial Lane Alignment
          4. 6.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.6.6  Physical Layer
          1. 6.3.6.6.1 SerDes Pre-Emphasis
        7. 6.3.6.7  JESD204C Enable
        8. 6.3.6.8  Multi-Device Synchronization and Deterministic Latency
        9. 6.3.6.9  Operation in Subclass 0 Systems
        10. 6.3.6.10 Alarm Monitoring
          1. 6.3.6.10.1 Clock Upset Detection
          2. 6.3.6.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1 Serializer Test-Mode Details
        2. 6.4.4.2 PRBS Test Modes
        3. 6.4.4.3 Clock Pattern Mode
        4. 6.4.4.4 Ramp Test Mode
        5. 6.4.4.5 Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6 D21.5 Test Mode
        7. 6.4.4.7 K28.5 Test Mode
        8. 6.4.4.8 Repeated ILA Test Mode
        9. 6.4.4.9 Modified RPAT Test Mode
      5. 6.4.5 Calibration Modes and Trimming
        1. 6.4.5.1 Foreground Calibration Mode
        2. 6.4.5.2 Background Calibration Mode
        3. 6.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 6.4.6 Offset Calibration
      7. 6.4.7 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
      7. 6.5.7 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10 Typical Characteristics

Typical values at 25°C, AIN = -1 dBFS, FIN = 347 MHz, FS = 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL off, CPLLREF = 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

ADC12QJ800 ADC12DJ800 ADC12SJ800 DNL vs Code
Figure 5-1 DNL vs Code
ADC12QJ800 ADC12DJ800 ADC12SJ800 Input Fullscale vs Input Frequency
Figure 5-3 Input Fullscale vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 Crosstalk vs Input Frequency, Channel B victim
Figure 5-5 Crosstalk vs Input Frequency, Channel B victim
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 897 MHz and -1dBFS
Figure 5-7 Single Tone FFT at 897 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 3247 MHz and -1dBFS
Figure 5-9 Single Tone FFT at 3247 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 897 MHz and -1dBFS
Low Power Mode
Figure 5-11 Single Tone FFT at 897 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 3247 MHz and -1dBFS
Low Power Mode
Figure 5-13 Single Tone FFT at 3247 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 347 MHz and -1dBFS
PLL on, suppression on
Figure 5-15 Single Tone FFT at 347 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 997 MHz and -1dBFS
PLL on, suppression on
Figure 5-17 Single Tone FFT at 997 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 347 MHz and -1dBFS
Low Lower Mode, PLL on, suppression on
Figure 5-19 Single Tone FFT at 347 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 997 MHz and -1dBFS
Low Lower Mode, PLL on, suppression on
Figure 5-21 Single Tone FFT at 997 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Input Frequency
Figure 5-23 SFDR vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 HD3 vs Input Frequency
Figure 5-25 HD3 vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 ENOB vs Input Frequency
Figure 5-27 ENOB vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Sample Rate
Figure 5-29 SFDR vs Sample Rate
ADC12QJ800 ADC12DJ800 ADC12SJ800 ENOB vs Sample Rate
Figure 5-31 ENOB vs Sample Rate
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Input Amplitude
Figure 5-33 SFDR vs Input Amplitude
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Input Frequency and Suppression
CPLL on
Figure 5-35 SFDR vs Input Frequency and Suppression
ADC12QJ800 ADC12DJ800 ADC12SJ800 ENOB vs Input Frequency and Suppression
CPLL on
Figure 5-37 ENOB vs Input Frequency and Suppression
ADC12QJ800 ADC12DJ800 ADC12SJ800 HD2, HD3 and worst non-HD vs Supply Voltage
All supplies moved together
Figure 5-39 HD2, HD3 and worst non-HD vs Supply Voltage
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Clock Amplitude
Figure 5-41 SFDR vs Clock Amplitude
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Temperature
FIN = 347 MHz
Figure 5-43 SNR vs Temperature
ADC12QJ800 ADC12DJ800 ADC12SJ800 HD2 vs Temperature
FIN = 347 MHz
Figure 5-45 HD2 vs Temperature
ADC12QJ800 ADC12DJ800 ADC12SJ800 worst non-HD spur vs Temperature
FIN = 347 MHz
Figure 5-47 worst non-HD spur vs Temperature
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Input Frequency in Low Power Mode
Low Power Mode
Figure 5-49 SFDR vs Input Frequency in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 HD3 vs Input Frequency in Low Power Mode
Low Power Mode
Figure 5-51 HD3 vs Input Frequency in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 ENOB vs Input Frequency in Low Power Mode
Low Power Mode
Figure 5-53 ENOB vs Input Frequency in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Sample Rate in Low Power Mode
Low Power Mode
Figure 5-55 SFDR vs Sample Rate in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 ENOB vs Sample Rate in Low Power Mode
Low Power Mode
Figure 5-57 ENOB vs Sample Rate in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Input Amplitude in Low Power Mode
Low Power Mode
Figure 5-59 SFDR vs Input Amplitude in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Input Frequency
CPLL On, Low Power Mode
Figure 5-61 SFDR vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 ENOB vs Input Frequency
CPLL On, Low Power Mode
Figure 5-63 ENOB vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 HD2, HD3 and worst non-HD vs Supply Voltage
Low Power Mode, all supplies moved together
Figure 5-65 HD2, HD3 and worst non-HD vs Supply Voltage
ADC12QJ800 ADC12DJ800 ADC12SJ800 Two Tone FFT at 1798 MHz
-7 dBFS each tone
Figure 5-67 Two Tone FFT at 1798 MHz
ADC12QJ800 ADC12DJ800 ADC12SJ800 Two Tone FFT at 347 MHz in Low Power Mode
-7 dBFS each tone
Figure 5-69 Two Tone FFT at 347 MHz in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 Two Tone FFT at 3498 MHz in Low Power Mode
-7 dBFS each tone
Figure 5-71 Two Tone FFT at 3498 MHz in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 IMD3 vs Input Frequency in Low Power Mode
Low Power Mode
Figure 5-73 IMD3 vs Input Frequency in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, Power Dissipation vs FS for JMODES 4 - 7
Figure 5-75 Quad Channel, Power Dissipation vs FS for JMODES 4 - 7
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, Power Dissipation vs FS for JMODES 12 - 15
Figure 5-77 Quad Channel, Power Dissipation vs FS for JMODES 12 - 15
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, IVA11 vs FS
Independent of JMODE
Figure 5-79 Quad Channel, IVA11 vs FS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, IVD11 vs FS for JMODES 4 - 7
Independent of Power Mode
Figure 5-81 Quad Channel, IVD11 vs FS for JMODES 4 - 7
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, IVD11 vs FS for JMODES 13-15
Independent of Power Mode
Figure 5-83 Quad Channel, IVD11 vs FS for JMODES 13-15
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, IVA19 vs FS over Modes
Difference to LPBG mode
Figure 5-85 Quad Channel, IVA19 vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, IVD11 vs FS over Modes
Difference to LPBG mode
Figure 5-87 Quad Channel, IVD11 vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, Power Dissipation vs FS for JMODES 4 - 7
Figure 5-89 Dual Channel, Power Dissipation vs FS for JMODES 4 - 7
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, Power Dissipation vs FS for JMODES 12 - 15
Figure 5-91 Dual Channel, Power Dissipation vs FS for JMODES 12 - 15
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, IVA11 vs FS
Independent of JMODE
Figure 5-93 Dual Channel, IVA11 vs FS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, IVD11 vs FS for JMODES 4 - 7
Figure 5-95 Dual Channel, IVD11 vs FS for JMODES 4 - 7
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, IVD11 vs FS for JMODES 13 - 15
Figure 5-97 Dual Channel, IVD11 vs FS for JMODES 13 - 15
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, IVA19 vs FS over Modes
Difference to LPBG mode
Figure 5-99 Dual Channel, IVA19 vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, Power Dissipation vs FS for JMODES 0 - 3
Figure 5-101 Dual Channel, Power Dissipation vs FS for JMODES 0 - 3
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, Power Dissipation vs FS for JMODES 8 - 11
Figure 5-103 Single Channel, Power Dissipation vs FS for JMODES 8 - 11
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, IVA19 vs FS
Independent of JMODE
Figure 5-105 Single Channel, IVA19 vs FS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, IVD11 vs FS for JMODES 0 - 3
Figure 5-107 Single Channel, IVD11 vs FS for JMODES 0 - 3
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, IVD11 vs FS for JMODES 8 - 12
Figure 5-109 Single Channel, IVD11 vs FS for JMODES 8 - 12
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, Power Dissipation vs FS over Modes
Difference to LPBG mode
Figure 5-111 Single Channel, Power Dissipation vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, IVA11 vs FS over Modes
Difference to LPBG mode
Figure 5-113 Single Channel, IVA11 vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Background Calibration Core Transition (midscale)
BG Calibration, midscale input voltage, ADC_SRC_DLY=31, MUX_DLY=30
Figure 5-115 Background Calibration Core Transition (midscale)
ADC12QJ800 ADC12DJ800 ADC12SJ800 Background Calibration Core Transition (AC signal)
BG Calibration, midscale input voltage, ADC_SRC_DLY=31, MUX_DLY=30
Figure 5-117 Background Calibration Core Transition (AC signal)
ADC12QJ800 ADC12DJ800 ADC12SJ800 INL vs Code
Figure 5-2 INL vs Code
ADC12QJ800 ADC12DJ800 ADC12SJ800 Crosstalk vs Input Frequency, Channel A victim
Figure 5-4 Crosstalk vs Input Frequency, Channel A victim
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 347 MHz and -1dBFS
Figure 5-6 Single Tone FFT at 347 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 2097 MHz and -1dBFS
Figure 5-8 Single Tone FFT at 2097 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 347 MHz and -1dBFS
Low Power Mode
Figure 5-10 Single Tone FFT at 347 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 2097 MHz and -1dBFS
Low Power Mode
Figure 5-12 Single Tone FFT at 2097 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 347 MHz and -1dBFS
PLL on, suppression off
Figure 5-14 Single Tone FFT at 347 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 997 MHz and -1dBFS
PLL on, suppression off
Figure 5-16 Single Tone FFT at 997 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 347 MHz and -1dBFS
Low Lower Mode, PLL on, suppression off
Figure 5-18 Single Tone FFT at 347 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Tone FFT at 997 MHz and -1dBFS
Low Lower Mode, PLL on, suppression off
Figure 5-20 Single Tone FFT at 997 MHz and -1dBFS
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Input Frequency
Figure 5-22 SNR vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 HD2 vs Input Frequency
Figure 5-24 HD2 vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 SINAD vs Input Frequency
Figure 5-26 SINAD vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Sample Rate
Figure 5-28 SNR vs Sample Rate
ADC12QJ800 ADC12DJ800 ADC12SJ800 SINAD vs Sample Rate
Figure 5-30 SINAD vs Sample Rate
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Input Amplitude
Figure 5-32 SNR vs Input Amplitude
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Input Frequency and Suppression
CPLL on
Figure 5-34 SNR vs Input Frequency and Suppression
ADC12QJ800 ADC12DJ800 ADC12SJ800 SINAD vs Input Frequency and Suppression
CPLL on
Figure 5-36 SINAD vs Input Frequency and Suppression
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR, SFDR and SINAD vs Supply Voltage
All supplies moved together
Figure 5-38 SNR, SFDR and SINAD vs Supply Voltage
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Clock Amplitude
Figure 5-40 SNR vs Clock Amplitude
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR, SFDR and SINAD vs Reference Frequency with PLL on
Figure 5-42 SNR, SFDR and SINAD vs Reference Frequency with PLL on
ADC12QJ800 ADC12DJ800 ADC12SJ800 SFDR vs Temperature
FIN = 347 MHz
Figure 5-44 SFDR vs Temperature
ADC12QJ800 ADC12DJ800 ADC12SJ800 HD3 vs Temperature
FIN = 347 MHz
Figure 5-46 HD3 vs Temperature
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Input Frequency in Low Power Mode
Low Power Mode
Figure 5-48 SNR vs Input Frequency in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 HD2 vs Input Frequency in Low Power Mode
Low Power Mode
Figure 5-50 HD2 vs Input Frequency in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 SINAD vs Input Frequency in Low Power Mode
Low Power Mode
Figure 5-52 SINAD vs Input Frequency in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Sample Rate in Low Power Mode
Low Power Mode
Figure 5-54 SNR vs Sample Rate in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 SINAD vs Sample Rate in Low Power Mode
Low Power Mode
Figure 5-56 SINAD vs Sample Rate in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Input Amplitude in Low Power Mode
Low Power Mode
Figure 5-58 SNR vs Input Amplitude in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR vs Input Frequency
CPLL On, Low Power Mode
Figure 5-60 SNR vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 SINAD vs Input Frequency
CPLL On, Low Power Mode
Figure 5-62 SINAD vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 SNR, SFDR and SINAD vs Supply Voltage
Low Power Mode, all supplies moved together
Figure 5-64 SNR, SFDR and SINAD vs Supply Voltage
ADC12QJ800 ADC12DJ800 ADC12SJ800 Two Tone FFT at 347 MHz
-7 dBFS each tone
Figure 5-66 Two Tone FFT at 347 MHz
ADC12QJ800 ADC12DJ800 ADC12SJ800 Two Tone FFT at 3498 MHz
-7 dBFS each tone
Figure 5-68 Two Tone FFT at 3498 MHz
ADC12QJ800 ADC12DJ800 ADC12SJ800 Two Tone FFT at 1798 MHz in Low Power Mode
-7 dBFS each tone
Figure 5-70 Two Tone FFT at 1798 MHz in Low Power Mode
ADC12QJ800 ADC12DJ800 ADC12SJ800 IMD3 vs Input Frequency
Figure 5-72 IMD3 vs Input Frequency
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, Power Dissipation vs FS for JMODES 0 - 3
Figure 5-74 Quad Channel, Power Dissipation vs FS for JMODES 0 - 3
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, Power Dissipation vs FS for JMODES 8 - 11
Figure 5-76 Quad Channel, Power Dissipation vs FS for JMODES 8 - 11
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, IVA19 vs FS
Independent of JMODE
Figure 5-78 Quad Channel, IVA19 vs FS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, IVD11 vs FS for JMODES 0 - 3
Independent of Power Mode
Figure 5-80 Quad Channel, IVD11 vs FS for JMODES 0 - 3
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, IVD11 vs FS for JMODES 8-12
Independent of Power Mode
Figure 5-82 Quad Channel, IVD11 vs FS for JMODES 8-12
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, Power Dissipation vs FS over Modes
Difference to LPBG mode
Figure 5-84 Quad Channel, Power Dissipation vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Quad Channel, IVA11 vs FS over Modes
Difference to LPBG mode
Figure 5-86 Quad Channel, IVA11 vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, Power Dissipation vs FS for JMODES 0 - 3
Figure 5-88 Dual Channel, Power Dissipation vs FS for JMODES 0 - 3
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, Power Dissipation vs FS for JMODES 8 - 11
Figure 5-90 Dual Channel, Power Dissipation vs FS for JMODES 8 - 11
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, IVA19 vs FS
Independent of JMODE
Figure 5-92 Dual Channel, IVA19 vs FS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, IVD11 vs FS for JMODES 0 - 3
Figure 5-94 Dual Channel, IVD11 vs FS for JMODES 0 - 3
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, IVD11 vs FS for JMODES 8 - 12
Figure 5-96 Dual Channel, IVD11 vs FS for JMODES 8 - 12
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, Power Dissipation vs FS over Modes
Difference to LPBG mode
Figure 5-98 Dual Channel, Power Dissipation vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Dual Channel, IVA11 vs FS over Modes
Difference to LPBG mode
Figure 5-100 Dual Channel, IVA11 vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, Power Dissipation vs FS for JMODES 4 - 7
Figure 5-102 Single Channel, Power Dissipation vs FS for JMODES 4 - 7
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, Power Dissipation vs FS for JMODES 12 - 15
Figure 5-104 Single Channel, Power Dissipation vs FS for JMODES 12 - 15
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, IVA11 vs FS
Independent of JMODE
Figure 5-106 Single Channel, IVA11 vs FS
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, IVD11 vs FS for JMODES 4 - 7
Figure 5-108 Single Channel, IVD11 vs FS for JMODES 4 - 7
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, IVD11 vs FS for JMODES 13 - 15
Figure 5-110 Single Channel, IVD11 vs FS for JMODES 13 - 15
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, IVA19 vs FS over Modes
Difference to LPBG mode
Figure 5-112 Single Channel, IVA19 vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Single Channel, IVD11 vs FS over Modes
Difference to LPBG mode
Figure 5-114 Single Channel, IVD11 vs FS over Modes
ADC12QJ800 ADC12DJ800 ADC12SJ800 Background Calibration Core Transition (voltage offset)
BG Calibration, midscale input voltage, ADC_SRC_DLY=31, MUX_DLY=30
Figure 5-116 Background Calibration Core Transition (voltage offset)
ADC12QJ800 ADC12DJ800 ADC12SJ800 Background Calibration Core Transition (AC signal zoomed)
BG Calibration, midscale input voltage, ADC_SRC_DLY=31, MUX_DLY=30
Figure 5-118 Background Calibration Core Transition (AC signal zoomed)